RTL: fixed issue with memory access alignment

BrunoLevy · Apr 30, 2022 · 726d888 · 726d888
1 parent 5010d37
commit 726d888
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v b/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v
@@ -235,7 +235,7 @@ module FemtoRV32 #(
    // 32 bits, so we deactivate width test for mem_addr and writeBackData
 
    assign mem_addr = state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ?
-                     PC : loadstore_addr ;
+                     PC : {loadstore_addr[ADDR_WIDTH-1:2], 2'b00} ;
 
    /***************************************************************************/
    // The value written back to the register file.