chore: release v0.12.0-beta.2

Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "aluvm"
 description = "Functional registry-based RISC virtual machine"
-version = "0.12.0-beta.1"
+version = "0.12.0-beta.2"
 authors = ["Dr Maxim Orlovsky <[email protected]>"]
 repository = "https://github.com/aluvm/rust-aluvm"
 homepage = "https://aluvm.org"

src/core/core.rs

@@ -126,9 +126,9 @@ pub struct Core<
 #[strict_type(lib = LIB_NAME_ALUVM)]
 #[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
 pub struct CoreConfig {
-    /// Initial value for the [`Core::ch`] flag.
+    /// Initial value for the `CH` register.
     pub halt: bool,
-    /// Initial value for the [`Core::cl`] flag.
+    /// Initial value for the `CL` register.
     pub complexity_lim: Option<u64>,
 }
 
@@ -141,15 +141,20 @@ impl Default for CoreConfig {
     ///
     /// - [`CoreConfig::halt`]
     /// - [`CoreConfig::complexity_lim`]
-    /// - [`CoreConfig::field_order`]
     fn default() -> Self { CoreConfig { halt: true, complexity_lim: None } }
 }
 
+impl<Id: SiteId, Cx: CoreExt, const CALL_STACK_SIZE: usize> Default
+    for Core<Id, Cx, CALL_STACK_SIZE>
+{
+    fn default() -> Self { Core::new() }
+}
+
 impl<Id: SiteId, Cx: CoreExt, const CALL_STACK_SIZE: usize> Core<Id, Cx, CALL_STACK_SIZE> {
     /// Initializes registers. Sets `st0` to `true`, counters to zero, call stack to empty and the
     /// rest of registers to `None` value.
     ///
-    /// An alias for [`AluCore::with`]`(`[`CoreConfig::default()`]`)`.
+    /// An alias for [`Core::with`]`(`[`CoreConfig::default()`]`)`.
     #[inline]
     pub fn new() -> Self {
         assert!(CALL_STACK_SIZE <= CALL_STACK_SIZE_MAX as usize, "Call stack size is too large");

src/core/mod.rs

@@ -24,6 +24,7 @@
 
 //! AluVM registers system
 
+#[allow(clippy::module_inception)]
 mod core;
 mod microcode;
 mod util;

src/core/util.rs

@@ -35,17 +35,20 @@ pub trait Register: Copy + Ord + Debug + Display {
 
 #[derive(Debug)]
 pub enum NoRegs {}
+#[allow(clippy::non_canonical_clone_impl)]
 impl Clone for NoRegs {
     fn clone(&self) -> Self { unreachable!() }
 }
 impl Copy for NoRegs {}
+#[allow(clippy::non_canonical_clone_impl)]
 impl PartialEq for NoRegs {
     fn eq(&self, _: &Self) -> bool { unreachable!() }
 }
 impl Eq for NoRegs {}
 impl Ord for NoRegs {
     fn cmp(&self, _: &Self) -> Ordering { unreachable!() }
 }
+#[allow(clippy::non_canonical_partial_ord_impl)]
 impl PartialOrd for NoRegs {
     fn partial_cmp(&self, _: &Self) -> Option<Ordering> { unreachable!() }
 }

src/isa/arch.rs

@@ -58,7 +58,7 @@ impl From<&'static str> for IsaId {
     fn from(id: &'static str) -> Self { Self(RString::from(id)) }
 }
 
-/// Reserved instruction, which equal to [`ControlFlowOp::Fail`].
+/// Reserved instruction, which equal to [`crate::ExecStep::FailHalt`].
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Display, Default)]
 #[display("halt    {0:#02X}#h")]
 pub struct ReservedInstr(/** Reserved instruction op code value */ pub(super) u8);

src/isa/ctrl/exec.rs

@@ -69,8 +69,8 @@ impl<Id: SiteId> Instruction<Id> for Instr<Id> {
         _: &Self::Context<'_>,
     ) -> ExecStep<Site<Id>> {
         match self {
-            Instr::Ctrl(instr) => instr.exec(site, core, &mut ()),
-            Instr::Reserved(instr) => instr.exec(site, core, &mut ()),
+            Instr::Ctrl(instr) => instr.exec(site, core, &()),
+            Instr::Reserved(instr) => instr.exec(site, core, &()),
         }
     }
 }
@@ -153,7 +153,7 @@ impl<Id: SiteId> Instruction<Id> for CtrlInstr<Id> {
             let Some(pos) = current.offset.checked_add_signed(shift as i16) else {
                 return ExecStep::FailHalt;
             };
-            return ExecStep::Jump(pos);
+            ExecStep::Jump(pos)
         };
 
         match *self {

src/isa/instr.rs

@@ -62,7 +62,7 @@ pub trait Instruction<Id: SiteId>: Display + Debug + Bytecode<Id> {
     type Context<'ctx>;
 
     fn isa_ext() -> TinyOrdSet<IsaId> {
-        let iter = Self::ISA_EXT.into_iter().copied().map(IsaId::from);
+        let iter = Self::ISA_EXT.iter().copied().map(IsaId::from);
         TinyOrdSet::from_iter_checked(iter)
     }
 

src/library/lib.rs

@@ -35,7 +35,7 @@ use strict_encoding::{StrictDeserialize, StrictSerialize};
 use crate::core::SiteId;
 use crate::{IsaId, Site, LIB_NAME_ALUVM};
 
-pub const LIB_ID_TAG: &'static str = "urn:ubideco:aluvm:lib:v01#241020";
+pub const LIB_ID_TAG: &str = "urn:ubideco:aluvm:lib:v01#241020";
 
 /// Unique identifier for an AluVM library.
 #[derive(Wrapper, Copy, Clone, Ord, PartialOrd, Eq, PartialEq, Hash, Default, Debug, From)]

src/library/marshaller.rs

@@ -423,7 +423,7 @@ where
         if len >= u16::MAX as usize {
             return Err(MarshallError::DataExceedsLimit(len));
         }
-        let offset = self.write_unique(&data)?;
+        let offset = self.write_unique(data)?;
         self.write_word(offset)?;
         self.write_word(len as u16)
     }

src/vm.rs

@@ -31,7 +31,7 @@ use crate::isa::{Instr, Instruction};
 use crate::library::{Lib, LibId, LibSite};
 
 /// Alu virtual machine providing single-core execution environment
-#[derive(Clone, Debug)]
+#[derive(Clone, Debug, Default)]
 pub struct Vm<Isa = Instr<LibId>>
 where Isa: Instruction<LibId>
 {