isa: asm fix RegAR macro

AluVM · Apr 22, 2024 · 4058c09 · 4058c09
1 parent 3c4d6c2
commit 4058c09
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Showing 2 changed files with 58 additions and 4 deletions.
diff --git a/src/isa/exec.rs b/src/isa/exec.rs
@@ -1320,7 +1320,7 @@ impl InstructionSet for BytesOp {
                     let offset = regs.a16[*offset as u8 as usize].filter(|e| *e < s_len)?;
                     let end = offset
                         .checked_add(dst.layout().bytes())
-                        .filter(|e| *e < s_len)
+                        .filter(|e| *e <= s_len)
                         .unwrap_or_else(|| {
                             regs.st0 = false;
                             s_len

diff --git a/src/isa/macros.rs b/src/isa/macros.rs
@@ -71,7 +71,7 @@ macro_rules! aluasm_isa {
             MergeFlag, MoveOp, PutOp, RoundingFlag, Secp256k1Op, SignFlag, NoneEqFlag
         };
         use ::aluvm::reg::{
-            Reg16, Reg32, Reg8, RegA, RegA2, RegBlockAFR, RegBlockAR, RegF, RegR, RegS,
+            Reg16, Reg32, Reg8, RegA, RegA2, RegAR, RegBlockAFR, RegBlockAR, RegF, RegR, RegS,
             NumericRegister,
         };
         use ::aluvm::library::LibSite;
@@ -220,15 +220,15 @@ macro_rules! instr {
     (extr s16[$idx:literal], $reg:ident[$reg_idx:literal], a16[$offset_idx:literal]) => {
         Instr::Bytes(BytesOp::Extr(
             RegS::from($idx),
-            $crate::_reg_ty!(Reg, $reg),
+            $crate::_reg_tyar!($reg),
             $crate::_reg_idx16!($reg_idx),
             $crate::_reg_idx16!($offset_idx),
         ))
     };
     (inj s16[$idx:literal], $reg:ident[$reg_idx:literal], a16[$offset_idx:literal]) => {
         Instr::Bytes(BytesOp::Inj(
             RegS::from($idx),
-            $crate::_reg_ty!(Reg, $reg),
+            $crate::_reg_tyar!($reg),
             $crate::_reg_idx16!($reg_idx),
             $crate::_reg_idx16!($offset_idx),
         ))
@@ -1355,6 +1355,60 @@ macro_rules! _reg_tyr {
     };
 }
 
+#[doc(hidden)]
+#[macro_export]
+macro_rules! _reg_tyar {
+    (a8) => {
+        RegAR::A(RegA::A8)
+    };
+    (a16) => {
+        RegAR::A(RegA::A16)
+    };
+    (a32) => {
+        RegAR::A(RegA::A32)
+    };
+    (a64) => {
+        RegAR::A(RegA::A64)
+    };
+    (a128) => {
+        RegAR::A(RegA::A128)
+    };
+    (a256) => {
+        RegAR::A(RegA::A256)
+    };
+    (a512) => {
+        RegAR::A(RegA::A512)
+    };
+    (a1024) => {
+        RegAR::A(RegA::A1024)
+    };
+
+    (r128) => {
+        RegAR::R(RegR::R128)
+    };
+    (r160) => {
+        RegAR::R(RegR::R160)
+    };
+    (r256) => {
+        RegAR::R(RegR::R256)
+    };
+    (r512) => {
+        RegAR::R(RegR::R512)
+    };
+    (r1024) => {
+        RegAR::R(RegR::R1024)
+    };
+    (r2048) => {
+        RegAR::R(RegR::R2048)
+    };
+    (r4096) => {
+        RegAR::R(RegR::R4096)
+    };
+    (r8192) => {
+        RegAR::R(RegR::R8192)
+    };
+}
+
 #[doc(hidden)]
 #[macro_export]
 macro_rules! _reg_idx {