Add changes in src and test directories

src/cts/src/HTreeBuilder.cpp

@@ -1776,9 +1776,10 @@ void HTreeBuilder::createClockSubNets()
   bool isFirstPoint = true;
   topLevelTopology.forEachBranchingPoint([&](unsigned idx,
                                              Point<double> branchPoint) {
-    // If the branch point has no sinks that will be connected to
+    // If the branch point is a leaf and has no sinks that will be connected to
     // it don't create a clock sub net for it
-    if (topLevelTopology.getBranchSinksLocations(idx).empty()) {
+    if (topologyForEachLevel_.size() == 1
+        && topLevelTopology.getBranchSinksLocations(idx).empty()) {
       return;
     }
     Point<double> legalBranchPoint
@@ -1829,9 +1830,10 @@ void HTreeBuilder::createClockSubNets()
     isFirstPoint = true;
     topology.forEachBranchingPoint([&](unsigned idx,
                                        Point<double> branchPoint) {
-      // If the branch point has no sinks that will be connected
+      // If the branch point is a leaf and has no sinks that will be connected
       // to it don't create a clock sub net for it
-      if (topology.getBranchSinksLocations(idx).empty()) {
+      if ((levelIdx == topologyForEachLevel_.size() - 1)
+          && topology.getBranchSinksLocations(idx).empty()) {
         return;
       }
       unsigned parentIdx = topology.getBranchingPointParentIdx(idx);

src/cts/src/TritonCTS.cpp

@@ -1578,12 +1578,8 @@ bool TritonCTS::hasInsertionDelay(odb::dbInst* inst, odb::dbMTerm* mterm)
       sta::LibertyPort* libPort
           = libCell->findLibertyPort(mterm->getConstName());
       if (libPort) {
-        const float rise = libPort->clkTreeDelay(
-            0.0, sta::RiseFall::rise(), sta::MinMax::max());
-        const float fall = libPort->clkTreeDelay(
-            0.0, sta::RiseFall::fall(), sta::MinMax::max());
-
-        if (rise != 0 || fall != 0) {
+        sta::RiseFallMinMax insDelays = libPort->clkTreeDelays();
+        if (insDelays.hasValue()) {
           return true;
         }
       }
@@ -1606,15 +1602,14 @@ double TritonCTS::computeInsertionDelay(const std::string& name,
   if (libCell) {
     sta::LibertyPort* libPort = libCell->findLibertyPort(mterm->getConstName());
     if (libPort) {
-      const float rise = libPort->clkTreeDelay(
-          0.0, sta::RiseFall::rise(), sta::MinMax::max());
-      const float fall = libPort->clkTreeDelay(
-          0.0, sta::RiseFall::fall(), sta::MinMax::max());
-
-      if (rise != 0 || fall != 0) {
+      sta::RiseFallMinMax insDelays = libPort->clkTreeDelays();
+      if (insDelays.hasValue()) {
         // use average of max rise and max fall
         // TODO: do we need to look at min insertion delays?
-        double delayPerSec = (rise + fall) / 2.0;
+        double delayPerSec
+            = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max())
+               + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max()))
+              / 2.0;
         // convert delay to length because HTree uses lengths
         sta::Corner* corner = openSta_->cmdCorner();
         double capPerMicron = resizer_->wireSignalCapacitance(corner) * 1e-6;
@@ -1976,13 +1971,12 @@ void TritonCTS::computeAveSinkArrivals(TreeBuilder* builder)
       sta::LibertyPort* libPort
           = libCell->findLibertyPort(mterm->getConstName());
       if (libPort) {
-        const float rise = libPort->clkTreeDelay(
-            0.0, sta::RiseFall::rise(), sta::MinMax::max());
-        const float fall = libPort->clkTreeDelay(
-            0.0, sta::RiseFall::fall(), sta::MinMax::max());
-
-        if (rise != 0 || fall != 0) {
-          ins_delay = (rise + fall) / 2.0;
+        sta::RiseFallMinMax insDelays = libPort->clkTreeDelays();
+        if (insDelays.hasValue()) {
+          ins_delay
+              = (insDelays.value(sta::RiseFall::rise(), sta::MinMax::max())
+                 + insDelays.value(sta::RiseFall::fall(), sta::MinMax::max()))
+                / 2.0;
         }
       }
     }

src/dbSta/include/db_sta/dbNetwork.hh

@@ -202,7 +202,6 @@ class dbNetwork : public ConcreteNetwork
   Cell* cell(const Instance* instance) const override;
   Instance* parent(const Instance* instance) const override;
   bool isLeaf(const Instance* instance) const override;
-  Port* findPort(const Cell* cell, const char* name) const override;
   Instance* findInstance(const char* path_name) const override;
   Instance* findChild(const Instance* parent, const char* name) const override;
   InstanceChildIterator* childIterator(const Instance* instance) const override;

src/dbSta/src/CMakeLists.txt

@@ -64,24 +64,23 @@ swig_lib(NAME          dbSta
                        ${ODB_HOME}/src/swig/common
                        ${ODB_HOME}/src/swig/tcl
                        ${ODB_HOME}/include
-         SCRIPTS       ${OPENSTA_HOME}/tcl/CmdArgs.tcl
+         SCRIPTS       ${OPENSTA_HOME}/tcl/Graph.tcl
+                       ${OPENSTA_HOME}/tcl/Liberty.tcl
+                       ${OPENSTA_HOME}/tcl/CmdArgs.tcl
                        ${OPENSTA_HOME}/tcl/CmdUtil.tcl
                        ${OPENSTA_HOME}/tcl/Property.tcl
-                       ${OPENSTA_HOME}/spice/WriteSpice.tcl
+                       ${OPENSTA_HOME}/tcl/WritePathSpice.tcl
+                       ${OPENSTA_HOME}/tcl/Network.tcl
+                       ${OPENSTA_HOME}/tcl/NetworkEdit.tcl
+                       ${OPENSTA_HOME}/tcl/Sdc.tcl
+                       ${OPENSTA_HOME}/tcl/Search.tcl
                        ${OPENSTA_HOME}/tcl/Variables.tcl
                        ${OPENSTA_HOME}/tcl/Sta.tcl
                        ${OPENSTA_HOME}/tcl/Splash.tcl
                        ${OPENSTA_HOME}/dcalc/DelayCalc.tcl
-                       ${OPENSTA_HOME}/graph/Graph.tcl
-                       ${OPENSTA_HOME}/liberty/Liberty.tcl
-                       ${OPENSTA_HOME}/network/Network.tcl
-                       ${OPENSTA_HOME}/network/NetworkEdit.tcl
                        ${OPENSTA_HOME}/parasitics/Parasitics.tcl
                        ${OPENSTA_HOME}/power/Power.tcl
-                       ${OPENSTA_HOME}/sdc/Sdc.tcl
                        ${OPENSTA_HOME}/sdf/Sdf.tcl
-                       ${OPENSTA_HOME}/search/Search.tcl
-                       ${OPENSTA_HOME}/tcl/Util.tcl
                        ${DBSTA_HOME}/src/dbReadVerilog.tcl
                        ${DBSTA_HOME}/src/dbSta.tcl
 )
@@ -93,13 +92,6 @@ target_sources(dbSta
     PathRenderer.cc
 )
 
-# sta warnings
-target_compile_options(dbSta
-  PRIVATE
-    -Wno-redundant-decls
-    -Wno-unused-function
-)
-
 target_include_directories(dbSta
   PUBLIC
     ../include

src/dbSta/src/dbNetwork.cc

@@ -315,48 +315,26 @@ class DbInstanceNetIterator : public InstanceNetIterator
   const dbNetwork* network_;
   dbSet<dbNet>::iterator iter_;
   dbSet<dbNet>::iterator end_;
-  dbSet<dbModNet>::iterator mod_net_iter_;
-  dbSet<dbModNet>::iterator mod_net_end_;
 };
 
 DbInstanceNetIterator::DbInstanceNetIterator(const Instance* instance,
                                              const dbNetwork* network)
     : network_(network)
 {
-  if (network_->hasHierarchy()) {
-    dbInst* db_inst;
-    dbModInst* mod_inst;
-    network_->staToDb(instance, db_inst, mod_inst);
-    if (mod_inst) {
-      dbModule* master = mod_inst->getMaster();
-      dbSet<dbModNet> nets = master->getModNets();
-      mod_net_iter_ = nets.begin();
-      mod_net_end_ = nets.end();
-    }
-  } else {
-    if (instance == network->topInstance()) {
-      dbSet<dbNet> nets = network->block()->getNets();
-      iter_ = nets.begin();
-      end_ = nets.end();
-    }
+  if (instance == network->topInstance()) {
+    dbSet<dbNet> nets = network->block()->getNets();
+    iter_ = nets.begin();
+    end_ = nets.end();
   }
 }
 
 bool DbInstanceNetIterator::hasNext()
 {
-  if (network_->hasHierarchy()) {
-    return mod_net_iter_ != mod_net_end_;
-  }
   return iter_ != end_;
 }
 
 Net* DbInstanceNetIterator::next()
 {
-  if (network_->hasHierarchy()) {
-    dbModNet* net = *mod_net_iter_;
-    mod_net_iter_++;
-    return network_->dbToSta(net);
-  }
   dbNet* net = *iter_;
   iter_++;
   return network_->dbToSta(net);
@@ -832,22 +810,6 @@ Instance* dbNetwork::parent(const Instance* instance) const
   return top_instance_;
 }
 
-Port* dbNetwork::findPort(const Cell* cell, const char* name) const
-{
-  if (hierarchy_) {
-    dbMaster* db_master;
-    dbModule* db_module;
-    staToDb(cell, db_master, db_module);
-    if (db_module) {
-      dbModBTerm* mod_bterm = db_module->findModBTerm(name);
-      Port* ret = dbToSta(mod_bterm);
-      return ret;
-    }
-  }
-  const ConcreteCell* ccell = reinterpret_cast<const ConcreteCell*>(cell);
-  return reinterpret_cast<Port*>(ccell->findPort(name));
-}
-
 bool dbNetwork::isLeaf(const Instance* instance) const
 {
   if (instance == top_instance_) {
@@ -1143,13 +1105,14 @@ PortDirection* dbNetwork::direction(const Port* port) const
   if (bterm) {
     PortDirection* dir = dbToSta(bterm->getSigType(), bterm->getIoType());
     return dir;
-  }
-  if (modbterm) {
+  } else if (modbterm) {
     PortDirection* dir = dbToSta(modbterm->getSigType(), modbterm->getIoType());
     return dir;
+  } else {
+    const ConcretePort* cport = reinterpret_cast<const ConcretePort*>(port);
+    return cport->direction();
   }
-  const ConcretePort* cport = reinterpret_cast<const ConcretePort*>(port);
-  return cport->direction();
+  return PortDirection::unknown();
 }
 
 PortDirection* dbNetwork::direction(const Pin* pin) const
@@ -1617,7 +1580,7 @@ void dbNetwork::makeCell(Library* library, dbMaster* master)
     }
   }
 
-  std::unique_ptr<CellPortIterator> port_iter{portIterator(cell)};
+  CellPortIterator* port_iter = portIterator(cell);
   while (port_iter->hasNext()) {
     Port* cur_port = port_iter->next();
     registerConcretePort(cur_port);
@@ -1653,7 +1616,7 @@ void dbNetwork::makeTopCell()
   });
 
   // record the top level ports
-  std::unique_ptr<CellPortIterator> port_iter{portIterator(top_cell_)};
+  CellPortIterator* port_iter = portIterator(top_cell_);
   while (port_iter->hasNext()) {
     Port* cur_port = port_iter->next();
     registerConcretePort(cur_port);
@@ -1758,23 +1721,13 @@ Instance* dbNetwork::makeInstance(LibertyCell* cell,
                                   const char* name,
                                   Instance* parent)
 {
-  const char* cell_name = cell->name();
   if (parent == top_instance_) {
+    const char* cell_name = cell->name();
     dbMaster* master = db_->findMaster(cell_name);
     if (master) {
       dbInst* inst = dbInst::create(block_, master, name);
       return dbToSta(inst);
     }
-  } else {
-    dbInst* db_inst = nullptr;
-    dbModInst* mod_inst = nullptr;
-    staToDb(parent, db_inst, mod_inst);
-    if (mod_inst) {
-      dbMaster* master = db_->findMaster(cell_name);
-      dbModule* parent = mod_inst->getMaster();
-      dbInst* inst = dbInst::create(block_, master, name, false, parent);
-      return dbToSta(inst);
-    }
   }
   return nullptr;
 }
@@ -2110,6 +2063,7 @@ void dbNetwork::staToDb(const Term* term,
   }
 }
 
+// Primary -- needs concrete test
 void dbNetwork::staToDb(const Cell* cell,
                         dbMaster*& master,
                         dbModule*& module) const
@@ -2150,7 +2104,7 @@ dbMTerm* dbNetwork::staToDb(const Port* port) const
 
 dbBTerm* dbNetwork::isTopPort(const Port* port) const
 {
-  std::unique_ptr<CellPortIterator> port_iter{portIterator(top_cell_)};
+  CellPortIterator* port_iter = portIterator(top_cell_);
   while (port_iter->hasNext()) {
     if (port == port_iter->next()) {
       const ConcretePort* cport = reinterpret_cast<const ConcretePort*>(port);

src/dbSta/src/dbReadVerilog.cc

@@ -278,7 +278,7 @@ void Verilog2db::recordBusPortsOrder()
   // Use a property to annotate the bus names as msb or lsb first for writing
   // verilog.
   Cell* top_cell = network_->cell(network_->topInstance());
-  std::unique_ptr<CellPortIterator> bus_iter{network_->portIterator(top_cell)};
+  CellPortIterator* bus_iter = network_->portIterator(top_cell);
   while (bus_iter->hasNext()) {
     Port* port = bus_iter->next();
     if (network_->isBus(port)) {
@@ -290,6 +290,7 @@ void Verilog2db::recordBusPortsOrder()
       odb::dbBoolProperty::create(block_, key.c_str(), from > to);
     }
   }
+  delete bus_iter;
 }
 
 dbModule* Verilog2db::makeUniqueDbModule(const char* name)
@@ -367,7 +368,7 @@ void Verilog2db::makeDbModule(
     if (hierarchy_) {
       dbBusPort* dbbusport = nullptr;
       // make the module ports
-      std::unique_ptr<CellPortIterator> cp_iter{network_->portIterator(cell)};
+      CellPortIterator* cp_iter = network_->portIterator(cell);
       while (cp_iter->hasNext()) {
         Port* port = cp_iter->next();
         if (network_->isBus(port)) {

src/dbSta/src/dbSdcNetwork.cc

@@ -180,7 +180,7 @@ void dbSdcNetwork::findMatchingPins(const Instance* instance,
 {
   if (instance != network_->topInstance()) {
     Cell* cell = network_->cell(instance);
-    std::unique_ptr<CellPortIterator> port_iter{network_->portIterator(cell)};
+    CellPortIterator* port_iter = network_->portIterator(cell);
     while (port_iter->hasNext()) {
       Port* port = port_iter->next();
       const char* port_name = network_->name(port);
@@ -214,6 +214,7 @@ void dbSdcNetwork::findMatchingPins(const Instance* instance,
         }
       }
     }
+    delete port_iter;
   }
 }
 

src/dbSta/src/dbSta.i

@@ -5,7 +5,6 @@
 #include "db_sta/dbNetwork.hh"
 #include "db_sta/MakeDbSta.hh"
 #include "ord/OpenRoad.hh"
-#include "sta/Property.hh"
 #include "sta/VerilogWriter.hh"
 
 namespace ord {
@@ -21,18 +20,12 @@ using sta::Instance;
 %include "../../Exception.i"
 // OpenSTA swig files
 %include "tcl/StaTclTypes.i"
+%include "tcl/StaTcl.i"
+%include "tcl/NetworkEdit.i"
+%include "sdf/Sdf.i"
 %include "dcalc/DelayCalc.i"
-%include "graph/Graph.i"
-%include "liberty/Liberty.i"
-%include "network/Network.i"
-%include "network/NetworkEdit.i"
 %include "parasitics/Parasitics.i"
 %include "power/Power.i"
-%include "sdc/Sdc.i"
-%include "sdf/Sdf.i"
-%include "search/Search.i"
-%include "spice/WriteSpice.i"
-%include "util/Util.i"
 
 %inline %{
 
@@ -129,14 +122,6 @@ sta_to_db_pin(Pin *pin)
   return iterm;
 }
 
-Port *
-sta_pin_to_port(Pin *pin)
-{
-  ord::OpenRoad *openroad = ord::getOpenRoad();
-  sta::dbNetwork *db_network = openroad->getDbNetwork();
-  return db_network->port(pin);
-}
-
 odb::dbNet *
 sta_to_db_net(Net *net)
 {

src/dbSta/test/hier2_out.vok

@@ -5,6 +5,7 @@ module top (a,
  input b;
  output out;
 
+ wire a_int;
 
  INV_X1 _4_ (.ZN(a_int),
     .A(a));