some stuff

src/pcf.rs

@@ -23,7 +23,7 @@ impl PcfFile {
     pub fn pin(&self, name: &str) -> Option<u32> {
         self.map.get(name).cloned()
     }
-    pub fn pinvec(&self, name: &str, index: u32) -> Option<u32> {
+    pub fn pinvec(&self, name: &str, index: usize) -> Option<u32> {
         // construct a name of the form <name>[<index>]
         let realname = format!("{name}[{index}]");
         self.map.get(&realname).cloned()

src/yosys_parser.rs

@@ -8,7 +8,7 @@ use std::str;
 // Custom deserializer for the strange string of binary
 // not sure what the format is.
 
-#[derive(Debug, Serialize, Clone, Deserialize)]
+#[derive(Debug, Serialize, Clone, Deserialize, Hash, PartialEq, Eq, PartialOrd, Ord)]
 #[serde(transparent)]
 pub struct Net(u32);
 
@@ -214,9 +214,34 @@ impl YosysDoc {
         }
         nl
     }
+    pub fn construct_netmap(&self, pcf: &PcfFile) -> Option<HashMap<Net, u32>> {
+        let mut map = HashMap::new();
+        for (name, m) in &self.modules {
+            println!("Processing Module {}", name);
+            for (name, port) in &m.ports {
+                println!("Found port {}", name);
+                let p = match port {
+                    Port::Input(p) => p,
+                    Port::Output(p) => p,
+                };
+                if p.bits.len() == 1 {
+                    println!("Adding {} to pinmap", name);
+                    map.insert(p.bits[0].clone(), pcf.pin(name)?);
+                } else {
+                    for (idx, net_num) in p.bits.iter().enumerate() {
+                        println!("Adding {}[{}] to pinmap", name, idx);
+                        map.insert(net_num.clone(), pcf.pinvec(name, idx)?);
+                    }
+                };
+            }
+        }
+
+        Some(map)
+    }
 }
 
 /* constraint mapping pipeline
+ * w
  * take yosys document -> look at top-level module ports
  * use constraints pcf file to map. This creates a HashMap<Net, u32> for mapping nets to pins.
  * only do this for *ports*, not cells.
@@ -227,9 +252,6 @@ enum PortValue {
     Register(Vec<u32>),
 }
 
-/*
- * this fn 
- */
 fn port_lookup(name: &str, cell: &AnyCell, pcf: &PcfFile) -> Option<PortValue> {
     match cell {
         AnyCell::Input(p) => {
@@ -250,3 +272,4 @@ fn port_lookup(name: &str, cell: &AnyCell, pcf: &PcfFile) -> Option<PortValue> {
         _ => None
     }
 }
+