reverting csr_regfile changes

10x-Engineers · Sep 11, 2023 · eaec24c · eaec24c
1 parent ef1a66a
commit eaec24c
Showing 1 changed file with 3 additions and 4 deletions.
diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
@@ -153,7 +153,7 @@ module csr_regfile import ariane_pkg::*; #(
     riscv::pmpcfg_t [15:0]    pmpcfg_q,  pmpcfg_d;
     logic [15:0][riscv::PLEN-3:0]        pmpaddr_q,  pmpaddr_d;
     logic [MHPMCounterNum+3-1:0] mcountinhibit_d,mcountinhibit_q;
-
+    int index;
     localparam riscv::xlen_t IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) <<  0)                // A - Atomic Instructions extension
                                      | (riscv::XLEN'(CVA6Cfg.RVC) <<  2)                // C - Compressed extension
                                      | (riscv::XLEN'(CVA6Cfg.RVD) <<  3)                // D - Double precsision floating-point extension
@@ -189,7 +189,7 @@ module csr_regfile import ariane_pkg::*; #(
         read_access_exception = 1'b0;
         csr_rdata = '0;
         perf_addr_o = csr_addr.address[11:0];
-
+        index = '0;
         if (csr_read) begin
             unique case (csr_addr.address)
                 riscv::CSR_FFLAGS: begin
@@ -465,8 +465,7 @@ module csr_regfile import ariane_pkg::*; #(
                 riscv::CSR_PMPADDR14,
                 riscv::CSR_PMPADDR15: begin
                     // index is specified by the last byte in the address
-                    automatic int index = {{28{1'b0}},csr_addr.csr_decode.address[3:0]};                    // Important: we only support granularity 8 bytes (G=1)
-                    // -> last bit of pmpaddr must be set 0/1 based on the mode:
+                    index = {{28{1'b0}},csr_addr.csr_decode.address[3:0]};                      // -> last bit of pmpaddr must be set 0/1 based on the mode:
                     // NA4, NAPOT: 1
                     // TOR, OFF:   0
                     if (pmpcfg_q[index].addr_mode[1] == 1'b1)