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Fix CSR coverage model & HVP (openhwgroup#1751)
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AyoubJalali authored and rohan-10xe committed Jan 23, 2024
1 parent 6b9d29a commit e2ae14b
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Showing 4 changed files with 38 additions and 12 deletions.
4 changes: 2 additions & 2 deletions verif/env/uvme/cov/uvme_cva6_config_covg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,7 @@ covergroup cg_cva6_config(string name) with function sample();
bins NrStorePipeRegs ={0};
}
cp_NrLoadBufEntries : coverpoint cva6_config_pkg::CVA6ConfigNrLoadBufEntries {
bins NrLoadBufEntries ={2};
bins NrLoadBufEntries ={1};
}
cp_InstrTlbEntries : coverpoint cva6_config_pkg::CVA6ConfigInstrTlbEntries {
bins InstrTlbEntries ={2};
Expand All @@ -130,7 +130,7 @@ covergroup cg_cva6_config(string name) with function sample();
bins DataTlbEntries ={2};
}
cp_RASDepth : coverpoint cva6_config_pkg::CVA6ConfigRASDepth {
bins RASDepth ={0};
bins RASDepth ={2};
}
cp_BTBEntries : coverpoint cva6_config_pkg::CVA6ConfigBTBEntries {
bins BTBEntries ={0};
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19 changes: 10 additions & 9 deletions verif/env/uvme/reg/cva6_csr_reg_file.sv
Original file line number Diff line number Diff line change
Expand Up @@ -96,22 +96,22 @@ class reg_mstatus extends csr_reg;
MPRV: coverpoint data[17:17];
XS: coverpoint data[16:15] {
bins legal_values[] = {0};
//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
}
FS: coverpoint data[14:13] {
bins legal_values[] = {0};
//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
}
MPP: coverpoint data[12:11];
VS: coverpoint data[10:9] {
bins legal_values[] = {0};
//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
}
SPP: coverpoint data[8:8];
MPIE: coverpoint data[7:7];
UBE: coverpoint data[6:6] {
bins legal_values[] = {0};
//GIT ISSUE #1417: illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
illegal_bins illegal_values = {[0:$]} with (!(item inside {0}));
}
SPIE: coverpoint data[5:5];
MIE: coverpoint data[3:3];
Expand Down Expand Up @@ -256,8 +256,9 @@ class reg_misa extends csr_reg;
illegal_bins illegal_values = {[0:$]} with (!(item inside {1}));
}
Extensions: coverpoint data[25:0] {
bins legal_values[] = {26'h0001104};
illegal_bins illegal_values = {[0:$]} with (!(item inside {26'h0001104}));
bins legal_values[] = {26'h0001106};
//TODO : Fix issue#1734
//illegal_bins illegal_values = {[0:$]} with (!(item inside {26'h0001106}));
}
endgroup

Expand All @@ -269,8 +270,8 @@ class reg_misa extends csr_reg;
bins illegal_values[] = {[0:$]} with (!(item inside {1}));
}
Extensions: coverpoint data[25:0] {
bins legal_values[] = {26'h0001104};
bins illegal_values[3] = {[0:$]} with (!(item inside {26'h0001104}));
bins legal_values[] = {26'h0001106};
bins illegal_values[3] = {[0:$]} with (!(item inside {26'h0001106}));
}
endgroup

Expand All @@ -297,7 +298,7 @@ class reg_misa extends csr_reg;
MXL.configure(.parent(this), .size(2), .lsb_pos(30), .access("RW"), .volatile(0), .reset(0), .has_reset(1), .is_rand(1), .individually_accessible(0));

Extensions = uvm_reg_field::type_id::create("Extensions");
Extensions.configure(.parent(this), .size(26), .lsb_pos(0), .access("RW"), .volatile(0), .reset(37782532), .has_reset(1), .is_rand(1), .individually_accessible(0));
Extensions.configure(.parent(this), .size(26), .lsb_pos(0), .access("RW"), .volatile(0), .reset(26'h0001106), .has_reset(1), .is_rand(1), .individually_accessible(0));
endfunction

virtual function void sample(uvm_reg_data_t data, uvm_reg_data_t byte_en,bit is_read, uvm_reg_map map);
Expand Down
2 changes: 1 addition & 1 deletion verif/sim/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -253,7 +253,7 @@ vcs-uvm:
$(tool_path)/spike-dasm --isa=$(variant) < ./vcs_results/default/vcs.d/trace_rvfi_hart_00.dasm > $(log)

generate_cov_dash:
urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp -tgl portsonly
urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes weight+description+Comment -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -tgl portsonly

vcs_clean_all:
@echo "[VCS] Cleanup (entire vcs_work dir)"
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25 changes: 25 additions & 0 deletions verif/sim/cva6.hvp
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@

plan "CVA6 Verification Master Plan";

attribute string Comment = "";

description = "CVA6 Verification Master Plan";
feature "Programmer view level";
Expand All @@ -9,7 +10,10 @@ plan "CVA6 Verification Master Plan";
description = "Instruction Set Architecture\nSpecification: Done, Dvplan: Done, Verification execution: Done";
feature RV32I;
description = "I extension";
Comment = "";
feature ADD;
Comment = "Issue in Spike-dasm decoder
Waiting for ISA_DECODER to be merge on master";
measure Group ADD;
source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_add_cg";
endmeasure
Expand Down Expand Up @@ -65,16 +69,19 @@ plan "CVA6 Verification Master Plan";
endmeasure
endfeature
feature DRET;
Comment = "RVFI limitation issue(#1338)";
measure Group DRET;
source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_dret_cg";
endmeasure
endfeature
feature EBREAK;
Comment = "RVFI limitation issue(#1338)";
measure Group EBREAK;
source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_ebreak_cg";
endmeasure
endfeature
feature ECALL;
Comment = "RVFI limitation issue(#1338)";
measure Group ECALL;
source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32i_ecall_cg";
endmeasure
Expand Down Expand Up @@ -331,6 +338,7 @@ plan "CVA6 Verification Master Plan";
endmeasure
endfeature
feature EBREAK;
Comment = "RVFI limitation issue(#1338)";
measure Group EBREAK;
source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32c_ebreak_cg";
endmeasure
Expand Down Expand Up @@ -461,6 +469,7 @@ plan "CVA6 Verification Master Plan";
endfeature
feature RV32ZIFENCEI;
description = "ZIFENCE.I extension";
Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
measure Group FEINCE_I;
source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32zifencei_fence_i_cg";
endmeasure
Expand All @@ -478,6 +487,7 @@ plan "CVA6 Verification Master Plan";
feature RV32ZCB;
weight = 0;
description = "ZCB extension";
Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
measure Group C_MUL;
endmeasure
measure Group C_ZEXT_B;
Expand All @@ -495,6 +505,7 @@ plan "CVA6 Verification Master Plan";
endfeature
feature RV32ZB;
description = "Bitmanip extension";
Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
feature RV32ZBA;
measure Group SH1ADD;
source = "group instance: uvma_isacov_pkg.uvma_isacov_pkg.rv32zba_sh1add_cg";
Expand Down Expand Up @@ -608,12 +619,14 @@ plan "CVA6 Verification Master Plan";
endfeature
feature "Illegal instructions";
weight = 0;
Comment = "RVFI limitation issue(#1338)";
measure Group illegal_instructions;
endmeasure
endfeature
endfeature
feature "CSR access";
description = "CSR registers access.\nSpecification: Done, Dvplan: Done, Verification execution: Done";
Comment = "Issue in Spike-dasm decoder\nWaiting for ISA_DECODER to be merge on master";
feature "CSR CODE COVERAGE";
measure Line, Cond, Toggle CSR_code_cov;
source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.csr_regfile_i";
Expand Down Expand Up @@ -1272,6 +1285,7 @@ plan "CVA6 Verification Master Plan";
endfeature
feature TRAPs;
description = "Interrupts and Exceptions.\nSpecification: Done, Dvplan: Done, Verification execution: No.";
Comment = "RVFI limitation issue(#1338)";
feature Interrupts;
measure Group Interrupts;
endmeasure
Expand All @@ -1288,6 +1302,7 @@ plan "CVA6 Verification Master Plan";
endfeature
feature PMP;
description = "Physical Memory Protection suppor.t\nSpecification: No, Dvplan: No, Verification execution: No.";
Comment = "Need to separate PMP from MMU";
measure Group PMP;
endmeasure
endfeature
Expand Down Expand Up @@ -1343,6 +1358,11 @@ plan "CVA6 Verification Master Plan";
measure Group Features;
endmeasure
endfeature
feature "Code Coverage";
measure Line, Cond, Toggle, Assert, SnpsAvg AXI;
source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.gen_cache_wt.i_cache_subsystem.i_adapter.i_axi_shim";
endmeasure
endfeature
feature Assertions;
measure Assert axi_protocol_assertion;
source = "property: **.axi_ar_assert.*", "property: **.axi_aw_assert.*", "property: **.axi_b_assert.*", "property: **.axi_r_assert.*", "property: **.axi_w_assert.*";
Expand All @@ -1363,6 +1383,11 @@ plan "CVA6 Verification Master Plan";
source = "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_after_n_cycle", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_kill", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_same_cycle", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_commit_valid_pulse", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_issue_multic", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_issue_resp_null_when_n_accept", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_res_multic", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_res_multic_we", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_result_dualwrite", "property: uvmt_cva6_tb.cva6_dut_wrap.cvxif_assert.c_sync_exc";
endmeasure
endfeature
feature "Code Coverage";
measure Line, Cond, Toggle, Assert, SnpsAvg CVXIF;
source = "tree: uvmt_cva6_tb.cva6_dut_wrap.cva6_tb_wrapper_i.i_cva6.ex_stage_i.gen_cvxif.cvxif_fu_i";
endmeasure
endfeature
feature "Extended instructions";
description = "XIF extended instructions";
feature Instructions;
Expand Down

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