zbkx implementation

10x-Engineers · Dec 17, 2024 · cfbefac · cfbefac
1 parent ed89c71
commit cfbefac
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Showing 7 changed files with 37 additions and 1 deletion.
diff --git a/core/alu.sv b/core/alu.sv
@@ -51,6 +51,9 @@ module alu
   logic lz_tz_empty, lz_tz_wempty;
   logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result;
 
+  logic [CVA6Cfg.XLEN-1:0] xperm8_result;
+  logic [CVA6Cfg.XLEN-1:0] xperm4_result;
+
   // bit reverse operand_a for left shifts and bit counting
   generate
     genvar k;
@@ -263,6 +266,23 @@ module alu
     end
   end
 
+// ZBKX Block
+if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : xperm_gen_block
+  genvar i, m;
+  for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : xperm8_gen
+    assign xperm8_result[i << 3 +: 8] = 
+      (fu_data_i.operand_b[i << 3 +: 8] < (CVA6Cfg.XLEN / 8)) 
+        ? fu_data_i.operand_a[fu_data_i.operand_b[i << 3 +: 8] << 3 +: 8] 
+        : 8'b0;
+  end
+  for (m = 0; m < (CVA6Cfg.XLEN / 4); m++) begin : xperm4_gen
+  assign xperm4_result[m * 4 +: 4] = 
+      (fu_data_i.operand_b[m * 4 +: 4] < (CVA6Cfg.XLEN / 4)) 
+      ? fu_data_i.operand_a[fu_data_i.operand_b[m * 4 +: 4] * 4 +: 4] 
+      : 4'b0;
+end
+end
+
   // -----------
   // Result MUX
   // -----------
@@ -358,5 +378,11 @@ module alu
         default: ;  // default case to suppress unique warning
       endcase
     end
+    if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
+      unique case (fu_data_i.operation)
+        XPERM8: result_o = xperm8_result;
+        XPERM4: result_o = xperm4_result;
+      endcase
+    end
   end
 endmodule
diff --git a/core/decoder.sv b/core/decoder.sv
@@ -776,6 +776,8 @@ module decoder
                 // Bitwise Shifting
                 {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROL;  // rol
                 {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::ROR;  // ror
+                {7'b001_0100, 3'b100} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM8; else illegal_instr_bm = 1'b1; // xperm8
+                {7'b001_0100, 3'b010} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::XPERM4; else illegal_instr_bm = 1'b1; // xperm4
                 // Zero Extend Op RV32 encoding
                 {
                   7'b000_0100, 3'b100

diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv
@@ -489,7 +489,9 @@ package ariane_pkg;
     ACCEL_OP_STORE,
     // Zicond instruction
     CZERO_EQZ,
-    CZERO_NEZ
+    CZERO_NEZ,
+    XPERM8,
+    XPERM4
   } fu_op;
 
   function automatic logic op_is_branch(input fu_op op);

diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv
@@ -65,6 +65,7 @@ package build_config_pkg;
     cfg.XF8 = CVA6Cfg.XF8;
     cfg.RVA = CVA6Cfg.RVA;
     cfg.RVB = CVA6Cfg.RVB;
+    cfg.ZKN = CVA6Cfg.ZKN;
     cfg.RVV = CVA6Cfg.RVV;
     cfg.RVC = CVA6Cfg.RVC;
     cfg.RVH = CVA6Cfg.RVH;

diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv
@@ -54,6 +54,8 @@ package config_pkg;
     bit                          RVA;
     // Bit manipulation RISC-V extension
     bit                          RVB;
+    // Scalar Cryptography RISC-V entension
+    bit                          ZKN;
     // Vector RISC-V extension
     bit                          RVV;
     // Compress RISC-V extension
@@ -240,6 +242,7 @@ package config_pkg;
     bit          XF8;
     bit          RVA;
     bit          RVB;
+    bit          ZKN;
     bit          RVV;
     bit          RVC;
     bit          RVH;

diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -91,6 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),

diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
@@ -91,6 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),