Updating changes after comments

core/cache_subsystem/cva6_icache.sv

@@ -166,7 +166,7 @@ end else begin : gen_piton_offset
 // main control logic
 ///////////////////////////////////////////////////////
   logic addr_ni;
-  assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, {{64-$bits(areq_i.fetch_paddr){1'b0}},areq_i.fetch_paddr});
+  assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, areq_i.fetch_paddr);
   always_comb begin : p_fsm
     // default assignment
     state_d      = state_q;

core/csr_regfile.sv

@@ -153,7 +153,6 @@ module csr_regfile import ariane_pkg::*; #(
     riscv::pmpcfg_t [15:0]    pmpcfg_q,  pmpcfg_d;
     logic [15:0][riscv::PLEN-3:0]        pmpaddr_q,  pmpaddr_d;
     logic [MHPMCounterNum+3-1:0] mcountinhibit_d,mcountinhibit_q;
-    int index;
 
     localparam riscv::xlen_t IsaCode = (riscv::XLEN'(CVA6Cfg.RVA) <<  0)                // A - Atomic Instructions extension
                                      | (riscv::XLEN'(CVA6Cfg.RVC) <<  2)                // C - Compressed extension
@@ -190,7 +189,6 @@ module csr_regfile import ariane_pkg::*; #(
         read_access_exception = 1'b0;
         csr_rdata = '0;
         perf_addr_o = csr_addr.address[11:0];
-        index = '0;
 
         if (csr_read) begin
             unique case (csr_addr.address)
@@ -467,8 +465,7 @@ module csr_regfile import ariane_pkg::*; #(
                 riscv::CSR_PMPADDR14,
                 riscv::CSR_PMPADDR15: begin
                     // index is specified by the last byte in the address
-                    index = {{28{1'b0}},csr_addr.csr_decode.address[3:0]};
-                    // Important: we only support granularity 8 bytes (G=1)
+                    automatic int index = {{28{1'b0}},csr_addr.csr_decode.address[3:0]};                    // Important: we only support granularity 8 bytes (G=1)
                     // -> last bit of pmpaddr must be set 0/1 based on the mode:
                     // NA4, NAPOT: 1
                     // TOR, OFF:   0
@@ -1218,9 +1215,10 @@ module csr_regfile import ariane_pkg::*; #(
     // CSR Exception Control
     // ----------------------
     always_comb begin : exception_ctrl
-        csr_exception_o = {
-           {(2*riscv::XLEN-2){1'b0}}, '0, '0, 1'b0
-        };
+    // Initialize the csr_exception_o object
+        csr_exception_o.cause = 'b0;   // Initialize cause to all zeros
+        csr_exception_o.tval = 'b0;    // Initialize tval to all zeros
+        csr_exception_o.valid = 1'b0; // Initialize valid to logic zero
         // ----------------------------------
         // Illegal Access (decode exception)
         // ----------------------------------
@@ -1305,7 +1303,7 @@ module csr_regfile import ariane_pkg::*; #(
             // in supervisor mode we also need to check whether we delegated this bit
             riscv::CSR_SIP: begin
                 csr_rdata_o = csr_rdata
-                            | (({{riscv::XLEN-1{1'b0}},irq_i[1]} & {{riscv::XLEN-1{1'b0}},mideleg_q[riscv::IRQ_S_EXT]}) << riscv::IRQ_S_EXT);
+                            | ({{riscv::XLEN-1{1'b0}}, (irq_i[1] & mideleg_q[riscv::IRQ_S_EXT])} << riscv::IRQ_S_EXT);
             end
             default:;
         endcase
@@ -1386,7 +1384,7 @@ module csr_regfile import ariane_pkg::*; #(
             stval_q                <= {riscv::XLEN{1'b0}};
             satp_q                 <= {riscv::XLEN{1'b0}};
             // timer and counters
-            cycle_q                <= {{64-riscv::XLEN{1'b0}},{riscv::XLEN{1'b0}}};
+            cycle_q                <= 64'b0;
             instret_q              <= {{64-riscv::XLEN{1'b0}},{riscv::XLEN{1'b0}}};
             // aux registers
             en_ld_st_translation_q <= 1'b0;

core/include/ariane_pkg.sv

@@ -87,13 +87,13 @@ package ariane_pkg;
       // pragma translate_on
     endfunction
 
-    function automatic logic range_check(logic[63:0] base, logic[63:0] len, logic[63:0] address);
+    function automatic logic range_check(logic [riscv::XLEN-1:0] base, logic [riscv::XLEN-1:0] len, logic [riscv::XLEN-1:0] address);
       // if len is a power of two, and base is properly aligned, this check could be simplified
       // Extend base by one bit to prevent an overflow.
-      return (address >= base) && (({1'b0, address}) < (65'(base)+len));
+      return (address >= base) && (({1'b0, address}) < ((riscv::XLEN+1)'(base)+len));
     endfunction : range_check
 
-    function automatic logic is_inside_nonidempotent_regions (ariane_cfg_t Cfg, logic[63:0] address);
+    function automatic logic is_inside_nonidempotent_regions (ariane_cfg_t Cfg, logic [riscv::XLEN-1:0] address);
       logic[NrMaxRules-1:0] pass;
       pass = '0;
       for (int unsigned k = 0; k < Cfg.NrNonIdempotentRules; k++) begin

core/load_unit.sv

@@ -176,7 +176,7 @@ module load_unit import ariane_pkg::*; #(
     logic not_commit_time;
     logic inflight_stores;
     logic stall_ni;
-    assign paddr_ni = is_inside_nonidempotent_regions(ArianeCfg, {{52-$bits(dtlb_ppn_i){1'b0}},{dtlb_ppn_i,12'd0}});
+    assign paddr_ni = is_inside_nonidempotent_regions(ArianeCfg, {dtlb_ppn_i,12'd0});
     assign not_commit_time = commit_tran_id_i != lsu_ctrl_i.trans_id;
     assign inflight_stores = (!dcache_wbuffer_not_ni_i || !store_buffer_empty_i);
     assign stall_ni = (inflight_stores || not_commit_time) && paddr_ni;

core/mmu_sv32/cva6_mmu_sv32.sv

@@ -390,7 +390,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #(
             lsu_dtlb_ppn_o        = {{riscv::PLEN-riscv::VLEN{1'b0}},lsu_vaddr_n[riscv::VLEN-1:12]};
         end else begin
             lsu_paddr_o           = lsu_vaddr_q[riscv::PLEN-1:0];
-            lsu_dtlb_ppn_o        = {{$bits(lsu_dtlb_ppn_o)-$bits(lsu_vaddr_n[riscv::VLEN-1:12]){1'b0}},lsu_vaddr_n[riscv::VLEN-1:12]};
+            lsu_dtlb_ppn_o        = {{riscv::PLEN-riscv::VLEN{1'b0}},lsu_vaddr_n[riscv::VLEN-1:12]};
         end
         lsu_valid_o           = lsu_req_q;
         lsu_exception_o       = misaligned_ex_q;

core/scoreboard.sv

@@ -176,7 +176,7 @@ module scoreboard #(
         // save the target address of a branch (needed for debug in commit stage)
         mem_n[trans_id_i[i]].sbe.bp.predict_address = resolved_branch_i.target_address;
         if (mem_n[trans_id_i[i]].sbe.fu == ariane_pkg::CVXIF && ~x_we_i) begin
-          mem_n[trans_id_i[i]].sbe.rd = 6'b0;
+          mem_n[trans_id_i[i]].sbe.rd = '0;
         end
         // write the exception back if it is valid
         if (ex_i[i].valid)
@@ -215,7 +215,7 @@ module scoreboard #(
   // FIFO counter updates
   assign num_commit = (CVA6Cfg.NrCommitPorts == 2) ? commit_ack_i[1] + commit_ack_i[0] : commit_ack_i[0];
 
-  assign issue_cnt_n         = (flush_i) ? '0 : issue_cnt_q - {{3-$bits(num_commit){1'b0}},num_commit} + {{3-$bits(issue_en){1'b0}},issue_en};
+  assign issue_cnt_n = (flush_i) ? '0 : issue_cnt_q - {{3{1'b0}}, (num_commit + issue_en)};
   assign commit_pointer_n[0] = (flush_i) ? '0 : commit_pointer_q[0] + num_commit;
   assign issue_pointer_n     = (flush_i) ? '0 : issue_pointer_q     + issue_en;
 

core/serdiv.sv

@@ -107,8 +107,8 @@ module serdiv import ariane_pkg::*; #(
     .empty_o ( lzc_b_no_one )
   );
 
-  assign shift_a      = (lzc_a_no_one) ? WIDTH : {{$bits(shift_a)-$bits(lzc_a_result){1'b0}},lzc_a_result};
-  assign div_shift    = {{$bits(div_shift)-$bits(lzc_b_result){1'b0}},lzc_b_result} - shift_a;
+  assign shift_a      = (lzc_a_no_one) ? WIDTH : {1'b0,lzc_a_result};
+  assign div_shift    = {1'b0,lzc_b_result} - shift_a;
 
   assign op_b         = op_b_i <<< $unsigned(div_shift);
 

core/store_buffer.sv

@@ -78,7 +78,7 @@ module store_buffer import ariane_pkg::*; #(
         speculative_status_cnt = speculative_status_cnt_q;
 
         // we are ready if the speculative and the commit queue have a space left
-        ready_o = ({{$bits(DEPTH_SPEC)-$bits(speculative_status_cnt_q){1'b0}},speculative_status_cnt_q} < (DEPTH_SPEC - 1)) || commit_i;
+        ready_o = ({{29{1'b0}},speculative_status_cnt_q} < (DEPTH_SPEC - 1)) || commit_i;
         // default assignments
         speculative_status_cnt_n    = speculative_status_cnt_q;
         speculative_read_pointer_n  = speculative_read_pointer_q;
@@ -149,7 +149,7 @@ module store_buffer import ariane_pkg::*; #(
         automatic logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt;
         commit_status_cnt = commit_status_cnt_q;
 
-        commit_ready_o = ({{$bits(DEPTH_COMMIT)-$bits(commit_status_cnt_q){1'b0}},commit_status_cnt_q} < DEPTH_COMMIT);
+        commit_ready_o = ({{29{1'b0}},commit_status_cnt_q}  < DEPTH_COMMIT);
         // no store is pending if we don't have any element in the commit queue e.g.: it is empty
         no_st_pending_o         = (commit_status_cnt_q == 0);
         // default assignments
@@ -268,15 +268,15 @@ module store_buffer import ariane_pkg::*; #(
         else $error ("[Commit Queue] You are trying to commit and flush in the same cycle");
 
     speculative_buffer_overflow: assert property (
-        @(posedge clk_i) rst_ni && ({{32-$bits(speculative_status_cnt_q){1'b0}},speculative_status_cnt_q} == DEPTH_SPEC) |-> !valid_i)
+        @(posedge clk_i) rst_ni && ({{29{1'b0}},speculative_status_cnt_q} == DEPTH_SPEC) |-> !valid_i)
         else $error ("[Speculative Queue] You are trying to push new data although the buffer is not ready");
 
     speculative_buffer_underflow: assert property (
         @(posedge clk_i) rst_ni && (speculative_status_cnt_q == 0) |-> !commit_i)
         else $error ("[Speculative Queue] You are committing although there are no stores to commit");
 
     commit_buffer_overflow: assert property (
-        @(posedge clk_i) rst_ni && ({{$bits(DEPTH_COMMIT)-$bits(commit_status_cnt_q){1'b0}},commit_status_cnt_q} == DEPTH_COMMIT) |-> !commit_i)
+        @(posedge clk_i) rst_ni && ({{29{1'b0}},commit_status_cnt_q} == DEPTH_COMMIT) |-> !commit_i)
         else $error("[Commit Queue] You are trying to commit a store although the buffer is full");
     //pragma translate_on
 endmodule

core/store_unit.sv

@@ -185,7 +185,7 @@ module store_unit import ariane_pkg::*; #(
         st_be_n   = lsu_ctrl_i.be;
         // don't shift the data if we are going to perform an AMO as we still need to operate on this data
         st_data_n = instr_is_amo ? lsu_ctrl_i.data[riscv::XLEN-1:0]
-                                 : data_align(lsu_ctrl_i.vaddr[2:0], {{64-$bits(lsu_ctrl_i.data){1'b0}},lsu_ctrl_i.data});
+                                 : data_align(lsu_ctrl_i.vaddr[2:0], {{64-riscv::XLEN{1'b0}},lsu_ctrl_i.data});
         st_data_size_n = extract_transfer_size(lsu_ctrl_i.operation);
         // save AMO op for next cycle
         case (lsu_ctrl_i.operation)