mazhar changes for lint fixes

10x-Engineers · Sep 8, 2023 · 90a612c · fatimasaleem · Sep 9, 2023 · fatimasaleem
1 parent 983d6cb
commit 90a612c
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Showing 6 changed files with 36 additions and 16 deletions.
diff --git a/core/alu.sv b/core/alu.sv
@@ -284,7 +284,7 @@ module alu import ariane_pkg::*; #(
                 CLZW, CTZW:  result_o = (lz_tz_wempty) ? 32 : {{riscv::XLEN-5{1'b0}}, lz_tz_wcount};
 
                 // Count population
-                CPOP, CPOPW: result_o = {{(riscv::XLEN-($clog2(riscv::XLEN))){1'b0}}, cpop};
+                CPOP, CPOPW: result_o = {{(riscv::XLEN-(($clog2(riscv::XLEN) +1))){1'b0}}, cpop};
 
                 // Sign and Zero Extend
                 SEXTB: result_o = {{riscv::XLEN-8{fu_data_i.operand_a[7]}}, fu_data_i.operand_a[7:0]};

diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv
@@ -118,15 +118,15 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
   assign cl_tag_d  = (areq_i.fetch_valid) ? areq_i.fetch_paddr[ICACHE_TAG_WIDTH+ICACHE_INDEX_WIDTH-1:ICACHE_INDEX_WIDTH] : cl_tag_q;
 
   // noncacheable if request goes to I/O space, or if cache is disabled
-  assign paddr_is_nc = (~cache_en_q) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{{64-riscv::PLEN}{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));
+  assign paddr_is_nc = (~cache_en_q) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{64-riscv::PLEN{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));
 
   // pass exception through
   assign dreq_o.ex = areq_i.fetch_exception;
 
   // latch this in case we have to stall later on
   // make sure this is 32bit aligned
   assign vaddr_d = (dreq_o.ready & dreq_i.req) ? dreq_i.vaddr : vaddr_q;
-  assign areq_o.fetch_vaddr = {vaddr_q>>2, 2'b0};
+  assign areq_o.fetch_vaddr = {vaddr_q[riscv::VLEN-1:2], 2'b0};
 
   // split virtual address into index and offset to address cache arrays
   assign cl_index    = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH];

diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv
@@ -191,15 +191,35 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
                                           toSize32(bdirty[dirty_ptr]);
 
   // replicate transfers shorter than a dword
+    /*
+  always_comb begin
+    if (riscv::IS_XLEN64)
+        miss_wdata_o = repData64(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]);
+    else 
+        miss_wdata_o = repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]);
+  end*/                           
   assign miss_wdata_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]):
-                                           repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]);
+                                           repData32(wbuffer_dirty_mux.data, bdirty_off, miss_size_o[1:0]); 
+
   if (ariane_pkg::DATA_USER_EN) begin
+    /*
+    if (riscv::IS_XLEN64)
+      assign  miss_wuser_o = repData64(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);
+    else 
+      assign  miss_wuser_o = repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);
+    */
     assign miss_wuser_o = riscv::IS_XLEN64 ? repData64(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]):
-                                             repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);
+                                             repData32(wbuffer_dirty_mux.user, bdirty_off, miss_size_o[1:0]);                                      
   end else begin
     assign miss_wuser_o = '0;
   end
 
+  /*
+  if (riscv::IS_XLEN64)
+      assign  tx_be = to_byte_enable8(bdirty_off, miss_size_o[1:0]);
+  else 
+      assign  tx_be = to_byte_enable4(bdirty_off, miss_size_o[1:0]);
+  */
   assign tx_be        = riscv::IS_XLEN64 ? to_byte_enable8(bdirty_off, miss_size_o[1:0]):
                                            to_byte_enable4(bdirty_off, miss_size_o[1:0]);
 

diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv
@@ -279,8 +279,8 @@ module instr_queue import ariane_pkg::*; #(
           end
           fetch_entry_o.instruction = instr_data_out[i].instr;
           fetch_entry_o.ex.valid = instr_data_out[i].ex != ariane_pkg::FE_NONE;
-          fetch_entry_o.ex.tval  = {{64-riscv::VLEN{1'b0}}, instr_data_out[i].ex_vaddr};
-          fetch_entry_o.branch_predict.cf = instr_data_out[i].cf;
+          fetch_entry_o.ex.tval  = {/*{64-riscv::VLEN{1'b0}},*/ instr_data_out[i].ex_vaddr};
+            fetch_entry_o.branch_predict.cf = instr_data_out[i].cf;
           pop_instr[i] = fetch_entry_valid_o & fetch_entry_ready_i;
         end
       end

diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv
@@ -83,8 +83,8 @@ module issue_read_operands import ariane_pkg::*; #(
 );
     logic stall;
     logic fu_busy; // functional unit is busy
-    riscv::xlen_t    operand_a_regfile, operand_b_regfile;  // operands coming from regfile
-    rs3_len_t operand_c_regfile; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3
+    riscv::xlen_t    operand_a_regfile, operand_b_regfile, operand_c_regfile;  // operands coming from regfile
+    //rs3_len_t operand_c_regfile; // third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3
     // output flipflop (ID <-> EX)
     riscv::xlen_t operand_a_n, operand_a_q,
                  operand_b_n, operand_b_q,
@@ -222,7 +222,7 @@ module issue_read_operands import ariane_pkg::*; #(
             imm_n  = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} :
                                                     issue_instr_i.op == OFFLOAD ? operand_c_regfile : issue_instr_i.result;
         end else begin
-            imm_n  = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, operand_c_regfile} : issue_instr_i.result;
+            imm_n  = is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {/*{riscv::XLEN-CVA6Cfg.FLen{1'b0}},*/ operand_c_regfile} : issue_instr_i.result;
         end
         trans_id_n = issue_instr_i.trans_id;
         fu_n       = issue_instr_i.fu;
@@ -499,7 +499,7 @@ module issue_read_operands import ariane_pkg::*; #(
     assign operand_a_regfile = is_rs1_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[0]} : rdata[0];
     assign operand_b_regfile = is_rs2_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[1]} : rdata[1];
     assign operand_c_regfile = CVA6Cfg.NrRgprPorts == 3 ? (is_imm_fpr_cfg(issue_instr_i.op, CVA6Cfg.FpPresent) ? {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[2]} : rdata[2])
-                                                  : fprdata[2];
+                                                    : {{riscv::XLEN-CVA6Cfg.FLen{1'b0}}, fprdata[2]} ;
 
     // ----------------------
     // Registers (ID <-> EX)

diff --git a/corev_apu/tb/common/mock_uart.sv b/corev_apu/tb/common/mock_uart.sv
@@ -62,11 +62,11 @@ module mock_uart (
             if (psel_i & penable_i & pwrite_i) begin
                 case ((paddr_i >> 'h2) & 'h7)
                     THR: begin
-                        if (lcr & 'h80) dll <= byte'(pwdata_i[7:0]);
+                        if (&(lcr & 'h80)) dll <= byte'(pwdata_i[7:0]);
                         else uart_tx(byte'(pwdata_i[7:0]));
                     end
                     IER: begin
-                        if (lcr & 'h80) dlm <= byte'(pwdata_i[7:0]);
+                        if (&(lcr & 'h80)) dlm <= byte'(pwdata_i[7:0]);
                         else ier <= byte'(pwdata_i[7:0] & 'hF);
                     end
                     FCR: begin
@@ -89,10 +89,10 @@ module mock_uart (
         if (psel_i & penable_i & ~pwrite_i) begin
             case ((paddr_i >> 'h2) & 'h7)
                 THR: begin
-                    if (lcr & 'h80) prdata_o = {24'b0, dll};
+                    if (&(lcr & 'h80)) prdata_o = {24'b0, dll};
                 end
                 IER: begin
-                    if (lcr & 'h80) prdata_o = {24'b0, dlm};
+                    if (&(lcr & 'h80)) prdata_o = {24'b0, dlm};
                     else prdata_o = {24'b0, ier};
                 end
                 IIR: begin
@@ -101,7 +101,7 @@ module mock_uart (
                 end
                 LCR: prdata_o = {24'b0, lcr};
                 MCR: prdata_o = {24'b0, mcr};
-                LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))};
+                LSR: prdata_o = {24'b0, (lsr | (8'b00000001 << THRE) | (8'b00000001 << TEMT))};
                 MSR: prdata_o = {24'b0, msr};
                 SCR: prdata_o = {24'b0, scr};
                 default:;