Skip to content

Commit

Permalink
Added Zcmp Extension Support (Design and test files)
Browse files Browse the repository at this point in the history
  • Loading branch information
@rohan-10xe
rohan-10xe committed Jan 23, 2024
1 parent c430c6c commit 15fd386
Show file tree
Hide file tree
Showing 21 changed files with 1,972 additions and 25 deletions.
1 change: 1 addition & 0 deletions core/Flist.cva6
View file
Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,7 @@ ${CVA6_REPO_DIR}/core/alu.sv
${CVA6_REPO_DIR}/core/fpu_wrap.sv
${CVA6_REPO_DIR}/core/branch_unit.sv
${CVA6_REPO_DIR}/core/compressed_decoder.sv
${CVA6_REPO_DIR}/core/zcmp_decoder.sv
${CVA6_REPO_DIR}/core/controller.sv
${CVA6_REPO_DIR}/core/csr_buffer.sv
${CVA6_REPO_DIR}/core/csr_regfile.sv
Expand Down
42 changes: 26 additions & 16 deletions core/compressed_decoder.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ module compressed_decoder #(
) (
input logic [31:0] instr_i,
output logic [31:0] instr_o,
output logic is_zcmp_instr_o,
output logic illegal_instr_o,
output logic is_compressed_o
);
Expand All @@ -32,10 +33,11 @@ module compressed_decoder #(
// Compressed Decoder
// -------------------
always_comb begin
illegal_instr_o = 1'b0;
instr_o = '0;
is_compressed_o = 1'b1;
instr_o = instr_i;
illegal_instr_o = 1'b0;
instr_o = '0;
is_compressed_o = 1'b1;
instr_o = instr_i;
is_zcmp_instr_o = 0;

// I: | imm[11:0] | rs1 | funct3 | rd | opcode |
// S: | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode |
Expand Down Expand Up @@ -849,18 +851,25 @@ module compressed_decoder #(

riscv::OpcodeC2Fsdsp: begin
if (CVA6Cfg.FpPresent) begin
// c.fsdsp -> fsd rs2, imm(x2)
instr_o = {
3'b0,
instr_i[9:7],
instr_i[12],
instr_i[6:2],
5'h02,
3'b011,
instr_i[11:10],
3'b000,
riscv::OpcodeStoreFp
};
// c.fsdsp -> fsd rs2, imm(x2)
instr_o = {
3'b0,
instr_i[9:7],
instr_i[12],
instr_i[6:2],
5'h02,
3'b011,
instr_i[11:10],
3'b000,
riscv::OpcodeStoreFp
};
end else if (CVA6Cfg.RVZCMP) begin
if (instr_i[12:10] == 3'b110 || instr_i[12:10] == 3'b111 || instr_i[12:10] == 3'b011) begin //is a push/pop instruction
is_zcmp_instr_o = 1;
instr_o = instr_i;
end else begin
illegal_instr_o = 1'b1;
end
end else begin
illegal_instr_o = 1'b1;
end
Expand Down Expand Up @@ -933,3 +942,4 @@ module compressed_decoder #(
end
end
endmodule

1 change: 1 addition & 0 deletions core/cva6.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -180,6 +180,7 @@ module cva6
CVA6Cfg.RVV,
CVA6Cfg.RVC,
CVA6Cfg.RVZCB,
CVA6Cfg.RVZCMP,
CVA6Cfg.XFVec,
CVA6Cfg.CvxifEn,
CVA6Cfg.ZiCondExtEn,
Expand Down
51 changes: 42 additions & 9 deletions core/id_stage.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,8 +54,13 @@ module id_stage #(
ariane_pkg::scoreboard_entry_t decoded_instruction;

logic is_illegal;
logic is_illegal_cmp;
logic [31:0] instruction;
logic [31:0] compressed_instr;
logic is_compressed;
logic is_compressed_cmp;
logic is_zcmp_instr_i;
logic stall_instr_fetch;

if (CVA6Cfg.RVC) begin
// ---------------------------------------------------------
Expand All @@ -64,15 +69,38 @@ module id_stage #(
compressed_decoder #(
.CVA6Cfg(CVA6Cfg)
) compressed_decoder_i (
.instr_i (fetch_entry_i.instruction),
.instr_o (instruction),
.illegal_instr_o(is_illegal),
.is_compressed_o(is_compressed)
.instr_i (fetch_entry_i.instruction),
.instr_o (compressed_instr),
.illegal_instr_o (is_illegal),
.is_compressed_o (is_compressed),
.is_zcmp_instr_o (is_zcmp_instr_i)
);
if (CVA6Cfg.RVZCMP) begin
//sequencial decoder
zcmp_decoder #(
.CVA6Cfg(CVA6Cfg)
) zcmp_decoder_i (
.instr_i (compressed_instr),
.is_zcmp_instr_i (is_zcmp_instr_i),
.clk_i (clk_i),
.rst_ni (rst_ni),
.instr_o (instruction),
.illegal_instr_i (is_illegal),
.is_compressed_i (is_compressed),
.issue_ack_i (issue_instr_ack_i),
.illegal_instr_o (is_illegal_cmp),
.is_compressed_o (is_compressed_cmp),
.fetch_stall_o (stall_instr_fetch)
);
end else begin
assign instruction = compressed_instr;
assign is_illegal_cmp = is_illegal;
assign is_compressed_cmp = is_compressed;
end
end else begin
assign instruction = fetch_entry_i.instruction;
assign is_illegal = '0;
assign is_compressed = '0;
assign is_illegal_cmp = '0;
assign is_compressed_cmp = '0;
end
// ---------------------------------------------------------
// 2. Decode and emit instruction to issue stage
Expand All @@ -84,8 +112,8 @@ module id_stage #(
.irq_ctrl_i,
.irq_i,
.pc_i (fetch_entry_i.address),
.is_compressed_i (is_compressed),
.is_illegal_i (is_illegal),
.is_compressed_i (is_compressed_cmp),
.is_illegal_i (is_illegal_cmp),
.instruction_i (instruction),
.compressed_instr_i (fetch_entry_i.instruction[15:0]),
.branch_predict_i (fetch_entry_i.branch_predict),
Expand Down Expand Up @@ -120,7 +148,11 @@ module id_stage #(
// or the issue stage is currently acknowledging an instruction, which means that we will have space
// for a new instruction
if ((!issue_q.valid || issue_instr_ack_i) && fetch_entry_valid_i) begin
fetch_entry_ready_o = 1'b1;
if (stall_instr_fetch) begin
fetch_entry_ready_o = 1'b0;
end else begin
fetch_entry_ready_o = 1'b1;
end
issue_n = '{1'b1, decoded_instruction, is_control_flow_instr};
end

Expand All @@ -138,3 +170,4 @@ module id_stage #(
end
end
endmodule

1 change: 1 addition & 0 deletions core/include/config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,7 @@ package config_pkg;
bit RVV;
bit RVC;
bit RVZCB;
bit RVZCMP;
bit XFVec;
bit CvxifEn;
bit ZiCondExtEn;
Expand Down
2 changes: 2 additions & 0 deletions core/include/cv32a60x_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ package cva6_config_pkg;
localparam CVA6ConfigCvxifEn = 1;
localparam CVA6ConfigCExtEn = 1;
localparam CVA6ConfigZcbExtEn = 1;
localparam CVA6ConfigZcmpExtEn = 1;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
Expand Down Expand Up @@ -87,6 +88,7 @@ package cva6_config_pkg;
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVZCB: bit'(CVA6ConfigZcbExtEn),
RVZCMP: bit'(CVA6ConfigZcmpExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn),
Expand Down
2 changes: 2 additions & 0 deletions core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ package cva6_config_pkg;
localparam CVA6ConfigCvxifEn = 1;
localparam CVA6ConfigCExtEn = 1;
localparam CVA6ConfigZcbExtEn = 1;
localparam CVA6ConfigZcmpExtEn = 0;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
Expand Down Expand Up @@ -87,6 +88,7 @@ package cva6_config_pkg;
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVZCB: bit'(CVA6ConfigZcbExtEn),
RVZCMP: bit'(CVA6ConfigZcmpExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn),
Expand Down
2 changes: 2 additions & 0 deletions core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ package cva6_config_pkg;
localparam CVA6ConfigCvxifEn = 1;
localparam CVA6ConfigCExtEn = 1;
localparam CVA6ConfigZcbExtEn = 1;
localparam CVA6ConfigZcmpExtEn = 0;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
Expand Down Expand Up @@ -94,6 +95,7 @@ package cva6_config_pkg;
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVZCB: bit'(CVA6ConfigZcbExtEn),
RVZCMP: bit'(CVA6ConfigZcmpExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn),
Expand Down
2 changes: 2 additions & 0 deletions core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ package cva6_config_pkg;
localparam CVA6ConfigCvxifEn = 1;
localparam CVA6ConfigCExtEn = 1;
localparam CVA6ConfigZcbExtEn = 1;
localparam CVA6ConfigZcmpExtEn = 0;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 1;
localparam CVA6ConfigVExtEn = 0;
Expand Down Expand Up @@ -87,6 +88,7 @@ package cva6_config_pkg;
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVZCB: bit'(CVA6ConfigZcbExtEn),
RVZCMP: bit'(CVA6ConfigZcmpExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn),
Expand Down
2 changes: 2 additions & 0 deletions core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ package cva6_config_pkg;
localparam CVA6ConfigCvxifEn = 0;
localparam CVA6ConfigCExtEn = 1;
localparam CVA6ConfigZcbExtEn = 0;
localparam CVA6ConfigZcmpExtEn = 0;
localparam CVA6ConfigAExtEn = 1;
localparam CVA6ConfigBExtEn = 0;
localparam CVA6ConfigVExtEn = 1;
Expand Down Expand Up @@ -86,6 +87,7 @@ package cva6_config_pkg;
RVV: bit'(CVA6ConfigVExtEn),
RVC: bit'(CVA6ConfigCExtEn),
RVZCB: bit'(CVA6ConfigZcbExtEn),
RVZCMP: bit'(CVA6ConfigZcmpExtEn),
XFVec: bit'(CVA6ConfigFVecEn),
CvxifEn: bit'(CVA6ConfigCvxifEn),
ZiCondExtEn: bit'(0),
Expand Down
Loading

0 comments on commit 15fd386

Please sign in to comment.