From f5719db7c479fb500ed761237ff491657b2788cf Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Fri, 27 Sep 2024 13:47:28 +0200 Subject: [PATCH 1/8] boards: amd: kv260_r5: move unmodified sram0 from SoC to board DT Move the unmodified sram0 memory area declaration to this board's device tree due to its removal from the SoC device tree. Signed-off-by: Immo Birnbaum --- boards/amd/kv260_r5/kv260_r5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/boards/amd/kv260_r5/kv260_r5.dts b/boards/amd/kv260_r5/kv260_r5.dts index 85fb1c26891798..4aef0ae2f26616 100644 --- a/boards/amd/kv260_r5/kv260_r5.dts +++ b/boards/amd/kv260_r5/kv260_r5.dts @@ -12,6 +12,11 @@ model = "KV260 Cortex-R5"; compatible = "xlnx,zynqmp-r5"; + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 DT_SIZE_M(64)>; + }; + chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; From 7931fc1b0cc07b36bb81ea86b5941e9965d97786 Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Fri, 27 Sep 2024 13:49:50 +0200 Subject: [PATCH 2/8] boards: enclustra: mercury_xu: move unmodified sram0 from SoC to board DT Move the unmodified sram0 memory area declaration to this board's device tree due to its removal from the SoC device tree. Signed-off-by: Immo Birnbaum --- boards/enclustra/mercury_xu/mercury_xu.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/boards/enclustra/mercury_xu/mercury_xu.dts b/boards/enclustra/mercury_xu/mercury_xu.dts index df51ab470c579e..d602eb5e2d2974 100644 --- a/boards/enclustra/mercury_xu/mercury_xu.dts +++ b/boards/enclustra/mercury_xu/mercury_xu.dts @@ -12,6 +12,11 @@ model = "Mercury XU"; compatible = "xlnx,zynqmp"; + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 DT_SIZE_M(64)>; + }; + chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; From 0e5673ee3316d1b2b5fad37f8cd0b59b627af0d1 Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Fri, 27 Sep 2024 13:51:13 +0200 Subject: [PATCH 3/8] boards: qemu: cortex_r5: expand usable RAM area below 4G boundary Expand the RAM area beginning behind the BTCM to allow the use of a 64MB SRAM area starting at 0x4000000, which is the lowest possible 64MB area with a non-zero start address that doesn't overlap with the ATCM and BTCM memory areas. Signed-off-by: Immo Birnbaum --- .../cortex_r5/fdt-single_arch-zcu102-arm.dtb | Bin 66838 -> 66838 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb b/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb index c5dd6ea59f480bc37b52d37856595320a3817aed..abec19a51d95b9ef180fd8ba5766a000b33dcccd 100644 GIT binary patch delta 20 bcmbQ%#WJmnWdjcrBYQJ1({^4aMowk`J%t2x delta 20 bcmbQ%#WJmnWdjcrBXct^({^4aMowk`JzWHF From 4f3f0cdf66b7f75dbef7b32347978d9ea4210d62 Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Fri, 27 Sep 2024 13:55:25 +0200 Subject: [PATCH 4/8] boards: qemu: cortex_r5: declare 64MB sram0 area at board level Declare the sram0 area for this board to start at 0x4000000 and to be 64MB in size. The base address is the lowest possible multiple of 64MB which doesn't have its base address at 0, therefore preventing the mixed use of regular RAM and the ATCM/BTCM and the possible issues of having a 'black hole' between the ATCM and BTCM areas or the BTCM being completely disabled. Signed-off-by: Immo Birnbaum --- boards/qemu/cortex_r5/qemu_cortex_r5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/boards/qemu/cortex_r5/qemu_cortex_r5.dts b/boards/qemu/cortex_r5/qemu_cortex_r5.dts index b23e9534ed498e..a071506d9ef6b7 100644 --- a/boards/qemu/cortex_r5/qemu_cortex_r5.dts +++ b/boards/qemu/cortex_r5/qemu_cortex_r5.dts @@ -12,6 +12,11 @@ model = "QEMU Cortex-R5"; compatible = "xlnx,zynqmp-qemu"; + sram0: memory@4000000 { + compatible = "mmio-sram"; + reg = <0x4000000 DT_SIZE_M(64)>; + }; + chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; From e15ff78f7068ac30ad04241ef1cb32d42634d6e0 Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Fri, 27 Sep 2024 14:00:47 +0200 Subject: [PATCH 5/8] dts: arm: xilinx: zynqmp: remove sram0 declaration at SoC level Remove the universal, unconditional declaration of the RAM area at the SoC level, due to: - the hardcoded base address 0 overlapping the exception vectors, the ATCM and the BTCM areas. - the availability of the BTCM not being guaranteed unconditionally (config pin dependant) - the possibility of having a 'black hole' between the ATCM and the BTCM depending on the operating mode of the R-cores cluster, which leads to a part of the text section being unavailable - qemu not properly implementing the configuration-dependant behaviour of the ATCM and BTCM areas. Signed-off-by: Immo Birnbaum --- dts/arm/xilinx/zynqmp.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi index 65abc450543576..f5adec548a56da 100644 --- a/dts/arm/xilinx/zynqmp.dtsi +++ b/dts/arm/xilinx/zynqmp.dtsi @@ -19,12 +19,6 @@ compatible = "soc-nv-flash"; reg = <0xc0000000 DT_SIZE_M(32)>; }; - - sram0: memory@0 { - compatible = "mmio-sram"; - reg = <0 DT_SIZE_M(64)>; - }; - ocm: memory@fffc0000 { compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; reg = <0xfffc0000 DT_SIZE_K(256)>; From 5d2527b612473b7f97be7a6cb89514a73ea2f5bb Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Mon, 30 Sep 2024 18:31:12 +0200 Subject: [PATCH 6/8] arch: arm: cortex_a_r: update ROM region size calculation update the directive that calculates the ROM region size bit mask for the MPU setup. Signed-off-by: Immo Birnbaum --- include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld index 239ab62129371a..ae922c075aff47 100644 --- a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld +++ b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld @@ -250,7 +250,7 @@ SECTIONS __rodata_region_end = .; __rom_region_end = .; MPU_ALIGN(__rodata_region_end - __rom_region_start); - _image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1; + __rom_region_mpu_size_bits = (LOG2CEIL(__rodata_region_end - __rom_region_start) - 1) << 1; GROUP_END(ROMABLE_REGION) From ee208d20323aa374a0096f7a5f7c325690f121cf Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Mon, 30 Sep 2024 18:48:10 +0200 Subject: [PATCH 7/8] soc: xlnx: zynqmp: overhaul MPU regions Overhaul the MPU region definitions that are being configured when the MPU is set up: - drop local attribute definitions in favor of those already provided in arm_mpu_v7m.h - actually tie the RAM region to the device tree - set up a (potentially overlapping) R/O region for .text and .rodata, which hasn't existed so far - Consider XIP - Consider OCM only when not running a testsuite (comp. #79627) Signed-off-by: Immo Birnbaum --- soc/xlnx/zynqmp/arm_mpu_regions.c | 114 +++++++++++++++++------------- 1 file changed, 64 insertions(+), 50 deletions(-) diff --git a/soc/xlnx/zynqmp/arm_mpu_regions.c b/soc/xlnx/zynqmp/arm_mpu_regions.c index a4f36402d2cc72..f371c1173c15a6 100644 --- a/soc/xlnx/zynqmp/arm_mpu_regions.c +++ b/soc/xlnx/zynqmp/arm_mpu_regions.c @@ -1,62 +1,76 @@ /* SPDX-License-Identifier: Apache-2.0 * * Copyright (c) 2021 Lexmark International, Inc. + * Copyright (c) 2024 Immo Birnbaum */ #include -#include +#include -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +extern const uint32_t __rom_region_start; +extern const uint32_t __rom_region_mpu_size_bits; -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } - -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } - -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } - -extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), - - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), - - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), - - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + /* + * The address of the vectors is determined by arch/arm/core/cortex_a_r/prep_c.c + * -> for v7-R, there's no other option than 0x0, HIVECS always gets cleared + */ + MPU_REGION_ENTRY( + "vectors", + 0x00000000, + REGION_64B, + {.rasr = P_RO_U_NA_Msk | + NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + /* Basic SRAM mapping is all data, R/W + XN */ + MPU_REGION_ENTRY( + "sram", + CONFIG_SRAM_BASE_ADDRESS, + REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), +#if defined(CONFIG_XIP) + /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), + /* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ + /* .text and .rodata are in RAM, flash is data only -> RO + XN */ + MPU_REGION_ENTRY( + "flash", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | + NOT_EXEC}), + /* add rom_region mapping for SRAM which is RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), +#endif /* CONFIG_XIP */ + MPU_REGION_ENTRY( + "peripherals", + 0xf8000000, + REGION_128M, + {.rasr = P_RW_U_NA_Msk | + DEVICE_SHAREABLE | + NOT_EXEC}), +#if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)) && !defined(CONFIG_TEST) + MPU_REGION_ENTRY( + "ocm", + DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)), + REGION_256K, + {.rasr = FULL_ACCESS_Msk | + STRONGLY_ORDERED_SHAREABLE | + NOT_EXEC}), +#endif }; const struct arm_mpu_config mpu_config = { From d752614b6e25736bf0379dd9d92e668d14eb497a Mon Sep 17 00:00:00 2001 From: Immo Birnbaum Date: Wed, 9 Oct 2024 21:29:55 +0200 Subject: [PATCH 8/8] soc: renode: cortex_r8_virtual: overhaul MPU regions Apply the same modifications made to the ZynqMP's memory regions to the cortex_r8_virtual SoC which was mainlined while the fixes for the ZynqMP were being developed (minus the OCM mapping, as there's no indication that this type of memory was considered). The cortex_r8_virtual appears to be a stripped down copy of the old qemu_cortex_r5 codebase, therefore, the duplicated MPU regions have the same flaws as qemu_cortex_r5 or any actual ZynqMP-based target for that matter. Signed-off-by: Immo Birnbaum --- .../cortex_r8_virtual/arm_mpu_regions.c | 105 +++++++++--------- 1 file changed, 55 insertions(+), 50 deletions(-) diff --git a/soc/renode/cortex_r8_virtual/arm_mpu_regions.c b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c index 8287a0651d4d00..6a9ea54ed352c3 100644 --- a/soc/renode/cortex_r8_virtual/arm_mpu_regions.c +++ b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c @@ -2,62 +2,67 @@ * * Copyright (c) 2021 Lexmark International, Inc. * Copyright (c) 2024 Antmicro + * Copyright (c) 2024 Immo Birnbaum */ #include -#include +#include -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +extern const uint32_t __rom_region_start; +extern const uint32_t __rom_region_mpu_size_bits; -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } - -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } - -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } - -extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), - - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), - - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), - - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + /* + * The address of the vectors is determined by arch/arm/core/cortex_a_r/prep_c.c + * -> for v8-R, there's no other option than 0x0, HIVECS always gets cleared + */ + MPU_REGION_ENTRY( + "vectors", + 0x00000000, + REGION_64B, + {.rasr = P_RO_U_NA_Msk | + NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + /* Basic SRAM mapping is all data, R/W + XN */ + MPU_REGION_ENTRY( + "sram", + CONFIG_SRAM_BASE_ADDRESS, + REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), +#if defined(CONFIG_XIP) + /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), + /* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ + /* .text and .rodata are in RAM, flash is data only -> RO + XN */ + MPU_REGION_ENTRY( + "flash", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | + NOT_EXEC}), + /* add rom_region mapping for SRAM which is RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), +#endif /* CONFIG_XIP */ + MPU_REGION_ENTRY( + "peripherals", + 0xf8000000, + REGION_128M, + {.rasr = P_RW_U_NA_Msk | + DEVICE_SHAREABLE | + NOT_EXEC}), }; const struct arm_mpu_config mpu_config = {