diff --git a/boards/amd/kv260_r5/kv260_r5.dts b/boards/amd/kv260_r5/kv260_r5.dts index 85fb1c26891798..4aef0ae2f26616 100644 --- a/boards/amd/kv260_r5/kv260_r5.dts +++ b/boards/amd/kv260_r5/kv260_r5.dts @@ -12,6 +12,11 @@ model = "KV260 Cortex-R5"; compatible = "xlnx,zynqmp-r5"; + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 DT_SIZE_M(64)>; + }; + chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; diff --git a/boards/enclustra/mercury_xu/mercury_xu.dts b/boards/enclustra/mercury_xu/mercury_xu.dts index df51ab470c579e..d602eb5e2d2974 100644 --- a/boards/enclustra/mercury_xu/mercury_xu.dts +++ b/boards/enclustra/mercury_xu/mercury_xu.dts @@ -12,6 +12,11 @@ model = "Mercury XU"; compatible = "xlnx,zynqmp"; + sram0: memory@0 { + compatible = "mmio-sram"; + reg = <0 DT_SIZE_M(64)>; + }; + chosen { zephyr,console = &uart0; zephyr,shell-uart = &uart0; diff --git a/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb b/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb index c5dd6ea59f480b..abec19a51d95b9 100644 Binary files a/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb and b/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb differ diff --git a/boards/qemu/cortex_r5/qemu_cortex_r5.dts b/boards/qemu/cortex_r5/qemu_cortex_r5.dts index b23e9534ed498e..a071506d9ef6b7 100644 --- a/boards/qemu/cortex_r5/qemu_cortex_r5.dts +++ b/boards/qemu/cortex_r5/qemu_cortex_r5.dts @@ -12,6 +12,11 @@ model = "QEMU Cortex-R5"; compatible = "xlnx,zynqmp-qemu"; + sram0: memory@4000000 { + compatible = "mmio-sram"; + reg = <0x4000000 DT_SIZE_M(64)>; + }; + chosen { zephyr,sram = &sram0; zephyr,flash = &flash0; diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi index 65abc450543576..f5adec548a56da 100644 --- a/dts/arm/xilinx/zynqmp.dtsi +++ b/dts/arm/xilinx/zynqmp.dtsi @@ -19,12 +19,6 @@ compatible = "soc-nv-flash"; reg = <0xc0000000 DT_SIZE_M(32)>; }; - - sram0: memory@0 { - compatible = "mmio-sram"; - reg = <0 DT_SIZE_M(64)>; - }; - ocm: memory@fffc0000 { compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; reg = <0xfffc0000 DT_SIZE_K(256)>; diff --git a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld index 239ab62129371a..ae922c075aff47 100644 --- a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld +++ b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld @@ -250,7 +250,7 @@ SECTIONS __rodata_region_end = .; __rom_region_end = .; MPU_ALIGN(__rodata_region_end - __rom_region_start); - _image_rom_end_order = (LOG2CEIL(__rom_region_end) - 1) << 1; + __rom_region_mpu_size_bits = (LOG2CEIL(__rodata_region_end - __rom_region_start) - 1) << 1; GROUP_END(ROMABLE_REGION) diff --git a/soc/renode/cortex_r8_virtual/arm_mpu_regions.c b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c index 8287a0651d4d00..6a9ea54ed352c3 100644 --- a/soc/renode/cortex_r8_virtual/arm_mpu_regions.c +++ b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c @@ -2,62 +2,67 @@ * * Copyright (c) 2021 Lexmark International, Inc. * Copyright (c) 2024 Antmicro + * Copyright (c) 2024 Immo Birnbaum */ #include -#include +#include -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +extern const uint32_t __rom_region_start; +extern const uint32_t __rom_region_mpu_size_bits; -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } - -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } - -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } - -extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), - - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), - - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), - - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + /* + * The address of the vectors is determined by arch/arm/core/cortex_a_r/prep_c.c + * -> for v8-R, there's no other option than 0x0, HIVECS always gets cleared + */ + MPU_REGION_ENTRY( + "vectors", + 0x00000000, + REGION_64B, + {.rasr = P_RO_U_NA_Msk | + NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + /* Basic SRAM mapping is all data, R/W + XN */ + MPU_REGION_ENTRY( + "sram", + CONFIG_SRAM_BASE_ADDRESS, + REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), +#if defined(CONFIG_XIP) + /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), + /* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ + /* .text and .rodata are in RAM, flash is data only -> RO + XN */ + MPU_REGION_ENTRY( + "flash", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | + NOT_EXEC}), + /* add rom_region mapping for SRAM which is RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), +#endif /* CONFIG_XIP */ + MPU_REGION_ENTRY( + "peripherals", + 0xf8000000, + REGION_128M, + {.rasr = P_RW_U_NA_Msk | + DEVICE_SHAREABLE | + NOT_EXEC}), }; const struct arm_mpu_config mpu_config = { diff --git a/soc/xlnx/zynqmp/arm_mpu_regions.c b/soc/xlnx/zynqmp/arm_mpu_regions.c index a4f36402d2cc72..f371c1173c15a6 100644 --- a/soc/xlnx/zynqmp/arm_mpu_regions.c +++ b/soc/xlnx/zynqmp/arm_mpu_regions.c @@ -1,62 +1,76 @@ /* SPDX-License-Identifier: Apache-2.0 * * Copyright (c) 2021 Lexmark International, Inc. + * Copyright (c) 2024 Immo Birnbaum */ #include -#include +#include -#define MPUTYPE_READ_ONLY \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (7 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_C_Msk \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } +extern const uint32_t __rom_region_start; +extern const uint32_t __rom_region_mpu_size_bits; -#define MPUTYPE_READ_ONLY_PRIV \ - { \ - .rasr = (P_RO_U_RO_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk) \ - } - -#define MPUTYPE_PRIV_WBWACACHE_XN \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (5 << MPU_RASR_TEX_Pos) \ - | MPU_RASR_B_Msk \ - | MPU_RASR_XN_Msk) \ - } - -#define MPUTYPE_PRIV_DEVICE \ - { \ - .rasr = (P_RW_U_NA_Msk \ - | (2 << MPU_RASR_TEX_Pos)) \ - } - -extern uint32_t _image_rom_end_order; static const struct arm_mpu_region mpu_regions[] = { - MPU_REGION_ENTRY("FLASH0", - 0xc0000000, - REGION_32M, - MPUTYPE_READ_ONLY), - - MPU_REGION_ENTRY("SRAM_PRIV", - 0x00000000, - REGION_2G, - MPUTYPE_PRIV_WBWACACHE_XN), - - MPU_REGION_ENTRY("SRAM", - 0x00000000, - ((uint32_t)&_image_rom_end_order), - MPUTYPE_READ_ONLY_PRIV), - - MPU_REGION_ENTRY("REGISTERS", - 0xf8000000, - REGION_128M, - MPUTYPE_PRIV_DEVICE), + /* + * The address of the vectors is determined by arch/arm/core/cortex_a_r/prep_c.c + * -> for v7-R, there's no other option than 0x0, HIVECS always gets cleared + */ + MPU_REGION_ENTRY( + "vectors", + 0x00000000, + REGION_64B, + {.rasr = P_RO_U_NA_Msk | + NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE}), + /* Basic SRAM mapping is all data, R/W + XN */ + MPU_REGION_ENTRY( + "sram", + CONFIG_SRAM_BASE_ADDRESS, + REGION_SRAM_SIZE, + {.rasr = P_RW_U_NA_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | + NOT_EXEC}), +#if defined(CONFIG_XIP) + /* .text and .rodata (=rom_region) are in flash, must be RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE}), + /* RAM contains R/W data, non-executable */ +#else /* !CONFIG_XIP */ + /* .text and .rodata are in RAM, flash is data only -> RO + XN */ + MPU_REGION_ENTRY( + "flash", + CONFIG_FLASH_BASE_ADDRESS, + REGION_FLASH_SIZE, + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE | + NOT_EXEC}), + /* add rom_region mapping for SRAM which is RO + executable */ + MPU_REGION_ENTRY( + "rom_region", + (uint32_t)(&__rom_region_start), + (uint32_t)(&__rom_region_mpu_size_bits), + {.rasr = P_RO_U_RO_Msk | + NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE}), +#endif /* CONFIG_XIP */ + MPU_REGION_ENTRY( + "peripherals", + 0xf8000000, + REGION_128M, + {.rasr = P_RW_U_NA_Msk | + DEVICE_SHAREABLE | + NOT_EXEC}), +#if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)) && !defined(CONFIG_TEST) + MPU_REGION_ENTRY( + "ocm", + DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)), + REGION_256K, + {.rasr = FULL_ACCESS_Msk | + STRONGLY_ORDERED_SHAREABLE | + NOT_EXEC}), +#endif }; const struct arm_mpu_config mpu_config = {