drivers: sdhc: Add support for SDHC driver on EK-RA8D1 and MCK-RA8T1

Add config to support SDHC driver on EK-RA8D1 and MCK-RA8T1 Signed-off-by: Tran Van Quy <[email protected]>
zephyrproject-rtos · Nov 13, 2024 · e218cb3 · e218cb3
1 parent 7009fd8
commit e218cb3
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diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst
@@ -110,6 +110,8 @@ The below features are currently supported on Zephyr OS for EK-RA8D1 board:
 +--------------+------------+------------------+
 | CAN          | on-chip    | canfd            |
 +--------------+------------+------------------+
+| SDHC         | on-chip    | sdhc             |
++--------------+------------+------------------+
 
 Other hardware features are currently not supported by the port.
 

diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi
@@ -45,4 +45,23 @@
 			drive-strength = "high";
 		};
 	};
+
+	sdhc1_default: sdhc1_default {
+		group1 {
+			/* SDCD SDCMD SDDATA0 SDDATA1 SDDATA2 SDDATA3 SDWP */
+			psels = <RA_PSEL(RA_PSEL_SDHI, 4, 6)>,
+			<RA_PSEL(RA_PSEL_SDHI, 4, 1)>,
+			<RA_PSEL(RA_PSEL_SDHI, 4, 2)>,
+			<RA_PSEL(RA_PSEL_SDHI, 4, 3)>,
+			<RA_PSEL(RA_PSEL_SDHI, 4, 4)>,
+			<RA_PSEL(RA_PSEL_SDHI, 4, 5)>,
+			<RA_PSEL(RA_PSEL_SDHI, 7, 0)>;
+			drive-strength = "high";
+		};
+		group2 {
+			/* SDCLK */
+			psels = <RA_PSEL(RA_PSEL_SDHI, 4, 0)>;   /* P400 */
+			drive-strength = "highspeed-high";
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts
@@ -42,6 +42,7 @@
 
 	aliases {
 		led0 = &led1;
+		sdhc0 = &sdhc1;
 	};
 };
 

diff --git a/boards/renesas/mck_ra8t1/doc/index.rst b/boards/renesas/mck_ra8t1/doc/index.rst
@@ -108,6 +108,8 @@ The below features are currently supported on Zephyr OS for MCB-RA8T1 board:
 +--------------+------------+----------------------+
 | CAN          | on-chip    | canfd                |
 +--------------+------------+----------------------+
+| SDHC         | on-chip    | sdhc                 |
++--------------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 

diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi
@@ -45,4 +45,23 @@
 			drive-strength = "high";
 		};
 	};
+
+	sdhc0_default: sdhc0_default {
+		group1 {
+			/* SDCD SDCMD SDDATA0 SDDATA1 SDDATA2 SDDATA3 SDWP */
+			psels = <RA_PSEL(RA_PSEL_SDHI, 3, 6)>,
+			<RA_PSEL(RA_PSEL_SDHI, 3, 7)>,
+			<RA_PSEL(RA_PSEL_SDHI, 3, 4)>,
+			<RA_PSEL(RA_PSEL_SDHI, 3, 3)>,
+			<RA_PSEL(RA_PSEL_SDHI, 3, 2)>,
+			<RA_PSEL(RA_PSEL_SDHI, 3, 1)>,
+			<RA_PSEL(RA_PSEL_SDHI, 3, 5)>;
+			drive-strength = "high";
+		};
+		group2 {
+			/* SDCLK */
+			psels = <RA_PSEL(RA_PSEL_SDHI, 3, 8)>;   /* P308 */
+			drive-strength = "highspeed-high";
+		};
+	};
 };
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts
@@ -46,6 +46,7 @@
 
 	aliases {
 		led0 = &led1;
+		sdhc0 = &sdhc0;
 	};
 };
 
@@ -87,6 +88,10 @@
 	status = "okay";
 };
 
+&ioport3 {
+	status = "okay";
+};
+
 &ioport6 {
 	status = "okay";
 };
@@ -145,3 +150,11 @@
 		status = "okay";
 	};
 };
+
+&sdhc0 {
+	compatible = "renesas,ra-sdhc";
+	pinctrl-0 = <&sdhc0_default>;
+	enable-gpios = <&ioport3 11 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	status = "okay";
+};
-Original file line number
+Diff line change
@@ Expand Up @@
     +--------------+------------+------------------+
     | CAN          | on-chip    | canfd            |
     +--------------+------------+------------------+
+    | SDHC         | on-chip    | sdhc             |
+    +--------------+------------+------------------+
     Other hardware features are currently not supported by the port.
@@ Expand Down @@