From 3ad12a8886d30c67b6a7ca8bb064886f36f4e9da Mon Sep 17 00:00:00 2001
From: Francois Ramu <francois.ramu@st.com>
Date: Tue, 26 Nov 2024 16:35:05 +0100
Subject: [PATCH] dts: arm: stm32f412 device has a clock 48MHz multiplexer

Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
---
 dts/arm/st/f4/stm32f412.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/dts/arm/st/f4/stm32f412.dtsi b/dts/arm/st/f4/stm32f412.dtsi
index d250d167259d8d5..6ec9381a4290000 100644
--- a/dts/arm/st/f4/stm32f412.dtsi
+++ b/dts/arm/st/f4/stm32f412.dtsi
@@ -16,6 +16,12 @@
 			compatible = "st,stm32f412-plli2s-clock";
 			status = "disabled";
 		};
+
+		clk48: clk48 {
+			#clock-cells = <0>;
+			compatible = "st,stm32-clock-mux";
+			status = "disabled";
+		};
 	};
 
 	soc {
@@ -201,8 +207,7 @@
 		};
 
 		sdmmc1: sdmmc@40012c00 {
-			clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
-				 <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 		};
 
 		quadspi: quadspi@a0001000 {