From 5a877290bb98a549691448e7540ba258a652f0bf Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Mon, 11 Sep 2023 15:44:28 +0800 Subject: [PATCH] arch: common: sw_isr_common: Move table index computing logic to function Borrow from #61422. Will rebased after it is merged. Signed-off-by: Yong Cong Sin --- arch/common/sw_isr_common.c | 43 ++++++++++++++++++++--------------- include/zephyr/sw_isr_table.h | 10 ++++++++ 2 files changed, 35 insertions(+), 18 deletions(-) diff --git a/arch/common/sw_isr_common.c b/arch/common/sw_isr_common.c index 538c03603f28024..0fbc14cb2e5a50d 100644 --- a/arch/common/sw_isr_common.c +++ b/arch/common/sw_isr_common.c @@ -71,40 +71,28 @@ unsigned int get_parent_offset(unsigned int parent_irq, #endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */ -void z_isr_install(unsigned int irq, void (*routine)(const void *), - const void *param) +unsigned int get_sw_isr_table_idx(unsigned int irq) { unsigned int table_idx; - /* - * Do not assert on the IRQ enable status for ARM GIC since the SGI - * type interrupts are always enabled and attempting to install an ISR - * for them will cause the assertion to fail. - */ -#ifndef CONFIG_GIC - __ASSERT(!irq_is_enabled(irq), "IRQ %d is enabled", irq); -#endif /* !CONFIG_GIC */ - #ifdef CONFIG_MULTI_LEVEL_INTERRUPTS - unsigned int level; - unsigned int parent_irq; - unsigned int parent_offset; + unsigned int level, parent_irq, parent_offset; level = irq_get_level(irq); if (level == 2U) { parent_irq = irq_parent_level_2(irq); parent_offset = get_parent_offset(parent_irq, - lvl2_irq_list, - CONFIG_NUM_2ND_LEVEL_AGGREGATORS); + lvl2_irq_list, + CONFIG_NUM_2ND_LEVEL_AGGREGATORS); table_idx = parent_offset + irq_from_level_2(irq); } #ifdef CONFIG_3RD_LEVEL_INTERRUPTS else if (level == 3U) { parent_irq = irq_parent_level_3(irq); parent_offset = get_parent_offset(parent_irq, - lvl3_irq_list, - CONFIG_NUM_3RD_LEVEL_AGGREGATORS); + lvl3_irq_list, + CONFIG_NUM_3RD_LEVEL_AGGREGATORS); table_idx = parent_offset + irq_from_level_3(irq); } #endif /* CONFIG_3RD_LEVEL_INTERRUPTS */ @@ -117,6 +105,25 @@ void z_isr_install(unsigned int irq, void (*routine)(const void *), table_idx = irq - CONFIG_GEN_IRQ_START_VECTOR; #endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */ + return table_idx; +} + +void z_isr_install(unsigned int irq, void (*routine)(const void *), + const void *param) +{ + unsigned int table_idx; + + /* + * Do not assert on the IRQ enable status for ARM GIC since the SGI + * type interrupts are always enabled and attempting to install an ISR + * for them will cause the assertion to fail. + */ +#ifndef CONFIG_GIC + __ASSERT(!irq_is_enabled(irq), "IRQ %d is enabled", irq); +#endif /* !CONFIG_GIC */ + + table_idx = get_sw_isr_table_idx(irq); + /* If dynamic IRQs are enabled, then the _sw_isr_table is in RAM and * can be modified */ diff --git a/include/zephyr/sw_isr_table.h b/include/zephyr/sw_isr_table.h index 3fd687d2c58d65c..60b4da04e5de235 100644 --- a/include/zephyr/sw_isr_table.h +++ b/include/zephyr/sw_isr_table.h @@ -61,6 +61,16 @@ struct _isr_list { const void *param; }; +/** + * @brief Helper function used to compute the index in _sw_isr_table + * based on passed IRQ. + * + * @param irq IRQ number in its zephyr format + * + * @return corresponding index in _sw_isr_table + */ +unsigned int get_sw_isr_table_idx(unsigned int irq); + /** This interrupt gets put directly in the vector table */ #define ISR_FLAG_DIRECT BIT(0)