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It would help with visualization I think if we encapsulate logical X, Y, Z and stabilize with custom gates, so that circuit visualizations are more reasonable. Then, if a user wants to decompose the circuit further they can to see the same circuit visualizations that we currently have.
The text was updated successfully, but these errors were encountered:
Also, it would be cool if we could show the internal gates that compose a logical X gate (for example) and also denote that these gates constitute an overall logical X (i.e. add in some text over the barrier constrained region with the logical X gates).
It would help with visualization I think if we encapsulate logical X, Y, Z and stabilize with custom gates, so that circuit visualizations are more reasonable. Then, if a user wants to decompose the circuit further they can to see the same circuit visualizations that we currently have.
The text was updated successfully, but these errors were encountered: