diff --git a/src/cpu/cb_opcodes.rs b/src/cpu/cb_opcodes.rs
index 921da39..d191e1d 100644
--- a/src/cpu/cb_opcodes.rs
+++ b/src/cpu/cb_opcodes.rs
@@ -10,9 +10,9 @@ impl GameBoy {
             .update_zero_flag(if self.flags.zero { 1 } else { 0 });
     }
 
-    fn reset_ram(&mut self, address: u16, offset: u8) {
-        let mut byte_from_ram = self.bus[address].clone();
-        byte_from_ram.set_bit(offset, false);
+    fn set_bit_ram(&mut self, address: u16, offset: u8, value: bool) {
+        let mut byte_from_ram = self.bus[address];
+        byte_from_ram.set_bit(offset, value);
 
         self.bus[address] = byte_from_ram;
     }
@@ -91,14 +91,24 @@ impl GameBoy {
             0x7E => { self.bit_r(self.bus[self.registers.get_hl()], 7); (1, 3) },
 
             // RESET RAM, <bit offset>
-            0x86 => { self.reset_ram(self.registers.get_hl(), 0); (1, 4) }
-            0x8E => { self.reset_ram(self.registers.get_hl(), 1); (1, 4) }
-            0x96 => { self.reset_ram(self.registers.get_hl(), 2); (1, 4) }
-            0x9E => { self.reset_ram(self.registers.get_hl(), 3); (1, 4) }
-            0xA6 => { self.reset_ram(self.registers.get_hl(), 4); (1, 4) }
-            0xAE => { self.reset_ram(self.registers.get_hl(), 5); (1, 4) }
-            0xB6 => { self.reset_ram(self.registers.get_hl(), 6); (1, 4) }
-            0xBE => { self.reset_ram(self.registers.get_hl(), 7); (1, 4) }
+            0x86 => { self.set_bit_ram(self.registers.get_hl(), 0, false); (1, 4) },
+            0x8E => { self.set_bit_ram(self.registers.get_hl(), 1, false); (1, 4) },
+            0x96 => { self.set_bit_ram(self.registers.get_hl(), 2, false); (1, 4) },
+            0x9E => { self.set_bit_ram(self.registers.get_hl(), 3, false); (1, 4) },
+            0xA6 => { self.set_bit_ram(self.registers.get_hl(), 4, false); (1, 4) },
+            0xAE => { self.set_bit_ram(self.registers.get_hl(), 5, false); (1, 4) },
+            0xB6 => { self.set_bit_ram(self.registers.get_hl(), 6, false); (1, 4) },
+            0xBE => { self.set_bit_ram(self.registers.get_hl(), 7, false); (1, 4) },
+
+            // SET RAM, <bit offset>
+            0xC6 => { self.set_bit_ram(self.registers.get_hl(), 0, true); (1, 4) },
+            0xCE => { self.set_bit_ram(self.registers.get_hl(), 1, true); (1, 4) },
+            0xD6 => { self.set_bit_ram(self.registers.get_hl(), 2, true); (1, 4) },
+            0xDE => { self.set_bit_ram(self.registers.get_hl(), 3, true); (1, 4) },
+            0xE6 => { self.set_bit_ram(self.registers.get_hl(), 4, true); (1, 4) },
+            0xEE => { self.set_bit_ram(self.registers.get_hl(), 5, true); (1, 4) },
+            0xF6 => { self.set_bit_ram(self.registers.get_hl(), 6, true); (1, 4) },
+            0xFE => { self.set_bit_ram(self.registers.get_hl(), 7, true); (1, 4) },
 
             _ => panic!("Opcode 0xcb{:x} not implemented yet", opcode),
         }