From 47ff05074ccfdc5d16e3b8fc6fca5a78f8af44fe Mon Sep 17 00:00:00 2001
From: velllu <91963404+velllu@users.noreply.github.com>
Date: Fri, 24 Nov 2023 18:16:24 +0100
Subject: [PATCH] Fixed opcodes `2A` and `3A`

- They used to set the zero flag, which is not accurate
- They incremented/subtracted the a register instead
of the hl register
---
 src/cpu/opcodes.rs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/cpu/opcodes.rs b/src/cpu/opcodes.rs
index 1f75175..f033ec3 100644
--- a/src/cpu/opcodes.rs
+++ b/src/cpu/opcodes.rs
@@ -325,13 +325,13 @@ impl GameBoy {
             0x6E => { self.load_ram_into_r(self.registers.get_hl(), OneByteRegister::L); (1, 2) },
             0x7E => { self.load_ram_into_r(self.registers.get_hl(), OneByteRegister::A); (1, 2) },
             0x2A => {
-                self.load_ram_into_r(self.registers.get_hl(), OneByteRegister::A);
-                self.increment_r(OneByteRegister::A, Operator::Inc, 1);
+                self.registers.a = self.bus[self.registers.get_hl()];
+                self.registers.increment_hl(1, Operator::Inc);
                 (1, 2)
             },
             0x3A => {
-                self.load_ram_into_r(self.registers.get_hl(), OneByteRegister::A);
-                self.increment_r(OneByteRegister::A, Operator::Sub, 1);
+                self.registers.a = self.bus[self.registers.get_hl()];
+                self.registers.increment_hl(1, Operator::Sub);
                 (1, 2)
             },