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axi_vip.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2017.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="D:/A_Design/FPGA_design/Vivado/SATA_0601/axi_vip/axi_vip.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="cdd15fa57ff64711847a1f64821551d3"/>
<Option Name="Part" Val="xc7v585tffg1157-2"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="23"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="1"/>
<Option Name="WTModelSimExportSim" Val="1"/>
<Option Name="WTQuestaExportSim" Val="1"/>
<Option Name="WTIesExportSim" Val="1"/>
<Option Name="WTVcsExportSim" Val="1"/>
<Option Name="WTRivieraExportSim" Val="1"/>
<Option Name="WTActivehdlExportSim" Val="1"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/axi_sim/axi_sim.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="axi_sim.bd" FileRelPathName="ip/axi_sim_auto_pc_0/axi_sim_auto_pc_0.xci">
<Proxy FileSetName="axi_sim_auto_pc_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="axi_sim.bd" FileRelPathName="ip/axi_sim_axi_bram_ctrl_0_0/axi_sim_axi_bram_ctrl_0_0.xci">
<Proxy FileSetName="axi_sim_axi_bram_ctrl_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="axi_sim.bd" FileRelPathName="ip/axi_sim_axi_vip_0_0/axi_sim_axi_vip_0_0.xci">
<Proxy FileSetName="axi_sim_axi_vip_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="axi_sim.bd" FileRelPathName="ip/axi_sim_xbar_0/axi_sim_xbar_0.xci">
<Proxy FileSetName="axi_sim_xbar_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="axi_sim.bd" FileRelPathName="ip/axi_sim_blk_mem_gen_0_0/axi_sim_blk_mem_gen_0_0.xci">
<Proxy FileSetName="axi_sim_blk_mem_gen_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="axi_sim.bd" FileRelPathName="ip/axi_sim_sim_clk_gen_0_0/axi_sim_sim_clk_gen_0_0.xci">
<Proxy FileSetName="axi_sim_sim_clk_gen_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/axi_sim/hdl/axi_sim_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="axi_sim_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/tb_axi_vip.v">
<FileInfo SFType="SVerilog">
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/tb_axi_vip_behav.wcfg">
<FileInfo>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="tb_axi_vip"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/tb_axi_vip_behav.wcfg"/>
<Option Name="xsim.simulate.runtime" Val="30us"/>
<Option Name="xsim.simulate.log_all_signals" Val="true"/>
</Config>
</FileSet>
<FileSet Name="axi_sim_auto_pc_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_sim_auto_pc_0">
<Config>
<Option Name="TopModule" Val="axi_sim_auto_pc_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axi_sim_axi_bram_ctrl_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_sim_axi_bram_ctrl_0_0">
<Config>
<Option Name="TopModule" Val="axi_sim_axi_bram_ctrl_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axi_sim_axi_vip_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_sim_axi_vip_0_0">
<Config>
<Option Name="TopModule" Val="axi_sim_axi_vip_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axi_sim_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_sim_xbar_0">
<Config>
<Option Name="TopModule" Val="axi_sim_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axi_sim_blk_mem_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_sim_blk_mem_gen_0_0">
<Config>
<Option Name="TopModule" Val="axi_sim_blk_mem_gen_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axi_sim_sim_clk_gen_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_sim_sim_clk_gen_0_0">
<Config>
<Option Name="TopModule" Val="axi_sim_sim_clk_gen_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7v585tffg1157-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
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<Step Id="synth_design"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="axi_sim_auto_pc_0_synth_1" Type="Ft3:Synth" SrcSet="axi_sim_auto_pc_0" Part="xc7v585tffg1157-2" ConstrsSet="axi_sim_auto_pc_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" IncludeInArchive="true">
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<Desc>Vivado Synthesis Defaults</Desc>
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<Run Id="axi_sim_axi_bram_ctrl_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_sim_axi_bram_ctrl_0_0" Part="xc7v585tffg1157-2" ConstrsSet="axi_sim_axi_bram_ctrl_0_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" IncludeInArchive="true">
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<Run Id="axi_sim_axi_vip_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_sim_axi_vip_0_0" Part="xc7v585tffg1157-2" ConstrsSet="axi_sim_axi_vip_0_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" IncludeInArchive="true">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Run Id="axi_sim_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="axi_sim_xbar_0" Part="xc7v585tffg1157-2" ConstrsSet="axi_sim_xbar_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" IncludeInArchive="true">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="axi_sim_blk_mem_gen_0_0_synth_1" Type="Ft3:Synth" SrcSet="axi_sim_blk_mem_gen_0_0" Part="xc7v585tffg1157-2" ConstrsSet="axi_sim_blk_mem_gen_0_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" IncludeInArchive="true">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
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<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
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<Step Id="post_route_phys_opt_design"/>
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</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
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<Step Id="power_opt_design"/>
<Step Id="place_design"/>
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<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Board/>
</Project>