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The fix proposed in the webpage is to change SYSTEM_OSC48M_DIV_3 to SYSTEM_OSC48M_DIV_1.
This causes issues for the board for unknown reasons; it fails to finish it’s configuration. Instead we will change the CAN configurations in the conf_can.h file. The documentation http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42464-SAMC21-CAN-BUS-Firmware_ApplicationNote_AT6493.pdf ; as per the documentation “48MHz / (5 + 1) = 8MHz, and each bit is (3 + 10 + 3) or 16 time quanta which is 8MHz / 16 = 500kHz.”. Now our clock because of the division by 3 is not 48MHz but rather 16MHz. Anaylsising the equation that they provided means that simply changing the NBRP value from a 5 to a 1 should remedy this issue.
**sorry for the poor formatting
The text was updated successfully, but these errors were encountered:
Hi Calvin, thanks for raising this issue, it definitely seems that the code in this repo is misconfigured. As you identified, there are 2 possible remedies:
Change system clock frequency to 48MHz
Change the CAN bitrate prescalers (NBRP and DBRP) to account for a system clock frequency of 16MHz
The reason the first one didn't work for you is probably because of the lack of wait states. According to the SAMC21 reference manual, you'd need at least flash 2 wait states at 48MHz to prevent it from locking up. See below:
The second could also work if you don't need to run at 48MHz (which for any simple DAQ application, you probably don't). Also, note that the CAN peripheral app note and documentation (including the default documentation in this repo) is quite wrong and should not be depended on. I found this thread very helpful for understanding this CAN peripheral.
Feel free to open a pull request to get this resolved!
Clock misconfigure issue
As identified here http://www.electronicsworkshop.eu/SAMC21XplainedPro-CAN-Troubleshooting the samC21 can operate and a clock speed of ⅓ of the normal. This is caused by this line in the conf_clocks.h file:
# define CONF_CLOCK_OSC48M_FREQ_DIV SYSTEM_OSC48M_DIV_3
The fix proposed in the webpage is to change SYSTEM_OSC48M_DIV_3 to SYSTEM_OSC48M_DIV_1.
This causes issues for the board for unknown reasons; it fails to finish it’s configuration. Instead we will change the CAN configurations in the conf_can.h file. The documentation http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42464-SAMC21-CAN-BUS-Firmware_ApplicationNote_AT6493.pdf ; as per the documentation “48MHz / (5 + 1) = 8MHz, and each bit is (3 + 10 + 3) or 16 time quanta which is 8MHz / 16 = 500kHz.”. Now our clock because of the division by 3 is not 48MHz but rather 16MHz. Anaylsising the equation that they provided means that simply changing the NBRP value from a 5 to a 1 should remedy this issue.
**sorry for the poor formatting
The text was updated successfully, but these errors were encountered: