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#ntt_kyber_layer345_symbolic_opt.s#
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#ntt_kyber_layer345_symbolic_opt.s#
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.macro mulmod dst, src, const, const_twisted
vmul.s16 \dst, \src, \const
vqrdmulh.s16 \src, \src, \const_twisted
vmla.s16 \dst, \src, modulus
.endm
.macro ct_butterfly a, b, root, root_twisted
mulmod tmp, \b, \root, \root_twisted
vsub.u16 \b, \a, tmp
vadd.u16 \a, \a, tmp
.endm
.macro load_next_roots r0, r1, r2, r3, r4, r5, r6
ldrd \r0, \r0\()_tw, [r]
ldrd \r1, \r1\()_tw, [r, #(-6*16)]
ldrd \r2, \r2\()_tw, [r, #(-5*16)]
ldrd \r3, \r3\()_tw, [r, #(-4*16)]
ldrd \r4, \r4\()_tw, [r, #(-3*16)]
ldrd \r5, \r5\()_tw, [r, #(-2*16)]
ldrd \r6, \r6\()_tw, [r, #(-1*16)]
.endm
ldrd r3, r8, [r]
vldrw.u32 q3, [in, #112]
vqrdmulh.s16 q5, q3, r8
vldrw.u32 q0, [in, #96]
vmul.s16 q7, q3, r3
vldrw.u32 q1, [in, #80]
vmla.s16 q7, q5, modulus
vldrw.u32 q6, [in, #48]
vqrdmulh.s16 q3, q0, r8
vadd.u16 q4, q6, q7
vmul.s16 q0, q0, r3
ldrd r7, r9, [r, #-96]
vmla.s16 q0, q3, modulus
vldrw.u32 q3, [in, #32]
vmul.s16 q2, q1, r3
vadd.u16 q5, q3, q0
vqrdmulh.s16 q1, q1, r8
vsub.u16 q3, q3, q0
vmla.s16 q2, q1, modulus
vldrw.u32 q1, [in, #16]
vsub.u16 q0, q1, q2
qsave QSTACK1, q3
vqrdmulh.s16 q3, q4, r9
qsave QSTACK0, q0
vsub.u16 q6, q6, q7
vmul.s16 q0, q4, r7
vadd.u16 q4, q1, q2
vmla.s16 q0, q3, modulus
vldrw.u32 q7, [in, #64]
vsub.u16 q3, q4, q0
vmul.s16 q2, q7, r3
vadd.u16 q1, q4, q0
vqrdmulh.s16 q0, q7, r8
ldrd r8, r3, [r, #-80]
vmla.s16 q2, q0, modulus
vldrw.u32 q0, [in]
vsub.u16 q4, q0, q2
vqrdmulh.s16 q7, q5, r9
vadd.u16 q0, q0, q2
vmul.s16 q2, q5, r7
qsave QSTACK5, q4
vmla.s16 q2, q7, modulus
ldrd r1, r2, [r, #-48]
vqrdmulh.s16 q5, q1, r3
.p2align 2
layer345_loop:
qsave QSTACK4, q5 // .................................................................................................................................*................................................
vmul.s16 q5, q7, r0 // ..................................................................................................................*...............................................................
qsave QSTACK0, q0 // .......................*..........................................................................................................................................................
vqrdmulh.s16 q7, q7, r5 // ...............................................................................................................*..................................................................
ldrd r6, r4, [r, #-48] // ...................................................................................................................................*..............................................
vmla.s16 q5, q7, modulus // ....................................................................................................................*.............................................................
qrestore q7, QSTACK2 // ......................................................................................................................................................*...........................
vqrdmulh.s16 q7, q4, r4 // ..............................................................................................................................................*...................................
vsub.u16 q7, q6, q5 // ......................................................................................................................*...........................................................
vstrw.u32 q7, [in, #16] // ............................................................................................................................................*.....................................
vadd.u16 q6, q6, q5 // ........................................................................................................................*.........................................................
vmul.s16 q5, q4, r6 // ..........................................................................................................................................*.......................................
vstrw.u32 q3, [in, #96] // .................................................................................................................................................................................*
vmul.s16 q4, q3, r7 // ..............................................................*...................................................................................................................
qsave QSTACK5, q4 // ........................................*.........................................................................................................................................
vmul.s16 q3, q7, r0 // .......................................................................................................................................................*..........................
ldrd r8, r7, [r, #-80] // ..........................................................................................................................*.......................................................
vmla.s16 q4, q2, modulus // ................................................................*.................................................................................................................
vldrw.u32 q2, [in, #96] // ............................................................................................*.....................................................................................
vsub.u16 q3, q0, q4 // .......................................................................*..........................................................................................................
vqrdmulh.s16 q5, q2, r9 // .................................................................................................*................................................................................
vadd.u16 q4, q0, q4 // ...................................................................*..............................................................................................................
vmul.s16 q0, q2, r3 // ...................................................................................................*..............................................................................
vldrw.u32 q2, [in, #32] // ......................................................................................................*...........................................................................
vmla.s16 q0, q5, modulus // .....................................................................................................*............................................................................
vstrw.u32 q3, [in, #48] // ..................................................................................*...............................................................................................
vadd.u16 q5, q2, q0 // ........................................................................................................*.........................................................................
vmul.s16 q3, q5, r0 // ................................................................................................................................*.................................................
vstrw.u32 q4, [in, #32] // .....................................................................*............................................................................................................
vqrdmulh.s16 q4, q5, r5 // ..............................................................................................................................*...................................................
vsub.u16 q2, q2, q0 // ..........................................................................................................*.......................................................................
vmla.s16 q3, q4, modulus // ..................................................................................................................................*...............................................
qrestore q5, QSTACK0 // .............................................................*....................................................................................................................
vsub.u16 q0, q1, q3 // ....................................................................................................................................................*.............................
vqrdmulh.s16 q0, q6, r7 // ....................................................................................................................................*.............................................
vadd.u16 q4, q1, q3 // .........................................................................................................................................*........................................
vmla.s16 q1, q0, modulus // ........................................................................................................................................*.........................................
qsave QSTACK2, q2 // ..............................................................................................................*...................................................................
vmla.s16 q2, q1, modulus // ..................*...............................................................................................................................................................
vstrw.u32 q4, [in, #32] // ..............................................................................................................................................................*...................
vqrdmulh.s16 q1, q1, r4 // ...............................................................................................................................................................*..................
vsub.u16 q4, q0, q2 // ....................................*.............................................................................................................................................
vqrdmulh.s16 q4, q7, r4 // .....................................................................................................................................................*............................
vstrw.u32 q4, [in] // ..................................................................................................................................................*...............................
vmla.s16 q7, q5, modulus // ......*...........................................................................................................................................................................
vstrw.u32 q0, [in, #48] // ...........................................................................................................................................................................*......
vmla.s16 q7, q5, modulus // ...................................................................................................................................................................*..............
vstrw.u32 q5, [in, #64] // .........................................................................................................................................................................*........
vmla.s16 q2, q0, modulus // ..................................*...............................................................................................................................................
qrestore q2, QSTACK5 // .........................................................................*........................................................................................................
vmla.s16 q3, q4, modulus // .........................................................................................................................................................*........................
vldrw.u32 q1, [in, #80] // .....*............................................................................................................................................................................
vmla.s16 q0, q3, modulus // ............*.....................................................................................................................................................................
qrestore q4, QSTACK4 // ..................................................................................................................................................................*...............
vmla.s16 q0, q3, modulus // ...........................*......................................................................................................................................................
ldrd r3, r7, [r, #-32] // .....................................................................................................................................*............................................
vmul.s16 q1, q6, r8 // ......................................................................................................................................*...........................................
ldrd r3, r8, [r] // *.................................................................................................................................................................................
vmul.s16 q6, q1, r6 // ................................................................................................................................................*.................................
vsub.u16 q6, q6, q7 // ........................*.........................................................................................................................................................
vmul.s16 q4, q6, r1 // .................................................*................................................................................................................................
ldrd r0, r4, [r, #-64] // .................................................................................................................................................*................................
vqrdmulh.s16 q6, q6, r2 // .....................................................*............................................................................................................................
ldrd r8, r9, [r, #-32] // ............................................*.....................................................................................................................................
vmla.s16 q4, q6, modulus // ..........................................................*.......................................................................................................................
vldrw.u32 q6, [in, #48] // .......*..........................................................................................................................................................................
vsub.u16 q0, q5, q4 // ...............................................................*..................................................................................................................
vmul.s16 q1, q2, r9 // .....................................................................................................................................................................*............
vadd.u16 q5, q5, q4 // .................................................................*................................................................................................................
vmul.s16 q3, q5, r8 // ....................................................................*.............................................................................................................
vstrw.u32 q4, [in, #112] // ...............................................................................................................................................................................*..
vqrdmulh.s16 q7, q5, r9 // ..................................................................*...............................................................................................................
qrestore q5, QSTACK1 // ......................................................*...........................................................................................................................
vmul.s16 q4, q5, r1 // .......................................................*..........................................................................................................................
ldrd r9, r8, [r, #-16] // .......................................................................................................................................*..........................................
vqrdmulh.s16 q6, q5, r2 // ......................................................................*...........................................................................................................
ldrd r7, r3, [r, #-16] // ..............................................*...................................................................................................................................
vmla.s16 q4, q6, modulus // ........................................................................*.........................................................................................................
vadd.u16 q5, q3, q0 // ...............*..................................................................................................................................................................
vqrdmulh.s16 q1, q1, r8 // ................*.................................................................................................................................................................
vsub.u16 q5, q2, q4 // ...............................................................................*..................................................................................................
vmul.s16 q6, q0, r7 // ............................................................................*.....................................................................................................
vadd.u16 q2, q2, q4 // ...........................................................................*......................................................................................................
vqrdmulh.s16 q1, q0, r3 // ..............................................................................*...................................................................................................
vadd.u16 q4, q0, q3 // ............................................................................................................................................................*.....................
vmla.s16 q6, q1, modulus // .................................................................................*................................................................................................
ldrd r7, r9, [r, #-96] // ...........*......................................................................................................................................................................
vsub.u16 q4, q5, q6 // .....................................................................................*............................................................................................
le lr, layer345_loop
ldrd r3, r7, [r, #-32]
vmul.s16 q1, q1, r8
ldrd r9, r8, [r, #-16]
vmla.s16 q1, q5, modulus
vadd.u16 q4, q0, q2
vmul.s16 q5, q6, r1
vsub.u16 q7, q4, q1
vstrw.u32 q7, [in, #16]
vadd.u16 q4, q4, q1
vqrdmulh.s16 q7, q6, r2
qrestore q1, QSTACK1
vmul.s16 q6, q1, r1
ldrd r0, r4, [r, #-64]
vstrw.u32 q4, [in]
vmla.s16 q5, q7, modulus
vsub.u16 q0, q0, q2
vqrdmulh.s16 q4, q3, r4
qrestore q7, QSTACK0
vmul.s16 q3, q3, r0
vsub.u16 q2, q7, q5
vmla.s16 q3, q4, modulus
vadd.u16 q7, q7, q5
vqrdmulh.s16 q5, q7, r7
vadd.u16 q4, q0, q3
vmul.s16 q7, q7, r3
vstrw.u32 q4, [in, #32]
vqrdmulh.s16 q1, q1, r2
vsub.u16 q0, q0, q3
vmla.s16 q6, q1, modulus
qrestore q4, QSTACK5
vmla.s16 q7, q5, modulus
vadd.u16 q3, q4, q6
vmul.s16 q1, q2, r9
vadd.u16 q5, q3, q7
vqrdmulh.s16 q2, q2, r8
vsub.u16 q6, q4, q6
vstrw.u32 q5, [in, #64]
vmla.s16 q1, q2, modulus
vstrw.u32 q0, [in, #48]
vsub.u16 q0, q3, q7
vstrw.u32 q0, [in, #80]
vsub.u16 q4, q6, q1
vstrw.u32 q4, [in, #112]
vadd.u16 q3, q6, q1
vstrw.u32 q3, [in, #96]
layer345_loop_end: