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fix: typo in examples

thisisjubepushed 1 commit to riscv • 136af27…87cf058 • 
14 days ago

feat: use loop optimization for dilithium

thisisjubepushed 1 commit to riscv • 91bc53e…136af27 • 
14 days ago

refactor: adjust .gitignore

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thisisjubeforce pushed to sphinx_docs • e584780…d778222 • 
16 days ago

wip: start to adjust docstrings

thisisjubepushed 1 commit to sphinx_docs • 637edab…e584780 • 
16 days ago

feat: nearly full port of documentation to sphinx

thisisjubepushed 1 commit to sphinx_docs • f9a7c14…637edab • 
19 days ago

feat: Add loop parsing to riscv model

dop-aminpushed 1 commit to riscv • f46bec4…91bc53e • 
20 days ago

wip: add vector registers

thisisjubepushed 1 commit to riscv • 5f30e5d…f46bec4 • 
21 days ago

fix: fix weird display error

thisisjubepushed 1 commit to sphinx_docs • a17e430…f9a7c14 • 
21 days ago

fix: slothy -> SLOTHY

thisisjubepushed 1 commit to sphinx_docs • b67bf6a…a17e430 • 
21 days ago

doc: introduce sphinx documentation

thisisjubecreated sphinx_docs • b67bf6a • 
21 days ago

fix: add missing constants in asm code

thisisjubepushed 1 commit to riscv • 915ff0b…5f30e5d • 
21 days ago

fix: fix typos in XuanTie and rename optimized function for risc-v nt…

thisisjubepushed 1 commit to riscv • 3fa15be…915ff0b • 
21 days ago

feat: add timeout for risc-v example

thisisjubepushed 1 commit to riscv • 551d9ef…3fa15be • 
21 days ago

fix: missing function renaming after optimization

thisisjubepushed 1 commit to riscv • 1c30331…551d9ef • 
21 days ago

refactor: cleanup

thisisjubepushed 1 commit to riscv • ccd9e47…1c30331 • 
26 days ago

Merge branch 'main' into riscv

thisisjubepushed 35 commits to riscv • 3a7aad3…ccd9e47 • 
26 days ago

doc: update todo

thisisjubepushed 1 commit to riscv • e336d8c…3a7aad3 • 
26 days ago

Merge pull request slothy-optimizer#114 from slothy-optimizer/extend-…

thisisjubepushed 34 commits to main • 5a115f9…2ebb278 • 
26 days ago

refactor: move instruction factory to RISCVInstruction class

thisisjubepushed 1 commit to riscv • 274db25…e336d8c • 
28 days ago

refactor: clean up code, reformat according to PEP-8 style

thisisjubepushed 1 commit to riscv • b1fc513…274db25 • 
28 days ago

refactor: update copyright headers

thisisjubepushed 1 commit to riscv • 45d92ec…b1fc513 • 
28 days ago

feat: first heuristic split optimization

thisisjubepushed 1 commit to riscv • e77d78b…45d92ec • 
28 days ago

fix: fix wrong instruction defs and register names

thisisjubepushed 1 commit to riscv • ab36ff4…e77d78b • 
28 days ago

feat: split ntt_dilithium example

thisisjubepushed 1 commit to riscv • 3dd91cd…ab36ff4 • 
28 days ago

feat: opt

thisisjubepushed 1 commit to riscv • c547d35…3dd91cd • 
on Nov 24, 2024

feat: further optimizations

thisisjubepushed 1 commit to riscv • c56821d…c547d35 • 
on Nov 24, 2024

feat: optimize ntt_8l_singlissue_plant_rv64im.s

thisisjubepushed 1 commit to riscv • 19a88a5…c56821d • 
on Nov 24, 2024

feat: add uArch model

thisisjubepushed 1 commit to riscv • 8c93b9f…19a88a5 • 
on Nov 24, 2024

feat: add naive rv64im Dilithium NTTs from PQRV paper

dop-aminpushed 1 commit to riscv • 1d6511e…8c93b9f • 
on Nov 19, 2024

feat: add new testing code, add register aliases

thisisjubepushed 1 commit to riscv • 1e154db…1d6511e • 
on Nov 18, 2024