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west.yml: update Zephyr to 5689916a70ad #8126
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Yay, sparse tests green again! The |
Some trouble with at least HDA cAVS2.5 test in https://sof-ci.01.org/sofpr/PR8126/build12289/devicetest/index.html , need to investigate before merge. UPDATE: but ACE HDA test passes https://sof-ci.01.org/sofpr/PR8126/build12288/devicetest/index.html .. this is pretty strange. |
Fuzzer build clang regression bisected to @kartben's |
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V2 uploaded:
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Doh, we seem to have a regression:
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Regression found, caused by a patch by certain @kv2019i :( Fixed in zephyrproject-rtos/zephyr#62180 Marking as DNM and will reupload this PR once the fix is merged upstream. |
Contains 450+ commits, including following directly affecting SOF targets: 5689916a70ad soc: xtensa: intel_adsp: cavs: fix assert on L3_MEM_BASE_ADDR 34ea488da91c intel_adsp: ace20_lnl: add ALH DAI support b7e181c2708b soc: intel_adsp: add HDA buffer interrupt functions d68a58d6cd26 dts: xtensa: intel: add HDA DMA interrupt defs for ACE2.0 62c7729b3e1a dts: xtensa: intel: add HDA DMA interrupt defs for cAVS platforms c6c6c5a5ed64 soc: intel_adsp: ace shim: add force L1 defines 0fead68e2b8e Revert "llvm: use proper syntax for --config option" cd97eae73b4b soc: xtensa: intel_adsp: common: s/device.h/init.h 6cdabb4dff5e soc: xtensa: intel_adsp: common: add missing section_tags.h c360284c6e14 soc: xtensa: intel_adsp: add missing init.h ffd2121c65d3 soc: xtensa: intel_adsp: cavs: fix power_down_cavs() signature a1d7ffdc374d soc: xtensa: intel_adsp: cavs: fix incorrect cached/uncached cast ce7c30c12978 soc: intel_adsp/ace: use WAIT_FOR for core power transitions 3f0ee7f6db7a power_domain: intel_adsp: initialize after DMA ca23a5f0cf75 xtensa: mmu: allow SoC to do additional MMU init steps 088a31e2bffa xtensa: mmu: preload ITLB for VECBASE before restoring... 40f2486b685c xtensa: mmu: rename MMU_KERNEL_RING to Z_XTENSA_KERNEL_RING... 18eb17f4cd69 xtensa: mmu: add arch_reserved_pages_update 4778c13bbeab xtensa: mmu: handle all data TLB misses in double exception c723d8b8d3ac xtensa: Add missing synchronization 24148718fc6e xtensa: mmu: cache common data and heap if !XTENSA_RPO_CACHE b6ccbae58dc4 xtensa: mmu: use _image_ram_start/end for data region 257404a14327 xtensa: mmu: init: only clear enough entries in way 6 614e64325d48 xtensa: mmu: no longer identity map the first 512MB b5016714b082 xtensa: mmu: handle TLB misses during user exception 98ffd1addd6a xtensa: crt1: call z_xtensa_mmu_init 38d4b7872401 xtensa: mmu: remove printing vaddr registers during exception 3d63e2060edf dts: cpu: add cdns,tensilica-xtensa-lx3 Signed-off-by: Kai Vehmanen <[email protected]>
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V3 upload:
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One system PM fail in And one one system PM fail in We have a new sparse fail introduce by the L1 exit code: ... but that's already in merged Zephyr code, so this has to be (again) handled in a separate PR. Proceeding with merge. |
Fix submitted in |
Contains 367 commits, including following directly affecting SOF targets:
ffd2121c65d3 soc: xtensa: intel_adsp: cavs: fix power_down_cavs() signature
a1d7ffdc374d soc: xtensa: intel_adsp: cavs: fix incorrect cached/uncached cast
ce7c30c12978 soc: intel_adsp/ace: use WAIT_FOR for core power transitions
3f0ee7f6db7a power_domain: intel_adsp: initialize after DMA
ca23a5f0cf75 xtensa: mmu: allow SoC to do additional MMU init steps
088a31e2bffa xtensa: mmu: preload ITLB for VECBASE before restoring...
40f2486b685c xtensa: mmu: rename MMU_KERNEL_RING to Z_XTENSA_KERNEL_RING...
18eb17f4cd69 xtensa: mmu: add arch_reserved_pages_update
4778c13bbeab xtensa: mmu: handle all data TLB misses in double exception
c723d8b8d3ac xtensa: Add missing synchronization
24148718fc6e xtensa: mmu: cache common data and heap if !XTENSA_RPO_CACHE
b6ccbae58dc4 xtensa: mmu: use _image_ram_start/end for data region
257404a14327 xtensa: mmu: init: only clear enough entries in way 6
614e64325d48 xtensa: mmu: no longer identity map the first 512MB
b5016714b082 xtensa: mmu: handle TLB misses during user exception
98ffd1addd6a xtensa: crt1: call z_xtensa_mmu_init
38d4b7872401 xtensa: mmu: remove printing vaddr registers during exception
3d63e2060edf dts: cpu: add cdns,tensilica-xtensa-lx3