From f6e41a3a9ec41369b829e4e457e95424f6fd0649 Mon Sep 17 00:00:00 2001 From: Tomasz Leman Date: Wed, 6 Sep 2023 15:34:39 +0200 Subject: [PATCH] ace: clock: update clock definitions ACE_1.5 and ACE_2.0 use only two clocks for DSP cores. First is WOVRCO and second is ACE IPLL. IPLL allows to configure it to work like LP RING Oscillator Clock or HP RING Oscillator Clock. Currently, the driver does not allow this, so I remove the frequency that cannot be achieved anyway. Clocks frequencies: WOV: 38.4 MHz IPLL: 393.216 MHz Signed-off-by: Tomasz Leman --- src/platform/lunarlake/include/platform/lib/clk.h | 10 ++++------ src/platform/lunarlake/lib/clk.c | 5 ++--- src/platform/meteorlake/include/platform/lib/clk.h | 10 ++++------ src/platform/meteorlake/lib/clk.c | 5 ++--- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/src/platform/lunarlake/include/platform/lib/clk.h b/src/platform/lunarlake/include/platform/lib/clk.h index fe8f140ff0a6..77e72d8c6ccd 100644 --- a/src/platform/lunarlake/include/platform/lib/clk.h +++ b/src/platform/lunarlake/include/platform/lib/clk.h @@ -14,21 +14,19 @@ #include -#define CLK_MAX_CPU_HZ 400000000 +#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ #define CPU_WOVCRO_FREQ_IDX 0 -#define CPU_LPRO_FREQ_IDX 1 - -#define CPU_HPRO_FREQ_IDX 2 +#define CPU_IPLL_FREQ_IDX 1 #define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX -#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX +#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX #define SSP_DEFAULT_IDX 1 -#define NUM_CPU_FREQ 3 +#define NUM_CPU_FREQ 2 #define NUM_SSP_FREQ 3 diff --git a/src/platform/lunarlake/lib/clk.c b/src/platform/lunarlake/lib/clk.c index ed2936b5efc4..7ad664c94118 100644 --- a/src/platform/lunarlake/lib/clk.c +++ b/src/platform/lunarlake/lib/clk.c @@ -9,9 +9,8 @@ #include static const struct freq_table platform_cpu_freq[] = { - { 38400000, 38400 }, - { 120000000, 120000 }, - { CLK_MAX_CPU_HZ, 400000 }, + { CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 }, + { CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 }, }; STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies); diff --git a/src/platform/meteorlake/include/platform/lib/clk.h b/src/platform/meteorlake/include/platform/lib/clk.h index 2eb1732aad55..fec0a582ab7e 100644 --- a/src/platform/meteorlake/include/platform/lib/clk.h +++ b/src/platform/meteorlake/include/platform/lib/clk.h @@ -14,21 +14,19 @@ #include -#define CLK_MAX_CPU_HZ 400000000 +#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ #define CPU_WOVCRO_FREQ_IDX 0 -#define CPU_LPRO_FREQ_IDX 1 - -#define CPU_HPRO_FREQ_IDX 2 +#define CPU_IPLL_FREQ_IDX 1 #define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX -#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX +#define CPU_DEFAULT_IDX CPU_IPLL_FREQ_IDX #define SSP_DEFAULT_IDX 1 -#define NUM_CPU_FREQ 3 +#define NUM_CPU_FREQ 2 #define NUM_SSP_FREQ 3 diff --git a/src/platform/meteorlake/lib/clk.c b/src/platform/meteorlake/lib/clk.c index 227bc9fd9366..20221b89d790 100644 --- a/src/platform/meteorlake/lib/clk.c +++ b/src/platform/meteorlake/lib/clk.c @@ -9,9 +9,8 @@ #include static const struct freq_table platform_cpu_freq[] = { - { 38400000, 38400 }, - { 120000000, 120000 }, - { CLK_MAX_CPU_HZ, 400000 }, + { CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000 }, + { CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 }, }; STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies);