diff --git a/.github/workflows/installer.yml b/.github/workflows/installer.yml index ed54ff7352a2..655603af0c83 100644 --- a/.github/workflows/installer.yml +++ b/.github/workflows/installer.yml @@ -23,8 +23,7 @@ jobs: fail-fast: false matrix: # just a vector in this case make_env: [ - IPC_VERSION=, # default version - IPC_VERSION=IPC4 UNSIGNED_list= SIGNED_list='tgl tgl-h', + IPC_VERSION= UNSIGNED_list='imx8' SIGNED_list=, # default version ] steps: diff --git a/.github/workflows/pull-request.yml b/.github/workflows/pull-request.yml index 200d380b7259..90ae5e511c92 100644 --- a/.github/workflows/pull-request.yml +++ b/.github/workflows/pull-request.yml @@ -127,7 +127,6 @@ jobs: # to COMMAS. Don't use a single big group so a single failure # does not block all other builds. platform: [imx8ulp, - tgl, rn rmb, mt8186 mt8195, ] diff --git a/Kconfig.sof b/Kconfig.sof index 22b16af9d036..453c5348b8dd 100644 --- a/Kconfig.sof +++ b/Kconfig.sof @@ -11,10 +11,6 @@ config HOST_PTABLE bool default n -config XT_BOOT_LOADER - bool - default n - config XT_HAVE_RESET_VECTOR_ROM bool default n diff --git a/installer/GNUmakefile b/installer/GNUmakefile index 3e854143cb71..3caaab5eb3b5 100644 --- a/installer/GNUmakefile +++ b/installer/GNUmakefile @@ -14,14 +14,11 @@ # List of /lib/firmware/sof/ images and symbolic links currently # released by Intel. -# See rimage/config/*.toml -SIGNED_list ?= tgl tgl-h - # To find aliases, try in a Linux kernel git clone: # # git grep 'sof-.*\.ri' -- sound/soc/ -ALIAS_OTHER_KEY_list += adl adl-s rpl rpl-s +# ALIAS_OTHER_KEY_list += adl adl-s rpl rpl-s # Not supported in the main branch anymore, go to stable-v2.3 # UNSIGNED_list += bdw byt cht @@ -39,11 +36,7 @@ $(info UNSIGNED_list = ${UNSIGNED_list} ) $(info SIGNED_list = ${SIGNED_list} ) $(info ALIAS_list = ${ALIAS_list} ) -target_of_ehl := tgl -target_of_adl := tgl -target_of_adl-s := tgl-h -target_of_rpl := tgl -target_of_rpl-s := tgl-h +target_of_imx := imx8 ifeq (,${TOOLCHAIN}) ifeq (,${XTENSA_TOOLS_ROOT}) diff --git a/installer/tests/staging_sof_ref.txt b/installer/tests/staging_sof_ref.txt index 2cad7d207e4b..0029924ddd40 100644 --- a/installer/tests/staging_sof_ref.txt +++ b/installer/tests/staging_sof_ref.txt @@ -1,23 +1,5 @@ . -├── community -│   ├── sof-adl-s.ri -> sof-tgl-h.ri -│   ├── sof-adl.ri -> sof-tgl.ri -│   ├── sof-rpl-s.ri -> sof-tgl-h.ri -│   ├── sof-rpl.ri -> sof-tgl.ri -│   ├── sof-tgl-h.ri -│   └── sof-tgl.ri -├── intel-signed -├── sof-adl-s.ldc -> sof-tgl-h.ldc -├── sof-adl-s.ri -> intel-signed/sof-adl-s.ri -├── sof-adl.ldc -> sof-tgl.ldc -├── sof-adl.ri -> intel-signed/sof-adl.ri -├── sof-rpl-s.ldc -> sof-tgl-h.ldc -├── sof-rpl-s.ri -> intel-signed/sof-rpl-s.ri -├── sof-rpl.ldc -> sof-tgl.ldc -├── sof-rpl.ri -> intel-signed/sof-rpl.ri -├── sof-tgl-h.ldc -├── sof-tgl-h.ri -> intel-signed/sof-tgl-h.ri -├── sof-tgl.ldc -└── sof-tgl.ri -> intel-signed/sof-tgl.ri +├── sof-imx8.ldc +└── sof-imx8.ri -2 directories, 18 files +0 directories, 2 files diff --git a/scripts/test-repro-build.sh b/scripts/test-repro-build.sh index 3ea0c63c96d5..d06c920c628d 100755 --- a/scripts/test-repro-build.sh +++ b/scripts/test-repro-build.sh @@ -39,7 +39,7 @@ SOF2="$SOF_PARENT"/sof-bind-mount-DO-NOT-DELETE # considerably, replace "sof" with something of the same length: # SOF2="$SOF_PARENT"/sog -PLATFS=(tgl) +PLATFS=(imx8) # diffoscope is great but it has hundreds of dependencies, too long to # install for CI so we don't use it here. This is just an alias diff --git a/scripts/xtensa-build-all.sh b/scripts/xtensa-build-all.sh index 05cb8f13dc98..059cd07fb283 100755 --- a/scripts/xtensa-build-all.sh +++ b/scripts/xtensa-build-all.sh @@ -8,7 +8,6 @@ set -e # Platforms built and tested by default in CI using the `-a` option. # They must have a toolchain available in the latest Docker image. DEFAULT_PLATFORMS=( - tgl tgl-h imx8 imx8x imx8m imx8ulp rn rmb mt8186 mt8195 @@ -199,25 +198,6 @@ do PLATFORM_PRIVATE_KEY='' case $platform in - tgl) - PLATFORM="tgplp" - XTENSA_CORE="cavs2x_LX6HiFi3_2017_8" - HOST="xtensa-cnl-elf" - XTENSA_TOOLS_VERSION="RG-2017.8-linux" - HAVE_ROM='yes' - IPC4_CONFIG_OVERLAY="tigerlake_ipc4" - # default key for TGL - PLATFORM_PRIVATE_KEY="-D${SIGNING_TOOL}_PRIVATE_KEY=$SOF_TOP/keys/otc_private_key_3k.pem" - ;; - tgl-h) - PLATFORM="tgph" - XTENSA_CORE="cavs2x_LX6HiFi3_2017_8" - HOST="xtensa-cnl-elf" - XTENSA_TOOLS_VERSION="RG-2017.8-linux" - HAVE_ROM='yes' - # default key for TGL - PLATFORM_PRIVATE_KEY="-D${SIGNING_TOOL}_PRIVATE_KEY=$SOF_TOP/keys/otc_private_key_3k.pem" - ;; imx8) PLATFORM="imx8" XTENSA_CORE="hifi4_nxp_v3_3_1_2_2017" diff --git a/src/arch/xtensa/CMakeLists.txt b/src/arch/xtensa/CMakeLists.txt index 4a5fe01567c5..dba585186872 100644 --- a/src/arch/xtensa/CMakeLists.txt +++ b/src/arch/xtensa/CMakeLists.txt @@ -20,10 +20,6 @@ elseif(CONFIG_MT8195) set(platform_folder mt8195) endif() -if(CONFIG_CAVS) - set(family_path intel/cavs) -endif() - set(fw_name ${CONFIG_RIMAGE_SIGNING_SCHEMA}) if(CONFIG_XT_BOOT_LOADER) diff --git a/src/arch/xtensa/xtos/crt1-boards-rom.S b/src/arch/xtensa/xtos/crt1-boards-rom.S deleted file mode 100644 index e5391999981c..000000000000 --- a/src/arch/xtensa/xtos/crt1-boards-rom.S +++ /dev/null @@ -1,166 +0,0 @@ -// crt1-boards.S -// -// For most hardware / boards, this code sets up the C calling context -// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start -// which sets up the C library, calls constructors and registers destructors, -// and calls main(). -// -// Control arrives here at _start from the reset vector or from crt0-app.S. - -// Copyright (c) 1998-2017 Cadence Design Systems, Inc. -// -// Permission is hereby granted, free of charge, to any person obtaining -// a copy of this software and associated documentation files (the -// "Software"), to deal in the Software without restriction, including -// without limitation the rights to use, copy, modify, merge, publish, -// distribute, sublicense, and/or sell copies of the Software, and to -// permit persons to whom the Software is furnished to do so, subject to -// the following conditions: -// -// The above copyright notice and this permission notice shall be included -// in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY -// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE -// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -#include - -#include - -// Exports -.global _start - -// Imports -// __clibrary_init from C library (eg. newlib or uclibc) -// exit from C library -// main from user application -// board_init board-specific (uart/mingloss/tinygloss.c) -// xthal_dcache_all_writeback from HAL library -// __stack from linker script (see LSP Ref Manual) -// _bss_table_start from linker script (see LSP Ref Manual) -// _bss_table_end from linker script (see LSP Ref Manual) - -.type main, @function - -// Macros to abstract away ABI differences - -#if __XTENSA_CALL0_ABI__ -# define CALL call0 -# define CALLX callx0 -#else -# define CALL call4 -# define CALLX callx4 -#endif - -/**************************************************************************/ - - .text - .align 4 - .literal_position - -// VM ROM jumps to boot loader in IMR/SRAM -_boot_ldr_entry: - .word IMR_BOOT_LDR_TEXT_ENTRY_BASE - .align 4 - -_start: - // _start is typically NOT at the beginning of the text segment -- - // it is always called from either the reset vector or other code - // that does equivalent initialization (such as crt0-app.S). - // - // Assumptions on entry to _start: - // - low (level-one) and medium priority interrupts are disabled - // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to - // be zeroed, to potentially enable them, before calling main) - // - C calling context not initialized: - // - PS not initialized - // - SP not initialized - // - the following are initialized: - // - LITBASE, cache attributes, WindowBase, WindowStart, - // CPENABLE, FP's FCR and FSR, EXCSAVE[n] - - // Keep a0 zero. It is used to initialize a few things. - // It is also the return address, where zero indicates - // that the frame used by _start is the bottommost frame. - // -#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX - movi a0, 0 // keep this register zero. -#endif - -#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT -#include "reset-unneeded.S" -#endif - -#if CONFIG_XT_BOOT_LOADER - .weak _Level2FromVector - .weak _Level3FromVector - .weak _Level4FromVector - .weak _Level5FromVector - - movi a4, _Level2FromVector - writesr excsave 2 a4 - movi a4, _Level3FromVector - writesr excsave 3 a4 - movi a4, _Level4FromVector - writesr excsave 4 a4 - movi a4, _Level5FromVector - writesr excsave 5 a4 -#endif - - // Assign stack ptr before PS is initialized to avoid any debugger - // side effects and prevent from double exception. - movi sp, __stack - - /* - * Now that sp (a1) is set, we can set PS as per the application - * (user vector mode, enable interrupts, enable window exceptions if applicable). - */ -#if XCHAL_HAVE_EXCEPTIONS - movi a3, PS_UM|PS_WOE_ABI // PS.WOE = 0|1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 - wsr.ps a3 - rsync -#endif - - /* - * Do any initialization that affects the memory map, such as - * setting up TLB entries, that needs to be done before we can - * successfully clear BSS (e.g. if some BSS segments are in - * remapped areas). - * - * NOTE: This hook works where the reset vector does not unpack - * segments (see "ROM packing" in the LSP manual), or where - * unpacking of segments is not affected by memory remapping. - * If ROM unpacking is affected, TLB setup must be done in - * assembler from the reset vector. - * - * The __memmap_init() routine can be a C function, however it - * does not have BSS initialized! In particular, __memmap_init() - * cannot set BSS variables, i.e. uninitialized global variables - * (they'll be wiped out by the following BSS clear), nor can it - * assume they are yet initialized to zero. - * - * The __memmap_init() function is optional. It is marked as a - * weak symbol, so that it gets valued zero if not defined. - */ - .weak __memmap_init - movi a4, __memmap_init - beqz a4, 1f - CALLX a4 -1: - l32r a0, _boot_ldr_entry // load SRAM reset handler address - callx12 a0 // jump to the handler - -dead: nop - j dead - - .data - // Mark argc/argv/envp parameters as weak so that an external - // object file can override them. - .text - - .size _start, . - _start diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 9b3232800f7e..64a86a6d2d64 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -9,7 +9,6 @@ choice config TIGERLAKE bool "Build for Tigerlake" - select XT_BOOT_LOADER select XT_IRQ_MAP select DMA_GW select DW diff --git a/src/platform/intel/cavs/CMakeLists.txt b/src/platform/intel/cavs/CMakeLists.txt index 7a026b75b5e1..09b76c325913 100644 --- a/src/platform/intel/cavs/CMakeLists.txt +++ b/src/platform/intel/cavs/CMakeLists.txt @@ -15,23 +15,6 @@ target_link_libraries(sof_static_libraries INTERFACE lps_vector) add_local_sources(sof lps_wait.c) endif() -if(CONFIG_NO_SECONDARY_CORE_ROM) - add_library(altreset STATIC "") - target_link_libraries(altreset sof_options) - target_compile_options(altreset PRIVATE -mtext-section-literals) - - add_local_sources(altreset alternate_reset_vector.S) - - target_link_libraries(sof_static_libraries INTERFACE altreset) -endif() - add_local_sources(sof platform.c) target_include_directories(sof_options INTERFACE ${PROJECT_SOURCE_DIR}/src/platform/intel/cavs/include) - -add_library(cavs_ext_manifest STATIC "") -add_local_sources(cavs_ext_manifest ext_manifest.c) -sof_append_relative_path_definitions(cavs_ext_manifest) - -target_link_libraries(cavs_ext_manifest sof_options) -target_link_libraries(sof_static_libraries INTERFACE cavs_ext_manifest) diff --git a/src/platform/intel/cavs/alternate_reset_vector.S b/src/platform/intel/cavs/alternate_reset_vector.S deleted file mode 100644 index 434b087db1e2..000000000000 --- a/src/platform/intel/cavs/alternate_reset_vector.S +++ /dev/null @@ -1,309 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - */ - - -#include -#include -#include -#if CONFIG_XT_BOOT_LOADER && !CONFIG_VM_ROM -#include -#include -#endif -#include -#include -#include -#include -#include -#include -#include - -#include "xtos-internal.h" - -.type secondary_core_init, @function -.type shared_vecbase_ptr, @object - -.section .AlternateResetVector.text, "ax" - - /* Alignemt and padding for 4 dwords is in order to meet - * lpsram header requiremetns */ -_LpsramHeader: - j _AltResetVector - .align 4 - /* Magic value. */ - .long 0 - /* Lp-restore vector address. */ - .long 0 - /* Reserved. */ - .long 0 - - .size _LpsramHeader, . - _LpsramHeader - -.align 4 -_AltResetVectorLiterals: - .literal_position - - .size _AltResetVectorLiterals, . - _AltResetVectorLiterals - -.align 4 -.global _AltResetVector - -.align 4 -_AltResetVector: - movi a0, 0 - movi a1, 1 - wsr a1, WINDOWSTART - wsr a0, WINDOWBASE - rsync - - get_prid a5 - movi a6, PLATFORM_PRIMARY_CORE_ID - bne a5, a6, secondary_init //core0 handle restore, core1 always starts from scratch - /* Currently no implementation for core 0: - - shutoff restore should be put either here on in L1SRAM */ - j alt_boot_error_loop - -secondary_init: - /* Block interrupt but not enable WOE */ - movi a3, PS_UM | PS_INTLEVEL(5) - wsr a3, PS - rsync - - movi a2, 0 - call0 _l1_cache_init - movi a0, 0 - -alt_boot_secondary_core_idc_receiver: - get_prid a5 - movi a3, IPC_DSP_BASE(0) - movi a4, IPC_DSP_SIZE - mull a4, a4, a5 - add a3, a3, a4 - - l32i a2, a3, 0 - bbsi a2, 31, alt_boot_validate_idc_msg - -alt_boot_secondary_core_enter_waiti: - - /* Setup int vector to be local */ - movi a2, _LpsramHeader - wsr a2, vecbase - - get_prid a5 - // Get core interrupt reg - // a5 should still contain processor id - movi a3, IRQ_CPU_OFFSET - mull a3, a3, a5 - movi a2, IRQ_BASE - add a3, a2, a3 - - movi a2, 0xffffffff & ~(BIT(IRQ_BIT_LVL2_IDC)) - s32i a2, a3, 0 - movi a2, 0xffffffff - s32i a2, a3, 0x10 - movi a2, 0xffffffff - s32i a2, a3, 0x20 - movi a2, 0xffffffff - s32i a2, a3, 0x30 - memw // at this point use l32i to read - //Unmask Tensilica L2 interrupt - movi a2, IRQ_MASK_EXT_LEVEL2 - - /* Enable L2 level trigger (external) interrupt */ - movi a2, BIT(6) - wsr a2, INTENABLE - - movi a2, 128 - -alt_boot_secondary_wait_for_waiti: - addi a2, a2, -1 - nop - bnez a2, alt_boot_secondary_wait_for_waiti - -alt_boot_secondary_enter_waiti: - isync - extw - waiti 1 - j alt_boot_secondary_core_idc_receiver - -alt_boot_validate_idc_msg: - /* Core wake version: bits 0-8 (9 - bits) - core wake version must be 0x2. */ - l32i a2, a3, 0 - movi a4, 0x1FF - and a2, a2, a4 - bnei a2, 0x2, alt_boot_handle_incorrect_idc - /* ROM Control Version bits 24-28 (5 bits) - rom control version must be 0x1. */ - l32i a2, a3, 0 - srli a2, a2, 24 - movi a4, 0x1F - and a2, a2, a4 - bnei a2, 0x1, alt_boot_handle_incorrect_idc - - .macro init_vector level - .if GREATERTHAN(XCHAL_NUM_INTLEVELS+1,\level) - .if XCHAL_DEBUGLEVEL-\level - .weak _Level&level&FromVector - movi a4, _Level&level&FromVector - writesr excsave \level a4 - .if GREATERTHAN(\level,XCHAL_EXCM_LEVEL) - movi a5, _Pri_&level&_HandlerAddress - s32i a4, a5, 0 - /* If user provides their own handler, that handler might - * not provide its own _Pri__HandlerAddress variable for - * linking handlers. In that case, the reference below - * would pull in the XTOS handler anyway, causing a conflict. - * To avoid that, provide a weak version of it here: - */ - .pushsection .data, "aw" - .global _Pri_&level&_HandlerAddress - .weak _Pri_&level&_HandlerAddress - .align 4 - _Pri_&level&_HandlerAddress: .space 4 - .popsection - .endif - .endif - .endif - .endm - - -lp_reset_setup_vecbase: - movi a2, shared_vecbase_ptr - l32i a2, a2, 0 - beqz a2, alt_boot_error_loop - /* Apply alternate vector base given from ldscripts. */ - wsr a2, vecbase - - init_vector 2 - init_vector 3 - init_vector 4 - init_vector 5 - -alt_boot_secondary_core_wakeup: - movi a2, 0 - wsr a2, INTENABLE - rsync - - // Compute address to jump - l32i a2, a3, 4 - slli a2, a2, 2 - // Clear busy bit - l32i a4, a3, 0 - s32i a4, a3, 0 - memw - - jx a2 -alt_boot_handle_incorrect_idc: - // Clear BUSY - l32i a2, a3, 0 - s32i a2, a3, 0 - memw - // HW limitation read the register - l32i a4, a3, 0 - j alt_boot_secondary_core_idc_receiver - -alt_boot_error_loop: - // TODO: consider some kind of status reporting here. - j alt_boot_error_loop - - .size _AltResetVector, . - _AltResetVector - -.section .AlternateResetL2IntVector.text, "ax" - -/* Note: at this moment it is essential that this is linked on - * _LpsramHeader + 0x180 */ -.align 4 -.global _AltResetL2IntHandler -_AltResetL2IntHandler: - xsr a2, excsave2 - xor a2, a2, a2 - wsr a2, intenable - xsr a2, excsave2 - rfi 2 - .size _AltResetL2IntHandler, . - _AltResetL2IntHandler - -.section .LpsramCode.text, "ax" - -.literal_position - -.global _l1_cache_init -.align 4 - -_l1_cache_init: - mov a9, a2 - movi a3, CxL1CCFG - bnez a9, l1_cache_enable_one_way - -l1_cache_way_enable_all: - movi a2, L1_CACHE_ALL_WAY_ENABLED_MASK - movi a4, L1_CACHE_ALL_WAY_ACTIVE_MASK - j l1_cache_enable_write - -l1_cache_enable_one_way: - movi a2, L1_CACHE_ONE_WAY_ENABLED_MASK - movi a4, L1_CACHE_ONE_WAY_ACTIVE_MASK - -l1_cache_enable_write: - s32i a2, a3, 0 - -l1_cache_wait_for_way_enable_loop: - l32i a2, a3, 0 - and a2, a2, a4 - bne a2, a4, l1_cache_wait_for_way_enable_loop - -#if XCHAL_HAVE_PREFETCH -l1_cache_pref_ebb_enble: - movi a3, CxL1PCFG - movi a2, L1_CACHE_PREFETCHER_ENABLED - movi a4, L1_CACHE_PREFETCHER_ACTIVE - s32i a2, a3, 0 - -l1_cache_wait_for_prefetcher: - l32i a2, a3, 0 - and a2, a2, a4 - bne a4, a2, l1_cache_wait_for_prefetcher -#endif - -l1_cache_inv_unlock: -#if ! XCHAL_HAVE_ICACHE_DYN_WAYS - icache_reset a2, a3 -#endif - -#if ! XCHAL_HAVE_DCACHE_DYN_WAYS - dcache_reset a2, a3 -#endif - -l1_cache_set_prefctl: -#if XCHAL_HAVE_PREFETCH - /* Enable cache prefetch if present. */ - movi a2, L1_CACHE_PREFCTL_VALUE - wsr a2, PREFCTL -#endif - -l1_cache_setup_memprotection: - movi a2, _memmap_cacheattr_reset - /* NOTE: CLOBBERS a2 - a8 !!! */ - cacheattr_set -#if XCHAL_USE_MEMCTL - bnez a9, l1_cache_init_program_memctl_one_way - -l1_cache_init_program_memctl_all_ways: - movi a3, ((~MEMCTL_SNOOP_EN)) - j l1_cache_init_program_memctl - -l1_cache_init_program_memctl_one_way: - movi a3, ((1 << 8) | (1 << 13) | (1 << 18) | MEMCTL_L0IBUF_EN | 1 << 23) - -l1_cache_init_program_memctl: - wsr a3, MEMCTL - rsync - /* Enable zero-overhead loop instr buffer, and snoop responses, if configured. */ - movi a3, (MEMCTL_SNOOP_EN | MEMCTL_L0IBUF_EN) - rsr a2, MEMCTL - or a2, a2, a3 - wsr a2, MEMCTL - rsync -#endif - ret - - .size _l1_cache_init, . - _l1_cache_init diff --git a/src/platform/intel/cavs/boot_entry.S b/src/platform/intel/cavs/boot_entry.S deleted file mode 100644 index f92cd86f1a44..000000000000 --- a/src/platform/intel/cavs/boot_entry.S +++ /dev/null @@ -1,230 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -/* - * Entry point from ROM - assumes :- - * - * 1) C runtime environment is initialised by ROM. - * 2) Stack is in first HPSRAM bank. - */ - -#include -#include -#include -#include - -#include -#include -#include "xtos-internal.h" - - .type boot_primary_core, @function - - .begin literal_prefix .boot_entry - .section .boot_entry.text, "ax" - - .align 4 - .global boot_entry - -boot_entry: - entry a1, 48 - j boot_init - - .align 4 - .literal_position -#if defined(PLATFORM_RESET_MHE_AT_BOOT) -l2_mecs: - .word SHIM_L2_MECS -#endif - -#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT) -l2_cache_pref: - .word SHIM_L2_PREF_CFG -#endif - -sof_stack_base: - .word __stack - -#if CONFIG_MEM_WND -wnd0_base: - .word DMWBA(0) - -wnd0_size: - .word DMWLO(0) - -wnd0_base_val: - .word HP_SRAM_WIN0_BASE | DMWBA_READONLY | DMWBA_ENABLE - -wnd0_size_val: - .word HP_SRAM_WIN0_SIZE | 0x7 - -wnd0_status_address: - .word HP_SRAM_WIN0_BASE - -wnd0_error_address: - .word HP_SRAM_WIN0_BASE | 0x4 - -fw_loaded_status_value: - .word 0x00000005 - -fw_no_errors_value: - .word 0x00000000 -#endif - -#if defined(PLATFORM_MEM_INIT_AT_BOOT) -shim_ldoctl_address: - .word SHIM_BASE + SHIM_LDOCTL - -ldoctl_hpsram_ldo_on: - .word SHIM_LDOCTL_HPSRAM_LDO_ON - -ldoctl_hpsram_ldo_bypass: - .word SHIM_LDOCTL_HPSRAM_LDO_BYPASS - -hspgctl0_address: - .word HSPGCTL0 - -hsrmctl0_address: - .word HSRMCTL0 - -hspgctl1_address: - .word HSPGCTL1 - -hsrmctl1_address: - .word HSRMCTL1 - -hspgists0_address: - .word HSPGISTS0 - -hspgists1_address: - .word HSPGISTS1 -#endif - -boot_init: - .align 4 -#if defined(PLATFORM_DISABLE_L2CACHE_AT_BOOT) - l32r a3, l2_cache_pref - movi a5, 0 - s32i a5, a3, 0 - memw -#endif - -#if defined(PLATFORM_RESET_MHE_AT_BOOT) - /* reset memory hole */ - l32r a3, l2_mecs - movi a5, 0 - s32i a5, a3, 0 -#endif - -#if defined(PLATFORM_MEM_INIT_AT_BOOT) - /* turn on memory _before_ stack reprogramming */ - - l32r a3, ldoctl_hpsram_ldo_on - l32r a5, shim_ldoctl_address - s32i a3, a5, 0 - memw - - /* delay for 256 iterations before touching pwr regs */ - movi a2, 256 -1: addi.n a2, a2, -1 - bnez a2, 1b - - movi a3, 0 - l32r a5, hspgctl0_address - s32i a3, a5, 0 - memw - - l32r a5, hsrmctl0_address - s32i a3, a5, 0 - memw - - l32r a5, hspgctl1_address - s32i a3, a5, 0 - memw - - l32r a5, hsrmctl1_address - s32i a3, a5, 0 - memw - - /* wait for status of first bank group */ - l32r a5, hspgists0_address -2: - l32i a3, a5, 0 - bnez a3, 2b - - /* wait for status of second bank group */ - l32r a5, hspgists1_address -3: - l32i a3, a5, 0 - bnez a3, 3b - - /* delay for 256 iterations before touching pwr regs */ - movi a2, 256 -4: addi.n a2, a2, -1 - bnez a2, 4b - - l32r a3, ldoctl_hpsram_ldo_bypass - l32r a5, shim_ldoctl_address - s32i a3, a5, 0 - memw -#endif - - /* reprogram stack to the area defined by main FW */ - l32r a3, sof_stack_base - mov sp, a3 - -#if CONFIG_MEM_WND - /* set status register to 0x00000005 in wnd0 */ - l32r a3, fw_loaded_status_value - l32r a5, wnd0_status_address - s32i a3, a5, 0 - - /* set error register to 0x00 in wnd0 */ - l32r a3, fw_no_errors_value - l32r a5, wnd0_error_address - s32i a3, a5, 0 - - /* realloc memory window0 to - continue reporting boot progress */ - l32r a3, wnd0_size - l32r a5, wnd0_size_val - s32i a5, a3, 0 - memw - l32r a3, wnd0_base - l32r a5, wnd0_base_val - s32i a5, a3, 0 - memw -#endif - -#if (XCHAL_DCACHE_IS_COHERENT || XCHAL_LOOP_BUFFER_SIZE) && \ - XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0 - /* Enable zero-overhead loop instr buffer, - and snoop responses, if configured. */ - movi a3, (MEMCTL_SNOOP_EN | MEMCTL_L0IBUF_EN) - rsr a2, MEMCTL - or a2, a2, a3 - wsr a2, MEMCTL -#endif - - /* determine core we are running on */ - get_prid a2 - movi a3, PLATFORM_PRIMARY_CORE_ID - beq a2, a3, 1f - - /* no core should get here */ - j dead - -1: - /* we are primary core so boot it */ - call8 boot_primary_core - -dead: - /* should never get here - we are dead */ - j dead - - .size boot_entry, . - boot_entry - - .end literal_prefix diff --git a/src/platform/intel/cavs/boot_loader.c b/src/platform/intel/cavs/boot_loader.c deleted file mode 100644 index 00828b5eaac4..000000000000 --- a/src/platform/intel/cavs/boot_loader.c +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2016 Intel Corporation. All rights reserved. -// -// Author: Liam Girdwood - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define MANIFEST_BASE IMR_BOOT_LDR_MANIFEST_BASE -#define MANIFEST_SEGMENT_COUNT 3 - -/* generic string compare cloned into the bootloader to - * compact code and make it more readable - */ -int strcmp(const char *s1, const char *s2) -{ - while (*s1 != 0 && *s2 != 0) { - if (*s1 < *s2) - return -1; - if (*s1 > *s2) - return 1; - s1++; - s2++; - } - - /* did both string end */ - if (*s1 != 0) - return 1; - if (*s2 != 0) - return -1; - - /* match */ - return 0; -} - -/* memcopy used by boot loader */ -static inline void bmemcpy(void *dest, void *src, size_t bytes) -{ - uint32_t *d = dest; - uint32_t *s = src; - int i; - - for (i = 0; i < (bytes >> 2); i++) - d[i] = s[i]; - - dcache_writeback_region(dest, bytes); -} - -/* bzero used by bootloader */ -static inline void bbzero(void *dest, size_t bytes) -{ - uint32_t *d = dest; - int i; - - for (i = 0; i < (bytes >> 2); i++) - d[i] = 0; - - dcache_writeback_region(dest, bytes); -} - -static void parse_module(struct sof_man_fw_header *hdr, - struct sof_man_module *mod) -{ - int i; - uint32_t bias; - - /* each module has 3 segments */ - for (i = 0; i < MANIFEST_SEGMENT_COUNT; i++) { - trace_point(TRACE_BOOT_LDR_PARSE_SEGMENT + i); - switch (mod->segment[i].flags.r.type) { - case SOF_MAN_SEGMENT_TEXT: - case SOF_MAN_SEGMENT_DATA: - bias = (mod->segment[i].file_offset - - SOF_MAN_ELF_TEXT_OFFSET); - - /* copy from IMR to SRAM */ - bmemcpy((void *)mod->segment[i].v_base_addr, - (void *)((int)hdr + bias), - mod->segment[i].flags.r.length * - HOST_PAGE_SIZE); - break; - case SOF_MAN_SEGMENT_BSS: - /* copy from IMR to SRAM */ - bbzero((void *)mod->segment[i].v_base_addr, - mod->segment[i].flags.r.length * - HOST_PAGE_SIZE); - break; - default: - /* ignore */ - break; - } - } -} - -/* parse FW manifest and copy modules */ -static void parse_manifest(void) -{ - struct sof_man_fw_desc *desc = - (struct sof_man_fw_desc *)MANIFEST_BASE; - struct sof_man_fw_header *hdr = &desc->header; - struct sof_man_module *mod; - int i; - - /* copy module to SRAM - skip bootloader module */ - for (i = 1; i < hdr->num_module_entries; i++) { - trace_point(TRACE_BOOT_LDR_PARSE_MODULE + i); - mod = (struct sof_man_module *)((char *)desc + - SOF_MAN_MODULE_OFFSET(i)); - parse_module(hdr, mod); - } -} - -#if PLATFORM_MEM_INIT_AT_BOOT - -static uint32_t get_fw_size_in_use(void) -{ - struct sof_man_fw_desc *desc = - (struct sof_man_fw_desc *)MANIFEST_BASE; - struct sof_man_fw_header *hdr = &desc->header; - struct sof_man_module *mod; - uint32_t fw_size_in_use = 0xffffffff; - int i; - - /* Calculate fw size passed in BASEFW module in MANIFEST */ - for (i = 1; i < hdr->num_module_entries; i++) { - trace_point(TRACE_BOOT_LDR_PARSE_MODULE + i); - mod = (struct sof_man_module *)((char *)desc + - SOF_MAN_MODULE_OFFSET(i)); - if (strcmp((char *)mod->name, "BASEFW")) - continue; - for (i = 0; i < MANIFEST_SEGMENT_COUNT; i++) { - if (mod->segment[i].flags.r.type - == SOF_MAN_SEGMENT_BSS) { - fw_size_in_use = mod->segment[i].v_base_addr - - HP_SRAM_BASE - + (mod->segment[i].flags.r.length - * HOST_PAGE_SIZE); - } - } - } - - return fw_size_in_use; -} - -static uint32_t hp_sram_power_memory(uint32_t memory_size, bool enable) -{ - uint32_t start_bank; - uint32_t end_bank; - uint32_t ebb_in_use; - - /* calculate total number of used SRAM banks (EBB) - * to power up only necessary banks - */ - ebb_in_use = SOF_DIV_ROUND_UP(memory_size, SRAM_BANK_SIZE); - - start_bank = enable ? 0 : ebb_in_use; - end_bank = (enable ? ebb_in_use : PLATFORM_HPSRAM_EBB_COUNT) - 1; - - cavs_pm_memory_hp_sram_banks_power_gate(start_bank, end_bank, enable); - - return 0; -} - -static int32_t hp_sram_power_off_unused_banks(uint32_t memory_size) -{ - /* keep enabled only memory banks used by FW */ - return hp_sram_power_memory(memory_size, false); -} - -static int32_t hp_sram_init(void) -{ - return hp_sram_power_memory(HP_SRAM_SIZE, true); -} - -#endif - -/* boot primary core */ -void boot_primary_core(void) -{ -#if PLATFORM_MEM_INIT_AT_BOOT - int32_t result; -#endif - - trace_point(TRACE_BOOT_LDR_ENTRY); - -#if PLATFORM_MEM_INIT_AT_BOOT - /* init the HPSRAM */ - trace_point(TRACE_BOOT_LDR_HPSRAM); - result = hp_sram_init(); - if (result < 0) { - platform_panic(SOF_IPC_PANIC_MEM); - return; - } -#endif - -#if CONFIG_LP_SRAM - /* init the LPSRAM */ - trace_point(TRACE_BOOT_LDR_LPSRAM); - - cavs_pm_memory_lp_sram_banks_power_gate(0, - PLATFORM_LPSRAM_EBB_COUNT - 1, - true); -#endif - -#if CONFIG_L1_DRAM - /* Power ON L1 DRAM memory */ - trace_point(TRACE_BOOT_LDR_L1DRAM); - cavs_pm_memory_l1_dram_banks_power_gate(CONFIG_L1_DRAM_MEMORY_BANKS - 1, - 0, true); -#endif - - /* parse manifest and copy modules */ - trace_point(TRACE_BOOT_LDR_MANIFEST); - parse_manifest(); - -#if PLATFORM_MEM_INIT_AT_BOOT - hp_sram_power_off_unused_banks(get_fw_size_in_use()); -#endif - - /* now call SOF entry */ - trace_point(TRACE_BOOT_LDR_JUMP); - _ResetVector(); -} diff --git a/src/platform/intel/cavs/ext_manifest.c b/src/platform/intel/cavs/ext_manifest.c deleted file mode 100644 index 50309a734770..000000000000 --- a/src/platform/intel/cavs/ext_manifest.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2020 Intel Corporation. All rights reserved. -// -// Author: Adrian Bonislawski -// - -#include -#include -#include -#include - -/* Describes elements counter from ext_man_cavs_config dictionary */ -#define CAVS_CONFIG_ELEM_CNT (EXT_MAN_CAVS_CONFIG_LAST_ELEM - 1) - -const struct ext_man_cavs_config_data ext_man_cavs_config - __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") = { - .hdr.type = EXT_MAN_ELEM_PLATFORM_CONFIG_DATA, - .hdr.elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_cavs_config_data) + - sizeof(struct config_elem) * CAVS_CONFIG_ELEM_CNT, - EXT_MAN_ALIGN), - .elems = { - {EXT_MAN_CAVS_CONFIG_LPRO, IS_ENABLED(CONFIG_CAVS_LPRO_ONLY)}, - {EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE, SRAM_OUTBOX_SIZE}, - {EXT_MAN_CAVS_CONFIG_INBOX_SIZE, SRAM_INBOX_SIZE}, - }, -}; diff --git a/src/platform/intel/cavs/lps_pic_restore_vector.S b/src/platform/intel/cavs/lps_pic_restore_vector.S deleted file mode 100644 index 42da750c710b..000000000000 --- a/src/platform/intel/cavs/lps_pic_restore_vector.S +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Marcin Maka - */ - -#include -#include -#include -#include - -#define MEMCTL_INIT_BIT 23 -#define MEMCTL_INIT_VAL (MEMCTL_L0IBUF_EN | 1 << MEMCTL_INIT_BIT) -#define SW_INT_NUM 7 -#define SW_INT_MASK (1<