From 4a9a99aeb24ac7fbcf3cf80973ac8f119a16c6e5 Mon Sep 17 00:00:00 2001 From: Iuliana Prodan Date: Tue, 22 Nov 2022 11:45:03 +0200 Subject: [PATCH] imx: clear general purpose pending interrupt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clear general purpose pending interrupt before enabling interrupts between host and DSP. The GIPn bit, from MU Status Register is cleared by writing it as “1” in order to de-assert the interrupt request source at the interrupt controller. This fixes a fw loading failure after a soft reboot caused by GIP bit that was 1. The problem was the MU which triggered endless interrupts causing timeout on Kernel side, which was waiting for FW_READY message. Signed-off-by: Iuliana Prodan --- src/drivers/imx/ipc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/drivers/imx/ipc.c b/src/drivers/imx/ipc.c index 2c016bcf32c0..8a99da0cf588 100644 --- a/src/drivers/imx/ipc.c +++ b/src/drivers/imx/ipc.c @@ -194,6 +194,11 @@ int platform_ipc_init(struct ipc *ipc) interrupt_register(PLATFORM_IPC_INTERRUPT, irq_handler, ipc); interrupt_enable(PLATFORM_IPC_INTERRUPT, ipc); + /* Clear GP pending interrupt #0 and #1 */ + imx_mu_xsr_rmw(IMX_MU_VERSION, IMX_MU_GSR, + IMX_MU_xSR_GIPn(IMX_MU_VERSION, 0) | + IMX_MU_xSR_GIPn(IMX_MU_VERSION, 1), 0); + /* enable GP #0 for Host -> DSP message notification * enable GP #1 for DSP -> Host message notification */