diff --git a/src/platform/Kconfig b/src/platform/Kconfig index ce972d1d9fc8..c558d371806e 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -340,6 +340,7 @@ config CAVS default n select INTEL select INTEL_MN + select SOF_ZEPHYR_NO_SOF_CLOCK config CAVS_VERSION_2_5 depends on CAVS diff --git a/src/platform/intel/cavs/include/cavs/lib/clk.h b/src/platform/intel/cavs/include/cavs/lib/clk.h deleted file mode 100644 index eec51ac3963e..000000000000 --- a/src/platform/intel/cavs/include/cavs/lib/clk.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -/** - * \file cavs/lib/clk.h - * \brief Clk parameters for run-time clock data, common for cAVS platforms. - */ - -#ifdef __PLATFORM_LIB_CLK_H__ - -#ifndef __CAVS_LIB_CLK_H__ -#define __CAVS_LIB_CLK_H__ - -#include -#include -#include -#include -#include - -struct sof; - -/** \brief Core(s) settings, up to CONFIG_CORE_COUNT */ -#define CLK_CPU(x) (x) - -/** \brief SSP clock r-t settings are after the core(s) settings */ -#define CLK_SSP CONFIG_CORE_COUNT - -/* SSP clock run-time data is the last one, so total number is ssp idx +1 */ - -/** \brief Total number of clocks */ -#define NUM_CLOCKS (CLK_SSP + 1) - -extern const struct freq_table *cpu_freq; -extern const uint32_t cpu_freq_enc[]; -extern const uint32_t cpu_freq_status_mask[]; - -void platform_clock_init(struct sof *sof); - -void platform_clock_on_waiti(void); -void platform_clock_on_wakeup(void); - -#endif /* __CAVS_LIB_CLK_H__ */ - -#else - -#error "This file shouldn't be included from outside of platform/lib/clk.h" - -#endif /* __PLATFORM_LIB_CLK_H__ */ diff --git a/src/platform/intel/cavs/platform.c b/src/platform/intel/cavs/platform.c index fde0f22f0a22..a871f612f3d3 100644 --- a/src/platform/intel/cavs/platform.c +++ b/src/platform/intel/cavs/platform.c @@ -116,14 +116,11 @@ int platform_init(struct sof *sof) { int ret; - trace_point(TRACE_BOOT_PLATFORM_CLOCK); - platform_clock_init(sof); - trace_point(TRACE_BOOT_PLATFORM_SCHED); scheduler_init_edf(); /* init low latency timer domain and scheduler */ - sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK); + sof->platform_timer_domain = timer_domain_init(sof->platform_timer, 0); scheduler_init_ll(sof->platform_timer_domain); /* init the system agent */ diff --git a/src/platform/tigerlake/include/platform/lib/clk.h b/src/platform/tigerlake/include/platform/lib/clk.h deleted file mode 100644 index ff44f00d544d..000000000000 --- a/src/platform/tigerlake/include/platform/lib/clk.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2017 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -#ifdef __SOF_LIB_CLK_H__ - -#ifndef __PLATFORM_LIB_CLK_H__ -#define __PLATFORM_LIB_CLK_H__ - -#include - -#define CLK_MAX_CPU_HZ 400000000 - -#define CPU_WOVCRO_FREQ_IDX 0 - -#define CPU_LPRO_FREQ_IDX 1 - -#define CPU_HPRO_FREQ_IDX 2 - -#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX - -#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX - -#define SSP_DEFAULT_IDX 1 - -#define NUM_CPU_FREQ 3 - -#define NUM_SSP_FREQ 3 - -#endif /* __PLATFORM_LIB_CLK_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/clk.h" - -#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/tigerlake/include/platform/platform.h b/src/platform/tigerlake/include/platform/platform.h index 74e0cd187aab..46bd196ebf44 100644 --- a/src/platform/tigerlake/include/platform/platform.h +++ b/src/platform/tigerlake/include/platform/platform.h @@ -19,18 +19,11 @@ #include #include +#include + struct ll_schedule_domain; struct timer; -/*! \def PLATFORM_DEFAULT_CLOCK - * \brief clock source for audio pipeline - * - * There are two types of clock: cpu clock which is a internal clock in - * xtensa core, and ssp clock which is provided by external HW IP. - * The choice depends on HW features on different platform - */ -#define PLATFORM_DEFAULT_CLOCK CLK_SSP - /* Host page size */ #define HOST_PAGE_SIZE 4096 diff --git a/src/platform/tigerlake/lib/clk.c b/src/platform/tigerlake/lib/clk.c deleted file mode 100644 index 581e9ba3eb40..000000000000 --- a/src/platform/tigerlake/lib/clk.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2019 Intel Corporation. All rights reserved. -// -// Author: Tomasz Lauda -// Janusz Jankowski - -#include -#include -#include - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request WOVCRO Clock */ -#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 -#define SHIM_CLKCTL_WOVCROSC BIT(3) - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV2 0 -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 -#define SHIM_CLKCTL_HMCS_DIV4 BIT(0) - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief WOVCRO Clock Status */ -#define SHIM_CLKSTS_WOV_CRO BIT(4) - -/** \brief XTAL Oscillator Clock Status */ -#define SHIM_CLKSTS_XOSCCS BIT(30) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -static const struct freq_table platform_cpu_freq[] = { - { 38400000, 38400 }, - { 120000000, 120000 }, - { CLK_MAX_CPU_HZ, 400000 }, -}; - -const uint32_t cpu_freq_enc[] = { - SHIM_CLKCTL_WOVCROSC | SHIM_CLKCTL_WOV_CRO_REQUEST | - SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, - SHIM_CLKCTL_RLROSCC | SHIM_CLKCTL_OCS_LP_RING | - SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, - SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_OCS_HP_RING | - SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, -}; - -const uint32_t cpu_freq_status_mask[] = { - SHIM_CLKSTS_WOV_CRO, - SHIM_CLKSTS_LROSCCS, - SHIM_CLKSTS_HROSCCS -}; - -STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq), - invalid_number_of_cpu_frequencies); - -const struct freq_table *cpu_freq = platform_cpu_freq; - -/* IMPORTANT: array should be filled in increasing order - * (regarding to .freq field) - */ -static const struct freq_table platform_ssp_freq[] = { - { 24576000, 24576 }, - { 38400000, 38400 }, - { 96000000, 96000 }, -}; - -static const uint32_t platform_ssp_freq_sources[] = { - SSP_CLOCK_AUDIO_CARDINAL, - SSP_CLOCK_XTAL_OSCILLATOR, - SSP_CLOCK_PLL_FIXED, -}; - -STATIC_ASSERT(NUM_SSP_FREQ == ARRAY_SIZE(platform_ssp_freq), - invalid_number_of_ssp_frequencies); - -const struct freq_table *ssp_freq = platform_ssp_freq; -const uint32_t *ssp_freq_sources = platform_ssp_freq_sources; diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 1a5adce8c560..2575067bb5aa 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -222,8 +222,6 @@ if (CONFIG_SOC_SERIES_INTEL_CAVS_V25) # Platform sources zephyr_library_sources( ${SOF_PLATFORM_PATH}/intel/cavs/platform.c - ${SOF_PLATFORM_PATH}/tigerlake/lib/clk.c - lib/clk.c lib/dma.c )