TTNNLayout does not model DRAM, height and width sharding correctly

[odjuricicTT]

When we create a TTNNLayout memref we split the tensor onto the GridAttr that is provided. The current logic models what happens when the tensor is block sharded which might not be correct in all cases. Support for L1 interleaved is being added #1607. Further investigation is needed for the rest of tensor memory layout options.

[mtopalovicTT]

@odjuricicTT I just want to check if I understand how shard size should be calculated in case of sharding.
lets imagine tensor of <1024x2048> and grid size of <8x8>

1. Width sharding: we divide 2048 / (8 * 8) which yields shard size <1024x32>
2. Height sharding: we divide 1024 / (8 * 8) which yields shard size <16x2048>

Is above correct for both L1 and DRAM?

[odjuricicTT]

@mtopalovicTT Yes that is correct for L1. DRAM sharding does not exist in that sense. DRAM cores are totally separate from tensix cores and are not part of the "grid" that we model with GridAttr. There are 12 dram cores in total.

There are references to "DRAM sharded" tensors in metal / ttnn, but this is something different used by only one specific op.

[mtopalovicTT]

@odjuricicTT I see. So let me try to capture everything:

• For L1 interleaved we have logic which models memory usage correctly
• Same goes for L1 Block sharded
• For DRAM we are calculating shard shape but it's not needed. Same applies for interleaved DRAM right?

if above is correct then we need to change memref to some new attribute lets say shard_shape and we would omit shard_shape in case of DRAM. Any thoughts?

[odjuricicTT]

Yes, that is correct.

I think that we currently use memref shape as the shard shape. This is correct for sharded tensors and L1 interleaved as well.

For DRAM interleaved, we just default to block sharded logic and get a memref that does not make sense. One option is that for DRAM we set GridAttr to some None value and have the memref shape be the same as the tensor shape.