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should there be hardware design files here? #1

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laf0rge opened this issue Feb 23, 2023 · 2 comments
Open

should there be hardware design files here? #1

laf0rge opened this issue Feb 23, 2023 · 2 comments

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@laf0rge
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laf0rge commented Feb 23, 2023

It looks like there's only the license file and the readme file in the repository, but not the actual schematics/layout design files for the hardware. Does it mean the project didn't get over the "idea phase", or does it mean some local commits that should have been pushed have not made it into this repo?

@whitequark
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Oh hi @laf0rge! Do you have a use case in mind? (I haven't directly worked on GlasgISA beyond participating in a discussion four years ago, but I'm still interested in the concept.)

@laf0rge
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laf0rge commented Feb 23, 2023

Hi @whitequark!

In recent months I've just been on and off thinking about some kind of hardware interface to act as a ISA bus master (like a classic x86 CPU) to talk to ancient ISA bus hardware (ISDN, Arcnet, HDLC, whatever cards).

Hence I've had a look at a variety of related projects and did some brainstorming about different possible approaches.

I'm not aiming for any kind of transparent interface into a modern PC. It's more for enabling VMs (qemu) to talk to real ISA hardware.

One aspect is speaking the ISA bus protocol. People have been emulating cards even with ISA DMA (see polpo/picogus). Or the approach taken by Manawyrm/ISASTM. Both doing it in software with PIO / bitbanging. As ISA and IDE are related, one can posisibly also look at jride/netpi-ide as well as pata-gpio for raspi. Doing that in an FPGA is of course far superior for that aspect of a project (see netpi-ide as the only related OSHW FPGA project I found). However, I'm personally just a software + electronics and not a FPGA person.

The other aspect is then of coruse how to get a relatively low-latency interface from that ISA bus master into the host PC and the VMs. USB isn't really suitable as we're talking about tons of PIO/MMIO reads/writes, and not bulk data transfer. @Manawyrm had suggested to look at the CH368L as a PCIe to intel-style parallel bus adapter.

So really, nothing realted to the Glasgow project here; I was just looking for all FOSS/OSHW projects doing something with ISA.

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