From 584625f09fcd744eacbc25111f9ddb54e8207c4f Mon Sep 17 00:00:00 2001 From: Yang Hau Date: Mon, 30 Dec 2024 02:27:19 +0100 Subject: [PATCH] wip --- src/decode.c | 173 +++++------ src/decode.h | 48 +-- src/encoding.h | 703 ++++++++++++++++++++++---------------------- src/riscv_private.h | 8 +- src/rv32_vector.c | 117 ++++---- tests/rvsim.c | 1 + 6 files changed, 540 insertions(+), 510 deletions(-) diff --git a/src/decode.c b/src/decode.c index 1ddd3bf4..1c76b694 100644 --- a/src/decode.c +++ b/src/decode.c @@ -1982,7 +1982,8 @@ static inline bool op_cfsw(rv_insn_t *ir, const uint32_t insn) #define op_cflwsp OP_UNIMP #endif /* RV32_HAS(EXT_C) && RV32_HAS(EXT_F) */ -static inline bool op_ivv(rv_insn_t *ir, const uint32_t insn) { +static inline bool op_ivv(rv_insn_t *ir, const uint32_t insn) +{ #define MASK 0xfc00707f #define MATCH_VADD_VI 0x3057 #define MATCH_VAND_VI 0x24003057 @@ -2011,74 +2012,74 @@ static inline bool op_ivv(rv_insn_t *ir, const uint32_t insn) { ir->rs2 = decode_rs2(insn); ir->vm = decode_rvv_vm(insn); switch (insn & MASK) { - case MATCH_VADD_VI: + case MATCH_VADD_VI: ir->opcode = rv_insn_vadd_vi; - break; - case MATCH_VAND_VI: + break; + case MATCH_VAND_VI: ir->opcode = rv_insn_vand_vi; - break; - case MATCH_VMADC_VI: + break; + case MATCH_VMADC_VI: ir->opcode = rv_insn_vmadc_vi; - break; - case MATCH_VMSEQ_VI: + break; + case MATCH_VMSEQ_VI: ir->opcode = rv_insn_vmseq_vi; - break; - case MATCH_VMSGT_VI: + break; + case MATCH_VMSGT_VI: ir->opcode = rv_insn_vmsgt_vi; - break; - case MATCH_VMSGTU_VI: + break; + case MATCH_VMSGTU_VI: ir->opcode = rv_insn_vmsgtu_vi; - break; - case MATCH_VMSLE_VI: + break; + case MATCH_VMSLE_VI: ir->opcode = rv_insn_vmsle_vi; - break; - case MATCH_VMSLEU_VI: + break; + case MATCH_VMSLEU_VI: ir->opcode = rv_insn_vmsleu_vi; - break; - case MATCH_VMSNE_VI: + break; + case MATCH_VMSNE_VI: ir->opcode = rv_insn_vmsne_vi; - break; - case MATCH_VOR_VI: + break; + case MATCH_VOR_VI: ir->opcode = rv_insn_vor_vi; - break; - case MATCH_VRGATHER_VI: + break; + case MATCH_VRGATHER_VI: ir->opcode = rv_insn_vrgather_vi; - break; - case MATCH_VRSUB_VI: + break; + case MATCH_VRSUB_VI: ir->opcode = rv_insn_vrsub_vi; - break; - case MATCH_VSADD_VI: + break; + case MATCH_VSADD_VI: ir->opcode = rv_insn_vsadd_vi; - break; - case MATCH_VSADDU_VI: + break; + case MATCH_VSADDU_VI: ir->opcode = rv_insn_vsaddu_vi; - break; - case MATCH_VSLIDEDOWN_VI: + break; + case MATCH_VSLIDEDOWN_VI: ir->opcode = rv_insn_vslidedown_vi; - break; - case MATCH_VSLIDEUP_VI: + break; + case MATCH_VSLIDEUP_VI: ir->opcode = rv_insn_vslideup_vi; - break; - case MATCH_VSLL_VI: + break; + case MATCH_VSLL_VI: ir->opcode = rv_insn_vsll_vi; - break; - case MATCH_VSRA_VI: + break; + case MATCH_VSRA_VI: ir->opcode = rv_insn_vsra_vi; - break; - case MATCH_VSRL_VI: + break; + case MATCH_VSRL_VI: ir->opcode = rv_insn_vsrl_vi; - break; - case MATCH_VSSRA_VI: + break; + case MATCH_VSSRA_VI: ir->opcode = rv_insn_vssra_vi; - break; - case MATCH_VSSRL_VI: + break; + case MATCH_VSSRL_VI: ir->opcode = rv_insn_vssrl_vi; - break; - case MATCH_VXOR_VI: + break; + case MATCH_VXOR_VI: ir->opcode = rv_insn_vxor_vi; - break; - default: - return false; + break; + default: + return false; } } @@ -2090,43 +2091,45 @@ static inline bool op_fvf(rv_insn_t *ir, const uint32_t insn) {} static inline bool op_mvx(rv_insn_t *ir, const uint32_t insn) {} /* OP: RVV - * opcode is 0x57 for VALU and VCFG + * opcode is 0x57 for VALU and VCFG * * VALU format: * 31 26 25 24 20 19 15 14 12 11 7 6 0 - * funct6 | vm | vs2 | vs1 | 0 0 0 (funct3) | vd |1010111| OP-V (OPIVV) - * funct6 | vm | vs2 | vs1 | 0 0 1 (funct3) | vd/rd |1010111| OP-V (OPFVV) - * funct6 | vm | vs2 | vs1 | 0 1 0 (funct3) | vd/rd |1010111| OP-V (OPMVV) - * funct6 | vm | vs2 | imm[4:0] | 0 1 1 (funct3) | vd |1010111| OP-V (OPIVI) - * funct6 | vm | vs2 | rs1 | 1 0 0 (funct3) | vd |1010111| OP-V (OPIVX) - * funct6 | vm | vs2 | rs1 | 1 0 1 (funct3) | vd |1010111| OP-V (OPFVF) - * funct6 | vm | vs2 | rs1 | 1 1 0 (funct3) | vd/rd |1010111| OP-V (OPMVX) - * 6 1 5 5 3 5 7 - * + * funct6 | vm | vs2 | vs1 | 0 0 0 (funct3) | vd |1010111| + * OP-V (OPIVV) funct6 | vm | vs2 | vs1 | 0 0 1 (funct3) | vd/rd + * |1010111| OP-V (OPFVV) funct6 | vm | vs2 | vs1 | 0 1 0 (funct3) + * | vd/rd |1010111| OP-V (OPMVV) funct6 | vm | vs2 | imm[4:0] | 0 1 1 + * (funct3) | vd |1010111| OP-V (OPIVI) funct6 | vm | vs2 | rs1 + * | 1 0 0 (funct3) | vd |1010111| OP-V (OPIVX) funct6 | vm | vs2 | + * rs1 | 1 0 1 (funct3) | vd |1010111| OP-V (OPFVF) funct6 | vm | vs2 + * | rs1 | 1 1 0 (funct3) | vd/rd |1010111| OP-V (OPMVX) 6 1 5 5 + * 3 5 7 + * * Where 'vm' is the bit indicates whether masking is enabled - * see https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#531-mask-encoding - * + * see + * https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#531-mask-encoding + * * VMEM format: - * + * * 31 29 28 27 26 25 24 20 19 15 14 12 11 7 6 0 - * nf | mew| mop | vm | lumop | rs1 | width | vd |0000111| VL* unit-stride - * nf | mew| mop | vm | rs2 | rs1 | width | vd |0000111| VLS* strided - * nf | mew| mop | vm | vs2 | rs1 | width | vd |0000111| VLX* indexed - * 3 1 2 1 5 5 3 5 7 - * + * nf | mew| mop | vm | lumop | rs1 | width | vd |0000111| VL* + * unit-stride nf | mew| mop | vm | rs2 | rs1 | width | vd + * |0000111| VLS* strided nf | mew| mop | vm | vs2 | rs1 | width | vd + * |0000111| VLX* indexed 3 1 2 1 5 5 3 5 7 + * * VCFG format: - * + * * 31 30 25 24 20 19 15 14 12 11 7 6 0 * 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli * 1 | 1| zimm[ 9:0] | uimm[4:0]| 1 1 1 | rd |1010111| vsetivli * 1 | 000000 | rs2 | rs1 | 1 1 1 | rd |1010111| vsetvl * 1 6 5 5 3 5 7 - * + * * reference: * https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/valu-format.edn * https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/v-inst-table.edn * https://observablehq.com/@drom/risc-v-v - * + * * funct3 * | 0 | 0 | 0 | OPIVV | vector-vector | N/A * | 0 | 0 | 1 | OPFVV | vector-vector | N/A @@ -2140,22 +2143,22 @@ static inline bool op_v(rv_insn_t *ir, const uint32_t insn) { uint32_t funct3_mask = 0x7000; switch ((insn & funct3_mask) >> 7) { - case 0: - return op_ivv(ir, insn); - case 1: - return op_fvv(ir, insn); - case 2: - return op_mvv(ir, insn); - case 3: - return op_ivi(ir, insn); - case 4: - return op_ivx(ir, insn); - case 5: - return op_fvf(ir, insn); - case 6: - return op_mvx(ir, insn); - default: - return false; + case 0: + return op_ivv(ir, insn); + case 1: + return op_fvv(ir, insn); + case 2: + return op_mvv(ir, insn); + case 3: + return op_ivi(ir, insn); + case 4: + return op_ivx(ir, insn); + case 5: + return op_fvf(ir, insn); + case 6: + return op_mvx(ir, insn); + default: + return false; } if ((insn & MASK_VSETVLI) == MATCH_VSETVLI) { @@ -2167,7 +2170,7 @@ static inline bool op_v(rv_insn_t *ir, const uint32_t insn) // vsetivli ir->rd = (insn >> 7) & 0x1f; ir->uimm = (insn >> 15) & 0x1f; - ir->zimm = (insn >> 20) & 0x3ff; // zimm[9:0] + ir->zimm = (insn >> 20) & 0x3ff; // zimm[9:0] } else if ((insn & MASK_VSETVL) == MATCH_VSETVL) { // vsetvl diff --git a/src/decode.h b/src/decode.h index 90f35788..8dccb3f4 100644 --- a/src/decode.h +++ b/src/decode.h @@ -195,30 +195,30 @@ enum op_field { _(fcvtswu, 0, 4, 0, ENC(rs1, rs2, rd)) \ _(fmvwx, 0, 4, 0, ENC(rs1, rs2, rd)) \ ) \ - IIF(RV32_HAS(EXT_RVV))( \ - _(vadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vand_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vmadc_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vmseq_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vmsgt_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vmsgtu_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vmsle_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vmsleu_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vmsne_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vor_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vrgather_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vrsub_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vsadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vsaddu_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vslidedown_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vslideup_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vsll_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vsra_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vsrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vssra_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vssrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - _(vxor_vi, 0, 4, 0, ENC(r1, r2, rd)) \ - ) \ + IIF(RV32_HAS(EXT_RVV))( \ + _(vadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vand_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vmadc_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vmseq_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vmsgt_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vmsgtu_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vmsle_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vmsleu_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vmsne_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vor_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vrgather_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vrsub_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vsadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vsaddu_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vslidedown_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vslideup_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vsll_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vsra_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vsrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vssra_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vssrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + _(vxor_vi, 0, 4, 0, ENC(r1, r2, rd)) \ + ) \ /* RV32C Standard Extension */ \ IIF(RV32_HAS(EXT_C))( \ _(caddi4spn, 0, 2, 1, ENC(rd)) \ diff --git a/src/encoding.h b/src/encoding.h index 0e8ab11a..bc95bcf5 100644 --- a/src/encoding.h +++ b/src/encoding.h @@ -13,308 +13,308 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_UBE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_VS 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS_SPELP 0x00800000 -#define MSTATUS_SDT 0x01000000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS_SBE 0x0000001000000000 -#define MSTATUS_MBE 0x0000002000000000 -#define MSTATUS_GVA 0x0000004000000000 -#define MSTATUS_MPV 0x0000008000000000 -#define MSTATUS_MPELP 0x0000020000000000 -#define MSTATUS_MDT 0x0000040000000000 -#define MSTATUS64_SD 0x8000000000000000 +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_UBE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_SUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_TVM 0x00100000 +#define MSTATUS_TW 0x00200000 +#define MSTATUS_TSR 0x00400000 +#define MSTATUS_SPELP 0x00800000 +#define MSTATUS_SDT 0x01000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS_UXL 0x0000000300000000 +#define MSTATUS_SXL 0x0000000C00000000 +#define MSTATUS_SBE 0x0000001000000000 +#define MSTATUS_MBE 0x0000002000000000 +#define MSTATUS_GVA 0x0000004000000000 +#define MSTATUS_MPV 0x0000008000000000 +#define MSTATUS_MPELP 0x0000020000000000 +#define MSTATUS_MDT 0x0000040000000000 +#define MSTATUS64_SD 0x8000000000000000 -#define MSTATUSH_SBE 0x00000010 -#define MSTATUSH_MBE 0x00000020 -#define MSTATUSH_GVA 0x00000040 -#define MSTATUSH_MPV 0x00000080 -#define MSTATUSH_MDT 0x00000400 +#define MSTATUSH_SBE 0x00000010 +#define MSTATUSH_MBE 0x00000020 +#define MSTATUSH_GVA 0x00000040 +#define MSTATUSH_MPV 0x00000080 +#define MSTATUSH_MDT 0x00000400 -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_UBE 0x00000040 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_VS 0x00000600 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS_SPELP 0x00800000 -#define SSTATUS_SDT 0x01000000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_UBE 0x00000040 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_VS 0x00000600 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_SUM 0x00040000 +#define SSTATUS_MXR 0x00080000 +#define SSTATUS_SPELP 0x00800000 +#define SSTATUS_SDT 0x01000000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS_UXL 0x0000000300000000 +#define SSTATUS64_SD 0x8000000000000000 -#define HSTATUS_VSXL 0x300000000 -#define HSTATUS_VTSR 0x00400000 -#define HSTATUS_VTW 0x00200000 -#define HSTATUS_VTVM 0x00100000 -#define HSTATUS_VGEIN 0x0003f000 -#define HSTATUS_HU 0x00000200 -#define HSTATUS_SPVP 0x00000100 -#define HSTATUS_SPV 0x00000080 -#define HSTATUS_GVA 0x00000040 -#define HSTATUS_VSBE 0x00000020 -#define HSTATUS_HUPMM 0x0003000000000000 +#define HSTATUS_VSXL 0x300000000 +#define HSTATUS_VTSR 0x00400000 +#define HSTATUS_VTW 0x00200000 +#define HSTATUS_VTVM 0x00100000 +#define HSTATUS_VGEIN 0x0003f000 +#define HSTATUS_HU 0x00000200 +#define HSTATUS_SPVP 0x00000100 +#define HSTATUS_SPV 0x00000080 +#define HSTATUS_GVA 0x00000040 +#define HSTATUS_VSBE 0x00000020 +#define HSTATUS_HUPMM 0x0003000000000000 -#define USTATUS_UIE 0x00000001 -#define USTATUS_UPIE 0x00000010 +#define USTATUS_UIE 0x00000001 +#define USTATUS_UPIE 0x00000010 -#define MNSTATUS_NMIE 0x00000008 -#define MNSTATUS_MNPV 0x00000080 -#define MNSTATUS_MNPELP 0x00000200 -#define MNSTATUS_MNPP 0x00001800 +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPELP 0x00000200 +#define MNSTATUS_MNPP 0x00001800 -#define DCSR_XDEBUGVER (15U<<28) -#define DCSR_EXTCAUSE (7<<24) -#define DCSR_CETRIG (1<<19) -#define DCSR_PELP (1<<18) -#define DCSR_EBREAKVS (1<<17) -#define DCSR_EBREAKVU (1<<16) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STEPIE (1<<11) -#define DCSR_STOPCOUNT (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_V (1<<5) -#define DCSR_MPRVEN (1<<4) -#define DCSR_NMIP (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) +#define DCSR_XDEBUGVER (15U << 28) +#define DCSR_EXTCAUSE (7 << 24) +#define DCSR_CETRIG (1 << 19) +#define DCSR_PELP (1 << 18) +#define DCSR_EBREAKVS (1 << 17) +#define DCSR_EBREAKVU (1 << 16) +#define DCSR_EBREAKM (1 << 15) +#define DCSR_EBREAKS (1 << 13) +#define DCSR_EBREAKU (1 << 12) +#define DCSR_STEPIE (1 << 11) +#define DCSR_STOPCOUNT (1 << 10) +#define DCSR_STOPTIME (1 << 9) +#define DCSR_CAUSE (7 << 6) +#define DCSR_V (1 << 5) +#define DCSR_MPRVEN (1 << 4) +#define DCSR_NMIP (1 << 3) +#define DCSR_STEP (1 << 2) +#define DCSR_PRV (3 << 0) -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 #define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 -#define DCSR_CAUSE_GROUP 6 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 +#define DCSR_CAUSE_GROUP 6 #define DCSR_CAUSE_EXTCAUSE 7 #define DCSR_EXTCAUSE_CRITERR 0 -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) +#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen) - 4)) +#define MCONTROL_DMODE(xlen) (1ULL << ((xlen) - 5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen) - 11)) -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0xf<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) +#define MCONTROL_SELECT (1 << 19) +#define MCONTROL_TIMING (1 << 18) +#define MCONTROL_ACTION (0xf << 12) +#define MCONTROL_CHAIN (1 << 11) +#define MCONTROL_MATCH (0xf << 7) +#define MCONTROL_M (1 << 6) +#define MCONTROL_H (1 << 5) +#define MCONTROL_S (1 << 4) +#define MCONTROL_U (1 << 3) +#define MCONTROL_EXECUTE (1 << 2) +#define MCONTROL_STORE (1 << 1) +#define MCONTROL_LOAD (1 << 0) -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 #define MCONTROL_MATCH_MASK_HIGH 5 -#define MIP_USIP (1 << IRQ_U_SOFT) -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_VSSIP (1 << IRQ_VS_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_UTIP (1 << IRQ_U_TIMER) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_VSTIP (1 << IRQ_VS_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_UEIP (1 << IRQ_U_EXT) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_VSEIP (1 << IRQ_VS_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) -#define MIP_SGEIP (1 << IRQ_S_GEXT) -#define MIP_LCOFIP (1 << IRQ_LCOF) -#define MIP_RAS_LOW_PRIO (1ULL << IRQ_RAS_LOW_PRIO) -#define MIP_RAS_HIGH_PRIO (1ULL << IRQ_RAS_HIGH_PRIO) +#define MIP_USIP (1 << IRQ_U_SOFT) +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_VSSIP (1 << IRQ_VS_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_UTIP (1 << IRQ_U_TIMER) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_VSTIP (1 << IRQ_VS_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_UEIP (1 << IRQ_U_EXT) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_VSEIP (1 << IRQ_VS_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) +#define MIP_LCOFIP (1 << IRQ_LCOF) +#define MIP_RAS_LOW_PRIO (1ULL << IRQ_RAS_LOW_PRIO) +#define MIP_RAS_HIGH_PRIO (1ULL << IRQ_RAS_HIGH_PRIO) -#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) -#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) -#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) +#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP) +#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define MIP_HS_MASK (MIP_VS_MASK | MIP_SGEIP) #define MIDELEG_FORCED_MASK MIP_HS_MASK #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP -#define MENVCFG_FIOM 0x00000001 -#define MENVCFG_LPE 0x00000004 -#define MENVCFG_SSE 0x00000008 -#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_LPE 0x00000004 +#define MENVCFG_SSE 0x00000008 +#define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 -#define MENVCFG_CBZE 0x00000080 -#define MENVCFG_PMM 0x0000000300000000 -#define MENVCFG_DTE 0x0800000000000000 -#define MENVCFG_ADUE 0x2000000000000000 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_PMM 0x0000000300000000 +#define MENVCFG_DTE 0x0800000000000000 +#define MENVCFG_ADUE 0x2000000000000000 #define MENVCFG_PBMTE 0x4000000000000000 -#define MENVCFG_STCE 0x8000000000000000 +#define MENVCFG_STCE 0x8000000000000000 -#define MENVCFGH_DTE 0x08000000 -#define MENVCFGH_ADUE 0x20000000 +#define MENVCFGH_DTE 0x08000000 +#define MENVCFGH_ADUE 0x20000000 #define MENVCFGH_PBMTE 0x40000000 -#define MENVCFGH_STCE 0x80000000 +#define MENVCFGH_STCE 0x80000000 -#define MSTATEEN0_CS 0x00000001 -#define MSTATEEN0_FCSR 0x00000002 -#define MSTATEEN0_JVT 0x00000004 -#define MSTATEEN0_CTR 0x0040000000000000 -#define MSTATEEN0_PRIV114 0x0080000000000000 +#define MSTATEEN0_CS 0x00000001 +#define MSTATEEN0_FCSR 0x00000002 +#define MSTATEEN0_JVT 0x00000004 +#define MSTATEEN0_CTR 0x0040000000000000 +#define MSTATEEN0_PRIV114 0x0080000000000000 #define MSTATEEN0_HCONTEXT 0x0200000000000000 -#define MSTATEEN0_AIA 0x0800000000000000 -#define MSTATEEN0_CSRIND 0x1000000000000000 -#define MSTATEEN0_HENVCFG 0x4000000000000000 -#define MSTATEEN_HSTATEEN 0x8000000000000000 +#define MSTATEEN0_AIA 0x0800000000000000 +#define MSTATEEN0_CSRIND 0x1000000000000000 +#define MSTATEEN0_HENVCFG 0x4000000000000000 +#define MSTATEEN_HSTATEEN 0x8000000000000000 -#define MSTATEEN0H_CTR 0x00400000 -#define MSTATEEN0H_PRIV114 0x00800000 +#define MSTATEEN0H_CTR 0x00400000 +#define MSTATEEN0H_PRIV114 0x00800000 #define MSTATEEN0H_HCONTEXT 0x02000000 -#define MSTATEEN0H_AIA 0x08000000 -#define MSTATEEN0H_CSRIND 0x10000000 -#define MSTATEEN0H_HENVCFG 0x40000000 -#define MSTATEENH_HSTATEEN 0x80000000 +#define MSTATEEN0H_AIA 0x08000000 +#define MSTATEEN0H_CSRIND 0x10000000 +#define MSTATEEN0H_HENVCFG 0x40000000 +#define MSTATEENH_HSTATEEN 0x80000000 #define MHPMEVENT_VUINH 0x0400000000000000 #define MHPMEVENT_VSINH 0x0800000000000000 -#define MHPMEVENT_UINH 0x1000000000000000 -#define MHPMEVENT_SINH 0x2000000000000000 -#define MHPMEVENT_MINH 0x4000000000000000 -#define MHPMEVENT_OF 0x8000000000000000 +#define MHPMEVENT_UINH 0x1000000000000000 +#define MHPMEVENT_SINH 0x2000000000000000 +#define MHPMEVENT_MINH 0x4000000000000000 +#define MHPMEVENT_OF 0x8000000000000000 #define MHPMEVENTH_VUINH 0x04000000 #define MHPMEVENTH_VSINH 0x08000000 -#define MHPMEVENTH_UINH 0x10000000 -#define MHPMEVENTH_SINH 0x20000000 -#define MHPMEVENTH_MINH 0x40000000 -#define MHPMEVENTH_OF 0x80000000 +#define MHPMEVENTH_UINH 0x10000000 +#define MHPMEVENTH_SINH 0x20000000 +#define MHPMEVENTH_MINH 0x40000000 +#define MHPMEVENTH_OF 0x80000000 -#define MCOUNTEREN_CY_SHIFT 0 -#define MCOUNTEREN_TIME_SHIFT 1 -#define MCOUNTEREN_IR_SHIFT 2 +#define MCOUNTEREN_CY_SHIFT 0 +#define MCOUNTEREN_TIME_SHIFT 1 +#define MCOUNTEREN_IR_SHIFT 2 -#define MCOUNTEREN_CY (1U << MCOUNTEREN_CY_SHIFT) -#define MCOUNTEREN_TIME (1U << MCOUNTEREN_TIME_SHIFT) -#define MCOUNTEREN_IR (1U << MCOUNTEREN_IR_SHIFT) +#define MCOUNTEREN_CY (1U << MCOUNTEREN_CY_SHIFT) +#define MCOUNTEREN_TIME (1U << MCOUNTEREN_TIME_SHIFT) +#define MCOUNTEREN_IR (1U << MCOUNTEREN_IR_SHIFT) -#define MCOUNTINHIBIT_CY MCOUNTEREN_CY -#define MCOUNTINHIBIT_IR MCOUNTEREN_IR +#define MCOUNTINHIBIT_CY MCOUNTEREN_CY +#define MCOUNTINHIBIT_IR MCOUNTEREN_IR -#define HENVCFG_FIOM 0x00000001 -#define HENVCFG_LPE 0x00000004 -#define HENVCFG_SSE 0x00000008 -#define HENVCFG_CBIE 0x00000030 +#define HENVCFG_FIOM 0x00000001 +#define HENVCFG_LPE 0x00000004 +#define HENVCFG_SSE 0x00000008 +#define HENVCFG_CBIE 0x00000030 #define HENVCFG_CBCFE 0x00000040 -#define HENVCFG_CBZE 0x00000080 -#define HENVCFG_PMM 0x0000000300000000 -#define HENVCFG_DTE 0x0800000000000000 -#define HENVCFG_ADUE 0x2000000000000000 +#define HENVCFG_CBZE 0x00000080 +#define HENVCFG_PMM 0x0000000300000000 +#define HENVCFG_DTE 0x0800000000000000 +#define HENVCFG_ADUE 0x2000000000000000 #define HENVCFG_PBMTE 0x4000000000000000 -#define HENVCFG_STCE 0x8000000000000000 +#define HENVCFG_STCE 0x8000000000000000 -#define HENVCFGH_DTE 0x08000000 -#define HENVCFGH_ADUE 0x20000000 +#define HENVCFGH_DTE 0x08000000 +#define HENVCFGH_ADUE 0x20000000 #define HENVCFGH_PBMTE 0x40000000 -#define HENVCFGH_STCE 0x80000000 +#define HENVCFGH_STCE 0x80000000 -#define SISELECT_SMCDELEG_START 0x40 -#define SISELECT_SMCDELEG_UNUSED 0x41 -#define SISELECT_SMCDELEG_INSTRET 0x42 -#define SISELECT_SMCDELEG_INSTRETCFG 0x42 +#define SISELECT_SMCDELEG_START 0x40 +#define SISELECT_SMCDELEG_UNUSED 0x41 +#define SISELECT_SMCDELEG_INSTRET 0x42 +#define SISELECT_SMCDELEG_INSTRETCFG 0x42 /* * ?iselect values for hpmcounters4..31 and hpmevent4..31 * can easily computed, and were elided for brevity. */ -#define SISELECT_SMCDELEG_HPMCOUNTER_3 0x43 -#define SISELECT_SMCDELEG_HPMEVENT_3 0x43 -#define SISELECT_SMCDELEG_END 0x5f +#define SISELECT_SMCDELEG_HPMCOUNTER_3 0x43 +#define SISELECT_SMCDELEG_HPMEVENT_3 0x43 +#define SISELECT_SMCDELEG_END 0x5f -#define HSTATEEN0_CS 0x00000001 -#define HSTATEEN0_FCSR 0x00000002 -#define HSTATEEN0_JVT 0x00000004 -#define HSTATEEN0_CTR 0x0040000000000000 +#define HSTATEEN0_CS 0x00000001 +#define HSTATEEN0_FCSR 0x00000002 +#define HSTATEEN0_JVT 0x00000004 +#define HSTATEEN0_CTR 0x0040000000000000 #define HSTATEEN0_SCONTEXT 0x0200000000000000 -#define HSTATEEN0_AIA 0x0800000000000000 -#define HSTATEEN0_CSRIND 0x1000000000000000 -#define HSTATEEN0_SENVCFG 0x4000000000000000 -#define HSTATEEN_SSTATEEN 0x8000000000000000 +#define HSTATEEN0_AIA 0x0800000000000000 +#define HSTATEEN0_CSRIND 0x1000000000000000 +#define HSTATEEN0_SENVCFG 0x4000000000000000 +#define HSTATEEN_SSTATEEN 0x8000000000000000 -#define HSTATEEN0H_CTR 0x00400000 +#define HSTATEEN0H_CTR 0x00400000 #define HSTATEEN0H_SCONTEXT 0x02000000 -#define HSTATEEN0H_AIA 0x08000000 -#define HSTATEEN0H_CSRIND 0x10000000 -#define HSTATEEN0H_SENVCFG 0x40000000 -#define HSTATEENH_SSTATEEN 0x80000000 +#define HSTATEEN0H_AIA 0x08000000 +#define HSTATEEN0H_CSRIND 0x10000000 +#define HSTATEEN0H_SENVCFG 0x40000000 +#define HSTATEENH_SSTATEEN 0x80000000 -#define SENVCFG_FIOM 0x00000001 -#define SENVCFG_LPE 0x00000004 -#define SENVCFG_SSE 0x00000008 -#define SENVCFG_CBIE 0x00000030 +#define SENVCFG_FIOM 0x00000001 +#define SENVCFG_LPE 0x00000004 +#define SENVCFG_SSE 0x00000008 +#define SENVCFG_CBIE 0x00000030 #define SENVCFG_CBCFE 0x00000040 -#define SENVCFG_CBZE 0x00000080 -#define SENVCFG_PMM 0x0000000300000000 +#define SENVCFG_CBZE 0x00000080 +#define SENVCFG_PMM 0x0000000300000000 -#define SSTATEEN0_CS 0x00000001 +#define SSTATEEN0_CS 0x00000001 #define SSTATEEN0_FCSR 0x00000002 -#define SSTATEEN0_JVT 0x00000004 +#define SSTATEEN0_JVT 0x00000004 -#define MSECCFG_MML 0x00000001 -#define MSECCFG_MMWP 0x00000002 -#define MSECCFG_RLB 0x00000004 -#define MSECCFG_USEED 0x00000100 -#define MSECCFG_SSEED 0x00000200 -#define MSECCFG_MLPE 0x00000400 -#define MSECCFG_PMM 0x0000000300000000 +#define MSECCFG_MML 0x00000001 +#define MSECCFG_MMWP 0x00000002 +#define MSECCFG_RLB 0x00000004 +#define MSECCFG_USEED 0x00000100 +#define MSECCFG_SSEED 0x00000200 +#define MSECCFG_MLPE 0x00000400 +#define MSECCFG_PMM 0x0000000300000000 /* jvt fields */ -#define JVT_MODE 0x3F -#define JVT_BASE (~0x3F) +#define JVT_MODE 0x3F +#define JVT_BASE (~0x3F) -#define HVICTL_VTI 0x40000000 -#define HVICTL_IID 0x003F0000 -#define HVICTL_DPR 0x00000200 +#define HVICTL_VTI 0x40000000 +#define HVICTL_IID 0x003F0000 +#define HVICTL_DPR 0x00000200 #define HVICTL_IPRIOM 0x00000100 -#define HVICTL_IPRIO 0x000000FF +#define HVICTL_IPRIO 0x000000FF -#define MTOPI_IID 0x0FFF0000 +#define MTOPI_IID 0x0FFF0000 #define MTOPI_IPRIO 0x000000FF #define PRV_U 0 @@ -325,12 +325,12 @@ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF +#define SATP32_PPN 0x003FFFFF #define SATP64_MODE 0xF000000000000000 #define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF +#define SATP64_PPN 0x00000FFFFFFFFFFF -#define SATP_MODE_OFF 0 +#define SATP_MODE_OFF 0 #define SATP_MODE_SV32 1 #define SATP_MODE_SV39 8 #define SATP_MODE_SV48 9 @@ -351,124 +351,124 @@ #define HGATP_MODE_SV48X4 9 #define HGATP_MODE_SV57X4 10 -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_L 0x80 #define PMP_SHIFT 2 -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 #define PMP_NAPOT 0x18 -#define MCTRCTL_U 0x0000000000000001 -#define MCTRCTL_S 0x0000000000000002 -#define MCTRCTL_M 0x0000000000000004 -#define MCTRCTL_RASEMU 0x0000000000000080 -#define MCTRCTL_STE 0x0000000000000100 -#define MCTRCTL_MTE 0x0000000000000200 -#define MCTRCTL_BPFRZ 0x0000000000000800 -#define MCTRCTL_LCOFIFRZ 0x0000000000001000 -#define MCTRCTL_EXCINH 0x0000000200000000 -#define MCTRCTL_INTRINH 0x0000000400000000 -#define MCTRCTL_TRETINH 0x0000000800000000 -#define MCTRCTL_NTBREN 0x0000001000000000 -#define MCTRCTL_TKBRINH 0x0000002000000000 +#define MCTRCTL_U 0x0000000000000001 +#define MCTRCTL_S 0x0000000000000002 +#define MCTRCTL_M 0x0000000000000004 +#define MCTRCTL_RASEMU 0x0000000000000080 +#define MCTRCTL_STE 0x0000000000000100 +#define MCTRCTL_MTE 0x0000000000000200 +#define MCTRCTL_BPFRZ 0x0000000000000800 +#define MCTRCTL_LCOFIFRZ 0x0000000000001000 +#define MCTRCTL_EXCINH 0x0000000200000000 +#define MCTRCTL_INTRINH 0x0000000400000000 +#define MCTRCTL_TRETINH 0x0000000800000000 +#define MCTRCTL_NTBREN 0x0000001000000000 +#define MCTRCTL_TKBRINH 0x0000002000000000 #define MCTRCTL_INDCALLINH 0x0000010000000000 #define MCTRCTL_DIRCALLINH 0x0000020000000000 -#define MCTRCTL_INDJMPINH 0x0000040000000000 -#define MCTRCTL_DIRJMPINH 0x0000080000000000 +#define MCTRCTL_INDJMPINH 0x0000040000000000 +#define MCTRCTL_DIRJMPINH 0x0000080000000000 #define MCTRCTL_CORSWAPINH 0x0000100000000000 -#define MCTRCTL_RETINH 0x0000200000000000 +#define MCTRCTL_RETINH 0x0000200000000000 #define MCTRCTL_INDLJMPINH 0x0000400000000000 #define MCTRCTL_DIRLJMPINH 0x0000800000000000 -#define SCTRCTL_U 0x0000000000000001 -#define SCTRCTL_S 0x0000000000000002 -#define SCTRCTL_RASEMU 0x0000000000000080 -#define SCTRCTL_STE 0x0000000000000100 -#define SCTRCTL_BPFRZ 0x0000000000000800 -#define SCTRCTL_LCOFIFRZ 0x0000000000001000 -#define SCTRCTL_EXCINH 0x0000000200000000 -#define SCTRCTL_INTRINH 0x0000000400000000 -#define SCTRCTL_TRETINH 0x0000000800000000 -#define SCTRCTL_NTBREN 0x0000001000000000 -#define SCTRCTL_TKBRINH 0x0000002000000000 +#define SCTRCTL_U 0x0000000000000001 +#define SCTRCTL_S 0x0000000000000002 +#define SCTRCTL_RASEMU 0x0000000000000080 +#define SCTRCTL_STE 0x0000000000000100 +#define SCTRCTL_BPFRZ 0x0000000000000800 +#define SCTRCTL_LCOFIFRZ 0x0000000000001000 +#define SCTRCTL_EXCINH 0x0000000200000000 +#define SCTRCTL_INTRINH 0x0000000400000000 +#define SCTRCTL_TRETINH 0x0000000800000000 +#define SCTRCTL_NTBREN 0x0000001000000000 +#define SCTRCTL_TKBRINH 0x0000002000000000 #define SCTRCTL_INDCALLINH 0x0000010000000000 #define SCTRCTL_DIRCALLINH 0x0000020000000000 -#define SCTRCTL_INDJMPINH 0x0000040000000000 -#define SCTRCTL_DIRJMPINH 0x0000080000000000 +#define SCTRCTL_INDJMPINH 0x0000040000000000 +#define SCTRCTL_DIRJMPINH 0x0000080000000000 #define SCTRCTL_CORSWAPINH 0x0000100000000000 -#define SCTRCTL_RETINH 0x0000200000000000 +#define SCTRCTL_RETINH 0x0000200000000000 #define SCTRCTL_INDLJMPINH 0x0000400000000000 #define SCTRCTL_DIRLJMPINH 0x0000800000000000 -#define VSCTRCTL_U 0x0000000000000001 -#define VSCTRCTL_S 0x0000000000000002 -#define VSCTRCTL_RASEMU 0x0000000000000080 -#define VSCTRCTL_STE 0x0000000000000100 -#define VSCTRCTL_BPFRZ 0x0000000000000800 -#define VSCTRCTL_LCOFIFRZ 0x0000000000001000 -#define VSCTRCTL_EXCINH 0x0000000200000000 -#define VSCTRCTL_INTRINH 0x0000000400000000 -#define VSCTRCTL_TRETINH 0x0000000800000000 -#define VSCTRCTL_NTBREN 0x0000001000000000 -#define VSCTRCTL_TKBRINH 0x0000002000000000 +#define VSCTRCTL_U 0x0000000000000001 +#define VSCTRCTL_S 0x0000000000000002 +#define VSCTRCTL_RASEMU 0x0000000000000080 +#define VSCTRCTL_STE 0x0000000000000100 +#define VSCTRCTL_BPFRZ 0x0000000000000800 +#define VSCTRCTL_LCOFIFRZ 0x0000000000001000 +#define VSCTRCTL_EXCINH 0x0000000200000000 +#define VSCTRCTL_INTRINH 0x0000000400000000 +#define VSCTRCTL_TRETINH 0x0000000800000000 +#define VSCTRCTL_NTBREN 0x0000001000000000 +#define VSCTRCTL_TKBRINH 0x0000002000000000 #define VSCTRCTL_INDCALLINH 0x0000010000000000 #define VSCTRCTL_DIRCALLINH 0x0000020000000000 -#define VSCTRCTL_INDJMPINH 0x0000040000000000 -#define VSCTRCTL_DIRJMPINH 0x0000080000000000 +#define VSCTRCTL_INDJMPINH 0x0000040000000000 +#define VSCTRCTL_DIRJMPINH 0x0000080000000000 #define VSCTRCTL_CORSWAPINH 0x0000100000000000 -#define VSCTRCTL_RETINH 0x0000200000000000 +#define VSCTRCTL_RETINH 0x0000200000000000 #define VSCTRCTL_INDLJMPINH 0x0000400000000000 #define VSCTRCTL_DIRLJMPINH 0x0000800000000000 -#define SCTRDEPTH_DEPTH 0x00000007 +#define SCTRDEPTH_DEPTH 0x00000007 -#define SCTRSTATUS_WRPTR 0x000000FF -#define SCTRSTATUS_FROZEN 0x80000000 +#define SCTRSTATUS_WRPTR 0x000000FF +#define SCTRSTATUS_FROZEN 0x80000000 -#define IRQ_U_SOFT 0 -#define IRQ_S_SOFT 1 -#define IRQ_VS_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_U_TIMER 4 -#define IRQ_S_TIMER 5 -#define IRQ_VS_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_U_EXT 8 -#define IRQ_S_EXT 9 -#define IRQ_VS_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_S_GEXT 12 -#define IRQ_COP 12 -#define IRQ_LCOF 13 -#define IRQ_RAS_LOW_PRIO 35 +#define IRQ_U_SOFT 0 +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_U_TIMER 4 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_U_EXT 8 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_COP 12 +#define IRQ_LCOF 13 +#define IRQ_RAS_LOW_PRIO 35 #define IRQ_RAS_HIGH_PRIO 43 /* page table entry (PTE) fields */ -#define PTE_V 0x001 /* Valid */ -#define PTE_R 0x002 /* Read */ -#define PTE_W 0x004 /* Write */ -#define PTE_X 0x008 /* Execute */ -#define PTE_U 0x010 /* User */ -#define PTE_G 0x020 /* Global */ -#define PTE_A 0x040 /* Accessed */ -#define PTE_D 0x080 /* Dirty */ -#define PTE_SOFT 0x300 /* Reserved for Software */ -#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ -#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ -#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ -#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ +#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ +#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ #define PTE_PPN_SHIFT 10 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) /* srmcfg CSR fields */ -#define SRMCFG_RCID 0x00000FFF -#define SRMCFG_MCID 0x0FFF0000 +#define SRMCFG_RCID 0x00000FFF +#define SRMCFG_MCID 0x0FFF0000 /* software check exception xtval codes */ #define LANDING_PAD_FAULT 2 @@ -477,15 +477,15 @@ #ifdef __riscv #if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SATP_MODE SATP64_MODE +#define MSTATUS_SD MSTATUS64_SD +#define SSTATUS_SD SSTATUS64_SD +#define RISCV_PGLEVEL_BITS 9 +#define SATP_MODE SATP64_MODE #else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SATP_MODE SATP32_MODE +#define MSTATUS_SD MSTATUS32_SD +#define SSTATUS_SD SSTATUS32_SD +#define RISCV_PGLEVEL_BITS 10 +#define SATP_MODE SATP32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) @@ -494,24 +494,35 @@ #ifdef __GNUC__ -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) +#define read_csr(reg) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; \ + }) -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) +#define write_csr(reg, val) ({ asm volatile("csrw " #reg ", %0" ::"rK"(val)); }) -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) +#define swap_csr(reg, val) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + __tmp; \ + }) -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) +#define set_csr(reg, bit) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; \ + }) -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) +#define clear_csr(reg, bit) \ + ({ \ + unsigned long __tmp; \ + asm volatile("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + __tmp; \ + }) #define rdtime() read_csr(time) #define rdcycle() read_csr(cycle) diff --git a/src/riscv_private.h b/src/riscv_private.h index 5cdf0b61..590dc170 100644 --- a/src/riscv_private.h +++ b/src/riscv_private.h @@ -136,10 +136,10 @@ struct riscv_internal { #endif #if RV32_HAS(EXT_RVV) -#define VLEN 128 // FIXME should not use a const and not even here for VLEN - uint8_t V1[(VLEN>>3)]; - uint8_t V2[(VLEN>>3)]; - uint8_t Vd[(VLEN>>3)]; +#define VLEN 128 // FIXME should not use a const and not even here for VLEN + uint8_t V1[(VLEN >> 3)]; + uint8_t V2[(VLEN >> 3)]; + uint8_t Vd[(VLEN >> 3)]; uint8_t vl; /* current vl size */ uint8_t lmul; uint8_t sew; /* current sew size */ diff --git a/src/rv32_vector.c b/src/rv32_vector.c index fc9f6a92..c29862ab 100644 --- a/src/rv32_vector.c +++ b/src/rv32_vector.c @@ -1,40 +1,49 @@ /* RV32 RVV Instruction Set */ -RVOP(vsetvli, { - // | `vlmul[2:0]` | LMUL | #groups | VLMAX | Registers grouped with register `n` | - // |--------------|--------|---------|-----------------|--------------------------------------------------| - // | `1 0 0` | - | - | - | Reserved | - // | `1 0 1` | `1/8` | 32 | `VLEN/SEW/8` | `v_n` (single register in group) | - // | `1 1 0` | `1/4` | 32 | `VLEN/SEW/4` | `v_n` (single register in group) | - // | `1 1 1` | `1/2` | 32 | `VLEN/SEW/2` | `v_n` (single register in group) | - // | `0 0 0` | `1` | 32 | `VLEN/SEW` | `v_n` (single register in group) | - // | `0 0 1` | `2` | 16 | `2*VLEN/SEW` | `v_n`, `v_n+1` | - // | `0 1 0` | `4` | 8 | `4*VLEN/SEW` | `v_n`, ..., `v_n+3` | - // | `0 1 1` | `8` | 4 | `8*VLEN/SEW` | `v_n`, ..., `v_n+7` | - rv->lmul = 1<<(ir->zimm & 0x3); - if (ir->zimm & 0x4) { - rv->lmul = 1; - } +RVOP( + vsetvli, + { + // | `vlmul[2:0]` | LMUL | #groups | VLMAX | Registers + // grouped with register `n` | + // |--------------|--------|---------|-----------------|--------------------------------------------------| + // | `1 0 0` | - | - | - | Reserved | | `1 + // 0 1` | `1/8` | 32 | `VLEN/SEW/8` | `v_n` (single + // register in group) | | `1 1 0` | `1/4` | 32 | + // `VLEN/SEW/4` | `v_n` (single register in group) | + // | `1 1 1` | `1/2` | 32 | `VLEN/SEW/2` | `v_n` (single + // register in group) | | `0 0 0` | `1` | 32 | + // `VLEN/SEW` | `v_n` (single register in group) | + // | `0 0 1` | `2` | 16 | `2*VLEN/SEW` | `v_n`, `v_n+1` + // | | `0 1 0` | `4` | 8 | `4*VLEN/SEW` | `v_n`, ..., + // `v_n+3` | | `0 1 1` | `8` | 4 | + // `8*VLEN/SEW` | `v_n`, ..., `v_n+7` | + rv->lmul = 1 << (ir->zimm & 0x3); + if (ir->zimm & 0x4) { + rv->lmul = 1; + } - // | `vsew[2:0]` | SEW | - // |-------------|----------| - // | 0 0 0 | 8 | - // | 0 0 1 | 16 | - // | 0 1 0 | 32 | - // | 0 1 1 | 64 | - // | 1 X X | Reserved | - rv->sew = 8 << (ir->zimm & 0xf); - }, GEN({/* no operation */})) + // | `vsew[2:0]` | SEW | + // |-------------|----------| + // | 0 0 0 | 8 | + // | 0 0 1 | 16 | + // | 0 1 0 | 32 | + // | 0 1 1 | 64 | + // | 1 X X | Reserved | + rv->sew = 8 << (ir->zimm & 0xf); + }, + GEN({/* no operation */})) -#define ADD_VV(BIT) \ - static inline *int##BIT##_t add_vv_i##BIT##(int##BIT##_t *a, int##BIT##_t *b, size_t size) { \ - int##BIT##_t c[size];\ - for (int i = 0; i < size; i++) {\ - c[i]=a[i]+b[i];\ - }\ - return c;\ - } +#define ADD_VV(BIT) \ + static inline *int##BIT##_t add_vv_i##BIT##(int##BIT##_t *a, \ + int##BIT##_t *b, size_t size) \ + { \ + int##BIT##_t c[size]; \ + for (int i = 0; i < size; i++) { \ + c[i] = a[i] + b[i]; \ + } \ + return c; \ + } ADD_VV(8) ADD_VV(16) ADD_VV(32) @@ -42,26 +51,32 @@ ADD_VV(64) RVOP(vadd_vi, { rv->V1[rv_reg_zero] = 0; }, GEN({/* no operation */})) -RVOP(vadd_vv, { - switch (rv->sew) { - case 8: - rv->Vd = (* int8_t)add_vv_i8((*int8_t)rv->V1, (*int8_t)rv->V2, rv-vl/8); - break; - case 16: - rv->Vd = (* int8_t)add_vv_i16((*int16_t)rv->V1, (*int16_t)rv->V2, rv-vl/16); - break; - case 32: - rv->Vd = (* int8_t)add_vv_i32((*int32_t)rv->V1, (*int32_t)rv->V2, rv-vl/32); - break; - case 64: - rv->Vd = (* int8_t)add_vv_i64((*int64_t)rv->V1, (*int64_t)rv->V2, rv-vl/64); - break; - - default: - break; - } +RVOP( + vadd_vv, + { + switch (rv->sew) { + case 8: + rv->Vd = (*int8_t) add_vv_i8((*int8_t) rv->V1, (*int8_t) rv->V2, + rv - vl / 8); + break; + case 16: + rv->Vd = (*int8_t) add_vv_i16((*int16_t) rv->V1, (*int16_t) rv->V2, + rv - vl / 16); + break; + case 32: + rv->Vd = (*int8_t) add_vv_i32((*int32_t) rv->V1, (*int32_t) rv->V2, + rv - vl / 32); + break; + case 64: + rv->Vd = (*int8_t) add_vv_i64((*int64_t) rv->V1, (*int64_t) rv->V2, + rv - vl / 64); + break; -}, GEN({/* no operation */})) + default: + break; + } + }, + GEN({/* no operation */})) RVOP(vand_vi, { rv->Vd[rv_reg_zero] = 0; }, GEN({/* no operation */})) RVOP(vand_vv, { rv->Vd[rv_reg_zero] = 0; }, GEN({/* no operation */})) RVOP(vmadc_vi, { rv->Vd[rv_reg_zero] = 0; }, GEN({/* no operation */})) diff --git a/tests/rvsim.c b/tests/rvsim.c index fbe22022..4dfdf227 100644 --- a/tests/rvsim.c +++ b/tests/rvsim.c @@ -39,6 +39,7 @@ enum { MAX_STEPS = 100 }; // TODO: make this a command-line argument #define EXT_F 0 #define EXT_D 0 #define EXT_C 1 +#define EXT_RVV 1 #define OPCODE_LIST_RV32I \ X(0x0000007f, 0x00000037, FMT_U, MNEM_LUI, "lui") \