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Hi, thanks for the solution; I just wanted to inform you the the last line:
// is output negative? muxout.out[4] -> and.in1, 1 -> and.in2, and.out -> negative
is not necessary, since you can directly pass: muxout.out[4] -> negative (and therefore even delete the AND gate completely).
muxout.out[4] -> negative
Cheers ;)
The text was updated successfully, but these errors were encountered:
... huh, that's kind of obvious in retrospect!
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Hi,
thanks for the solution; I just wanted to inform you the the last line:
is not necessary, since you can directly pass:
muxout.out[4] -> negative
(and therefore even delete the AND gate completely).Cheers ;)
The text was updated successfully, but these errors were encountered: