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RTC - Rename RTCSrc -> RtcSrc
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usbalbin committed Aug 4, 2024
1 parent 843c1e8 commit 5f2dcf3
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Showing 3 changed files with 13 additions and 13 deletions.
2 changes: 1 addition & 1 deletion src/rcc/config.rs
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ pub enum PLLSrc {

/// RTC clock input source
#[derive(Clone, Copy)]
pub enum RTCSrc {
pub enum RtcSrc {
LSE,
LSE_BYPASS,
LSI,
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18 changes: 9 additions & 9 deletions src/rcc/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -465,7 +465,7 @@ impl Rcc {
while pwr.cr1.read().dbp().bit_is_clear() {}
}

pub(crate) fn enable_rtc(&self, src: RTCSrc) {
pub(crate) fn enable_rtc(&self, src: RtcSrc) {
self.unlock_rtc();
self.rb
.apb1enr1
Expand All @@ -474,9 +474,9 @@ impl Rcc {
self.rb.bdcr.modify(|_, w| w.bdrst().set_bit());

let rtc_sel = match src {
RTCSrc::LSE | RTCSrc::LSE_BYPASS => 0b01,
RTCSrc::LSI => 0b10,
RTCSrc::HSE | RTCSrc::HSE_BYPASS => 0b11,
RtcSrc::LSE | RtcSrc::LSE_BYPASS => 0b01,
RtcSrc::LSI => 0b10,
RtcSrc::HSE | RtcSrc::HSE_BYPASS => 0b11,
};

self.rb.bdcr.modify(|_, w| {
Expand All @@ -490,11 +490,11 @@ impl Rcc {

self.unlock_rtc();
match src {
RTCSrc::LSE => self.enable_lse(false),
RTCSrc::LSE_BYPASS => self.enable_lse(true),
RTCSrc::LSI => self.enable_lsi(),
RTCSrc::HSE => self.enable_hse(false),
RTCSrc::HSE_BYPASS => self.enable_hse(true),
RtcSrc::LSE => self.enable_lse(false),
RtcSrc::LSE_BYPASS => self.enable_lse(true),
RtcSrc::LSI => self.enable_lsi(),
RtcSrc::HSE => self.enable_hse(false),
RtcSrc::HSE_BYPASS => self.enable_hse(true),
};
}
}
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6 changes: 3 additions & 3 deletions src/rtc.rs
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
//! Real Time Clock
use core::convert::TryInto;

use crate::rcc::{RTCSrc, Rcc};
use crate::rcc::{RtcSrc, Rcc};
use crate::stm32::RTC;
use crate::time::{self, *};

Expand Down Expand Up @@ -108,7 +108,7 @@ pub struct Rtc {
}

impl Rtc {
pub fn new(rtc: RTC, src: RTCSrc, rcc: &mut Rcc) -> Self {
pub fn new(rtc: RTC, src: RtcSrc, rcc: &mut Rcc) -> Self {
rcc.enable_rtc(src);
Rtc { rb: rtc }
}
Expand Down Expand Up @@ -346,7 +346,7 @@ pub trait RtcExt {

impl RtcExt for RTC {
fn constrain(self, rcc: &mut Rcc) -> Rtc {
Rtc::new(self, RTCSrc::LSI, rcc)
Rtc::new(self, RtcSrc::LSI, rcc)
}
}

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