From 145ba50ddd8f70b91caf66dde94282bf6c881b11 Mon Sep 17 00:00:00 2001 From: Albin Hedman Date: Thu, 7 Nov 2024 22:03:02 +0100 Subject: [PATCH] Slightly demacrofy DMA --- src/dma/stream.rs | 564 +++++++++++++++++++++++----------------------- 1 file changed, 282 insertions(+), 282 deletions(-) diff --git a/src/dma/stream.rs b/src/dma/stream.rs index eb5f1acf..76cf60c6 100644 --- a/src/dma/stream.rs +++ b/src/dma/stream.rs @@ -182,329 +182,329 @@ impl StreamsTuple { // the stream macro_rules! dma_stream { ($(($name:ident, $number:expr, $x:literal)),+$(,)*) => { - paste::paste!{ - $( - impl Stream for $name { - - const NUMBER: usize = $number; - type Config = DmaConfig; - type Interrupts = DmaInterrupts; - - fn apply_config(&mut self, config: DmaConfig) { - self.set_priority(config.priority); - self.set_memory_increment(config.memory_increment); - self.set_peripheral_increment(config.peripheral_increment); - self.set_circular_buffer(config.circular_buffer); - self.set_transfer_complete_interrupt_enable( - config.transfer_complete_interrupt - ); - self.set_half_transfer_interrupt_enable(config.half_transfer_interrupt); - self.set_transfer_error_interrupt_enable( - config.transfer_error_interrupt - ); - } + $( + impl Stream for $name { + + const NUMBER: usize = $number; + type Config = DmaConfig; + type Interrupts = DmaInterrupts; + + fn apply_config(&mut self, config: DmaConfig) { + self.set_priority(config.priority); + self.set_memory_increment(config.memory_increment); + self.set_peripheral_increment(config.peripheral_increment); + self.set_circular_buffer(config.circular_buffer); + self.set_transfer_complete_interrupt_enable( + config.transfer_complete_interrupt + ); + self.set_half_transfer_interrupt_enable(config.half_transfer_interrupt); + self.set_transfer_error_interrupt_enable( + config.transfer_error_interrupt + ); + } - #[inline(always)] - fn clear_interrupts(&mut self) { - //NOTE(unsafe) Atomic write with no side-effects and we only access the bits - // that belongs to the StreamX - let dma = unsafe { &*I::ptr() }; - dma.ifcr().write(|w| w - .[]().set_bit() //Clear transfer complete interrupt flag - .[]().set_bit() //Clear half transfer interrupt flag - .[]().set_bit() //Clear transfer error interrupt flag - .[]().set_bit() //Clear global interrupt flag - ); - let _ = dma.isr().read(); - let _ = dma.isr().read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn clear_interrupts(&mut self) { + let num = Self::NUMBER as u8; + + //NOTE(unsafe) Atomic write with no side-effects and we only access the bits + // that belongs to the StreamX + let dma = unsafe { &*I::ptr() }; + dma.ifcr().write(|w| w + .ctcif(num).set_bit() //Clear transfer complete interrupt flag + .chtif(num).set_bit() //Clear half transfer interrupt flag + .cteif(num).set_bit() //Clear transfer error interrupt flag + .cgif(num).set_bit() //Clear global interrupt flag + ); + let _ = dma.isr().read(); + let _ = dma.isr().read(); // Delay 2 peripheral clocks + } - #[inline(always)] - fn clear_transfer_complete_flag(&mut self) { - //NOTE(unsafe) Atomic write with no side-effects and we only access the bits - // that belongs to the StreamX - let dma = unsafe { &*I::ptr() }; - dma.ifcr().write(|w| w.[]().set_bit()); - } + #[inline(always)] + fn clear_transfer_complete_flag(&mut self) { + //NOTE(unsafe) Atomic write with no side-effects and we only access the bits + // that belongs to the StreamX + let dma = unsafe { &*I::ptr() }; + dma.ifcr().write(|w| w.ctcif(Self::NUMBER as u8).set_bit()); + } - #[inline(always)] - fn clear_transfer_complete_interrupt(&mut self) { - self.clear_transfer_complete_flag(); - //NOTE(unsafe) Atomic read with no side-effects. - let dma = unsafe { &*I::ptr() }; - let _ = dma.isr().read(); - let _ = dma.isr().read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn clear_transfer_complete_interrupt(&mut self) { + self.clear_transfer_complete_flag(); + //NOTE(unsafe) Atomic read with no side-effects. + let dma = unsafe { &*I::ptr() }; + let _ = dma.isr().read(); + let _ = dma.isr().read(); // Delay 2 peripheral clocks + } - #[inline(always)] - fn clear_transfer_error_interrupt(&mut self) { - //NOTE(unsafe) Atomic write with no side-effects and we only access the bits - // that belongs to the StreamX - let dma = unsafe { &*I::ptr() }; - dma.ifcr().write(|w| w.[]().set_bit()); - let _ = dma.isr().read(); - let _ = dma.isr().read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn clear_transfer_error_interrupt(&mut self) { + //NOTE(unsafe) Atomic write with no side-effects and we only access the bits + // that belongs to the StreamX + let dma = unsafe { &*I::ptr() }; + dma.ifcr().write(|w| w.ctcif(Self::NUMBER as u8).set_bit()); + let _ = dma.isr().read(); + let _ = dma.isr().read(); // Delay 2 peripheral clocks + } - #[inline(always)] - fn get_transfer_complete_flag() -> bool { - //NOTE(unsafe) Atomic read with no side effects - let dma = unsafe { &*I::ptr() }; - dma.isr().read().[]().bit_is_set() - } + #[inline(always)] + fn get_transfer_complete_flag() -> bool { + //NOTE(unsafe) Atomic read with no side effects + let dma = unsafe { &*I::ptr() }; + dma.isr().read().tcif(Self::NUMBER as u8).bit_is_set() + } - #[inline(always)] - fn get_transfer_error_flag() -> bool { - //NOTE(unsafe) Atomic read with no side effects - let dma = unsafe { &*I::ptr() }; - dma.isr().read().[]().bit_is_set() - } + #[inline(always)] + fn get_transfer_error_flag() -> bool { + //NOTE(unsafe) Atomic read with no side effects + let dma = unsafe { &*I::ptr() }; + dma.isr().read().tcif(Self::NUMBER as u8).bit_is_set() + } - #[inline(always)] - unsafe fn enable(&mut self) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = &unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| w.en().set_bit()); - } + #[inline(always)] + unsafe fn enable(&mut self) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = &unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| w.en().set_bit()); + } - #[inline(always)] - fn is_enabled() -> bool { - //NOTE(unsafe) Atomic read with no side effects - let dma_ch = &unsafe { &*I::ptr() }.[](); - dma_ch.cr().read().en().bit_is_set() - } + #[inline(always)] + fn is_enabled() -> bool { + //NOTE(unsafe) Atomic read with no side effects + let dma_ch = &unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().read().en().bit_is_set() + } - fn disable(&mut self) { - if Self::is_enabled() { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = &unsafe { &*I::ptr() }.[](); + fn disable(&mut self) { + if Self::is_enabled() { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = &unsafe { &*I::ptr() }.ch(Self::NUMBER); - // Aborting an on-going transfer might cause interrupts to fire, disable - // them - let interrupts = Self::get_interrupts_enable(); - self.disable_interrupts(); + // Aborting an on-going transfer might cause interrupts to fire, disable + // them + let interrupts = Self::get_interrupts_enable(); + self.disable_interrupts(); - dma_ch.cr().modify(|_, w| w.en().clear_bit()); - while Self::is_enabled() {} + dma_ch.cr().modify(|_, w| w.en().clear_bit()); + while Self::is_enabled() {} - self.clear_interrupts(); - self.enable_interrupts(interrupts); - } + self.clear_interrupts(); + self.enable_interrupts(interrupts); } + } - #[inline(always)] - fn set_request_line(&mut self, request_line: u8) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmamux = unsafe { &*I::mux_ptr() }; - unsafe { - dmamux.ccr($number) - .modify(|_, w| w.dmareq_id().bits(request_line)); - } + #[inline(always)] + fn set_request_line(&mut self, request_line: u8) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dmamux = unsafe { &*I::mux_ptr() }; + unsafe { + dmamux.ccr($number) + .modify(|_, w| w.dmareq_id().bits(request_line)); } + } - #[inline(always)] - fn set_priority(&mut self, priority: config::Priority) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = &unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| unsafe { w.pl().bits(priority.bits()) }); - } + #[inline(always)] + fn set_priority(&mut self, priority: config::Priority) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = &unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| unsafe { w.pl().bits(priority.bits()) }); + } - #[inline(always)] - fn disable_interrupts(&mut self) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { &*I::ptr() }.[]().cr(); - dmacr.modify(|_, w| w - .tcie().clear_bit() - .teie().clear_bit() - .htie().clear_bit()); - let _ = dmacr.read(); - let _ = dmacr.read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn disable_interrupts(&mut self) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dmacr = &unsafe { &*I::ptr() }.ch(Self::NUMBER).cr(); + dmacr.modify(|_, w| w + .tcie().clear_bit() + .teie().clear_bit() + .htie().clear_bit()); + let _ = dmacr.read(); + let _ = dmacr.read(); // Delay 2 peripheral clocks + } - #[inline(always)] - fn enable_interrupts(&mut self, interrupt: Self::Interrupts) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = &unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| w - .tcie().bit(interrupt.transfer_complete) - .teie().bit(interrupt.transfer_error) - .htie().bit(interrupt.half_transfer) - ); - } + #[inline(always)] + fn enable_interrupts(&mut self, interrupt: Self::Interrupts) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = &unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| w + .tcie().bit(interrupt.transfer_complete) + .teie().bit(interrupt.transfer_error) + .htie().bit(interrupt.half_transfer) + ); + } - #[inline(always)] - fn get_interrupts_enable() -> Self::Interrupts { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - let cr = dma_ch.cr().read(); + #[inline(always)] + fn get_interrupts_enable() -> Self::Interrupts { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + let cr = dma_ch.cr().read(); - DmaInterrupts { - transfer_complete: cr.tcie().bit_is_set(), - half_transfer: cr.htie().bit_is_set(), - transfer_error: cr.teie().bit_is_set() - } + DmaInterrupts { + transfer_complete: cr.tcie().bit_is_set(), + half_transfer: cr.htie().bit_is_set(), + transfer_error: cr.teie().bit_is_set() } + } - #[inline(always)] - fn set_transfer_complete_interrupt_enable(&mut self, transfer_complete_interrupt: bool) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { &*I::ptr() }.[]().cr(); - dmacr.modify(|_, w| w.tcie().bit(transfer_complete_interrupt)); - let _ = dmacr.read(); - let _ = dmacr.read(); // Delay 2 peripheral clocks - } - - #[inline(always)] - fn set_transfer_error_interrupt_enable(&mut self, transfer_error_interrupt: bool) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { &*I::ptr() }.[]().cr(); - dmacr.modify(|_, w| w.teie().bit(transfer_error_interrupt)); - let _ = dmacr.read(); - let _ = dmacr.read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn set_transfer_complete_interrupt_enable(&mut self, transfer_complete_interrupt: bool) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dmacr = &unsafe { &*I::ptr() }.ch(Self::NUMBER).cr(); + dmacr.modify(|_, w| w.tcie().bit(transfer_complete_interrupt)); + let _ = dmacr.read(); + let _ = dmacr.read(); // Delay 2 peripheral clocks + } - #[inline(always)] - fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { &*I::ptr() }.[]().cr(); - dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt)); - let _ = dmacr.read(); - let _ = dmacr.read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn set_transfer_error_interrupt_enable(&mut self, transfer_error_interrupt: bool) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dmacr = &unsafe { &*I::ptr() }.ch(Self::NUMBER).cr(); + dmacr.modify(|_, w| w.teie().bit(transfer_error_interrupt)); + let _ = dmacr.read(); + let _ = dmacr.read(); // Delay 2 peripheral clocks + } - #[inline(always)] - fn get_half_transfer_flag() -> bool { - //NOTE(unsafe) Atomic read with no side effects - let dma = unsafe { &*I::ptr() }; - dma.isr().read().[]().bit_is_set() - } + #[inline(always)] + fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dmacr = &unsafe { &*I::ptr() }.ch(Self::NUMBER).cr(); + dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt)); + let _ = dmacr.read(); + let _ = dmacr.read(); // Delay 2 peripheral clocks + } - #[inline(always)] - fn clear_half_transfer_interrupt(&mut self) { - //NOTE(unsafe) Atomic write with no side-effects and we only access the bits - // that belongs to the StreamX - let dma = unsafe { &*I::ptr() }; - dma.ifcr().write(|w| w.[]().set_bit()); - let _ = dma.isr().read(); - let _ = dma.isr().read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn get_half_transfer_flag() -> bool { + //NOTE(unsafe) Atomic read with no side effects + let dma = unsafe { &*I::ptr() }; + dma.isr().read().htif(Self::NUMBER as u8).bit_is_set() + } - #[inline(always)] - unsafe fn set_peripheral_address(&mut self, value: u32) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.par().write(|w| w.pa().bits(value)); - } + #[inline(always)] + fn clear_half_transfer_interrupt(&mut self) { + //NOTE(unsafe) Atomic write with no side-effects and we only access the bits + // that belongs to the StreamX + let dma = unsafe { &*I::ptr() }; + dma.ifcr().write(|w| w.chtif(Self::NUMBER as u8).set_bit()); + let _ = dma.isr().read(); + let _ = dma.isr().read(); // Delay 2 peripheral clocks + } - #[inline(always)] - unsafe fn set_memory_address(&mut self, value: u32) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.mar().write(|w| w.ma().bits(value) ); - } + #[inline(always)] + unsafe fn set_peripheral_address(&mut self, value: u32) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.par().write(|w| w.pa().bits(value)); + } - #[inline(always)] - fn get_memory_address(&self) -> u32 { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.mar().read().ma().bits() - } + #[inline(always)] + unsafe fn set_memory_address(&mut self, value: u32) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.mar().write(|w| w.ma().bits(value) ); + } - #[inline(always)] - fn set_number_of_transfers(&mut self, value: u16) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.ndtr().write(|w| unsafe {w.ndt().bits(value) }); - } + #[inline(always)] + fn get_memory_address(&self) -> u32 { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.mar().read().ma().bits() + } - #[inline(always)] - fn get_number_of_transfers() -> u16 { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.ndtr().read().ndt().bits() - } - #[inline(always)] - unsafe fn set_memory_size(&mut self, size: u8) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| w.msize().bits(size)); - } + #[inline(always)] + fn set_number_of_transfers(&mut self, value: u16) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.ndtr().write(|w| unsafe {w.ndt().bits(value) }); + } - #[inline(always)] - unsafe fn set_peripheral_size(&mut self, size: u8) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| w.psize().bits(size)); - } + #[inline(always)] + fn get_number_of_transfers() -> u16 { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.ndtr().read().ndt().bits() + } + #[inline(always)] + unsafe fn set_memory_size(&mut self, size: u8) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| w.msize().bits(size)); + } - #[inline(always)] - fn set_memory_increment(&mut self, increment: bool) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| w.minc().bit(increment)); - } + #[inline(always)] + unsafe fn set_peripheral_size(&mut self, size: u8) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| w.psize().bits(size)); + } - #[inline(always)] - fn set_peripheral_increment(&mut self, increment: bool) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| w.pinc().bit(increment)); - } + #[inline(always)] + fn set_memory_increment(&mut self, increment: bool) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| w.minc().bit(increment)); + } - #[inline(always)] - fn set_direction(&mut self, direction: DmaDirection) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| { - match direction { - DmaDirection::PeripheralToMemory => - w.dir().clear_bit().mem2mem().clear_bit(), - DmaDirection::MemoryToPeripheral => - w.dir().set_bit().mem2mem().clear_bit(), - DmaDirection::MemoryToMemory => - w.mem2mem().set_bit().dir().clear_bit(), - } - }); - } + #[inline(always)] + fn set_peripheral_increment(&mut self, increment: bool) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| w.pinc().bit(increment)); + } - #[inline(always)] - fn set_circular_buffer(&mut self, circular_buffer: bool) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dma_ch = unsafe { &*I::ptr() }.[](); - dma_ch.cr().modify(|_, w| w.circ().bit(circular_buffer)); - } + #[inline(always)] + fn set_direction(&mut self, direction: DmaDirection) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| { + match direction { + DmaDirection::PeripheralToMemory => + w.dir().clear_bit().mem2mem().clear_bit(), + DmaDirection::MemoryToPeripheral => + w.dir().set_bit().mem2mem().clear_bit(), + DmaDirection::MemoryToMemory => + w.mem2mem().set_bit().dir().clear_bit(), + } + }); } - impl $name { - #[inline(always)] - pub fn clear_half_transfer_interrupt(&mut self) { - //NOTE(unsafe) Atomic write with no side-effects and we only access the bits - // that belongs to the StreamX - let dma = unsafe { &*I::ptr() }; - dma.ifcr().write(|w| w.[]().set_bit()); - let _ = dma.isr().read(); - let _ = dma.isr().read(); // Delay 2 peripheral clocks - } + #[inline(always)] + fn set_circular_buffer(&mut self, circular_buffer: bool) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dma_ch = unsafe { &*I::ptr() }.ch(Self::NUMBER); + dma_ch.cr().modify(|_, w| w.circ().bit(circular_buffer)); + } + } + + impl $name { + #[inline(always)] + pub fn clear_half_transfer_interrupt(&mut self) { + //NOTE(unsafe) Atomic write with no side-effects and we only access the bits + // that belongs to the StreamX + let dma = unsafe { &*I::ptr() }; + dma.ifcr().write(|w| w.chtif(Self::NUMBER as u8).set_bit()); + let _ = dma.isr().read(); + let _ = dma.isr().read(); // Delay 2 peripheral clocks + } - #[inline(always)] - pub fn get_half_transfer_flag() -> bool { - //NOTE(unsafe) Atomic read with no side effects - let dma = unsafe { &*I::ptr() }; - dma.isr().read().[]().bit_is_set() - } + #[inline(always)] + pub fn get_half_transfer_flag() -> bool { + //NOTE(unsafe) Atomic read with no side effects + let dma = unsafe { &*I::ptr() }; + dma.isr().read().htif(Self::NUMBER as u8).bit_is_set() + } - #[inline(always)] - pub fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) { - //NOTE(unsafe) We only access the registers that belongs to the StreamX - let dmacr = &unsafe { &*I::ptr() }.[]().cr(); - dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt)); - let _ = dmacr.read(); - let _ = dmacr.read(); // Delay 2 peripheral clocks - } + #[inline(always)] + pub fn set_half_transfer_interrupt_enable(&mut self, half_transfer_interrupt: bool) { + //NOTE(unsafe) We only access the registers that belongs to the StreamX + let dmacr = &unsafe { &*I::ptr() }.ch(Self::NUMBER).cr(); + dmacr.modify(|_, w| w.htie().bit(half_transfer_interrupt)); + let _ = dmacr.read(); + let _ = dmacr.read(); // Delay 2 peripheral clocks } - )+ - } + } + )+ }; }