diff --git a/src/jtag.v b/src/jtag.v
index e44a619..c7cd1e3 100644
--- a/src/jtag.v
+++ b/src/jtag.v
@@ -161,31 +161,33 @@ module jtag (
             default: current_state <= ShiftIr;
           endcase
         end
-        ShiftDr:  // 6
-        // in the Shift-DR state, this data is shifted out, least significant bit first
-        // Pretty sure this means connect a shift register to TDO and drain it
-        case (tms)
-          1: current_state <= Exit1Dr;
-          default: begin
-            case (current_ir_instruction)
-              IdCode: begin
-                // place the byte transmitter with the IDCODE register and start to shift it onto TDO. 
-                r_output_selector_transmitter <= 0;
-                byte_transmitter_enable <= 1;
-                if (!idcode_out_done) begin
+        ShiftDr: begin  // 6
+          tap_channel <= 0;
+          // in the Shift-DR state, this data is shifted out, least significant bit first
+          // Pretty sure this means connect a shift register to TDO and drain it
+          case (tms)
+            1: current_state <= Exit1Dr;
+            default: begin
+              case (current_ir_instruction)
+                IdCode: begin
+                  // place the byte transmitter with the IDCODE register and start to shift it onto TDO. 
+                  r_output_selector_transmitter <= 0;
+                  byte_transmitter_enable <= 1;
+                  if (!idcode_out_done) begin
+                    current_state <= ShiftDr;
+                  end else begin
+                    byte_transmitter_enable <= 0;
+                    current_state <= Exit1Dr;  // Not sure if this is correct.
+                  end
+                end
+                default: begin
+                  current_ir_instruction_broken <= 1;
                   current_state <= ShiftDr;
-                end else begin
-                  byte_transmitter_enable <= 0;
-                  current_state <= Exit1Dr;  // Not sure if this is correct.
                 end
-              end
-              default: begin
-                current_ir_instruction_broken <= 1;
-                current_state <= ShiftDr;
-              end
-            endcase
-          end
-        endcase
+              endcase
+            end
+          endcase
+        end
         ShiftIr: begin  // 7
           tap_channel <= 0;
           case (tms)
diff --git a/test/test.py b/test/test.py
index 269b219..2e89ffb 100644
--- a/test/test.py
+++ b/test/test.py
@@ -42,10 +42,6 @@ async def test_tms_five_high_for_reset(dut):
         await ClockCycles(dut.clk, 1)
         assert dut.uo_out.value == 0x0
 
-        assert dut.uo_out.value == 0x0
-
-        # Drive TCK high/low enough times to see 0xFAF01
-
         # Drive TMS high then low for five cycles to put us into reset.
         dut._log.info("TMS high for five pulses to reset TAP controller")
         dut.ui_in.value = 0b0000_1111