diff --git a/gate_tests.sh b/gate_tests.sh
new file mode 100755
index 0000000..1087625
--- /dev/null
+++ b/gate_tests.sh
@@ -0,0 +1,5 @@
+cd test
+pip install -r requirements.txt
+TOP_MODULE=$(cd .. && ./tt/tt_tool.py --print-top-module)
+cp ../runs/wokwi/final/pnl/$TOP_MODULE.pnl.v gate_level_netlist.v
+make -B GATES=yes
diff --git a/src/byte_transmitter.v b/src/byte_transmitter.v
index 2f2cdec..d1b90d1 100644
--- a/src/byte_transmitter.v
+++ b/src/byte_transmitter.v
@@ -67,11 +67,13 @@ module byte_transmitter (
       assert (f_total_written == 32);  // We've drained the entire buffer.
       assert (byte_count == 0);
       assert (r_out != 1'bX);
+      assert (done != 1'bX);
     end
 
     if (f_past_valid && enable && byte_count == 0) begin
-      assert (done);
       assert (f_total_written == 32);
+      assert (done);
+      assert (r_out != 1'bX);
     end
   end
 
diff --git a/src/jtag.v b/src/jtag.v
index 825aaa2..8a0d3d2 100644
--- a/src/jtag.v
+++ b/src/jtag.v
@@ -14,13 +14,12 @@
   end;
 
 module jtag (
-    input tck,
+    input  wire tck,
     /* verilator lint_off UNUSED */
-    input wire tdi,
+    input  wire tdi,
     output wire tdo,
-    input wire tms,
-    input wire trst_n,
-    input wire reset  // comes from main domain clock.
+    input  wire tms,
+    input  wire trst_n
 );
 
   wire trst;
@@ -70,13 +69,14 @@ module jtag (
   reg byte_transmitter_enable;
   reg reset_byte_transmitter;
   wire transmitter_channel;  // for byte_transmitter to write to TDO
+  reg r_transmitter_channel;
 
   byte_transmitter id_byte_transmitter (
       .clk(tck),
       .reset(trst | reset_byte_transmitter),  // TODO: We need to be able to reset the byte_counter?
       .enable(byte_transmitter_enable),
       .in(IdCodeDrRegister),
-      .out(transmitter_channel),  // make this another wire.
+      .out(r_transmitter_channel),  // make this another wire.
       .done(idcode_out_done)
   );
 
@@ -110,6 +110,7 @@ module jtag (
       current_ir_instruction <= 4'b1110;  // IDCODE is the default instruction.
       r_output_selector_transmitter <= 1;  // by default the tap controller writes
       tap_channel <= 0;  // How can an X sneak in here?
+      r_transmitter_channel <= 0;
       byte_transmitter_enable <= 0;
       reset_byte_transmitter <= 0;
     end else begin
@@ -282,7 +283,7 @@ module jtag (
 
     if (f_past_valid && $past(trst_n)) begin
       assume (trst);
-      assert (current_state != 1'bX);
+      assert (current_state != 5'bX_XXXX);
       assert (r_output_selector_transmitter != 1'bX);
       assert (tdo != 1'bX);
     end
diff --git a/src/mux_2_1.v b/src/mux_2_1.v
index 6d07c0b..e1c7d4b 100644
--- a/src/mux_2_1.v
+++ b/src/mux_2_1.v
@@ -4,10 +4,10 @@
 `default_nettype none
 
 module mux_2_1 (
-    input  one,
-    input  two,
-    input  selector,
-    output out
+    input  wire one,
+    input  wire two,
+    input  wire selector,
+    output wire out
 );
 
   assign out = (selector) ? one : two;
diff --git a/src/project.v b/src/project.v
index 2f63878..89138fe 100644
--- a/src/project.v
+++ b/src/project.v
@@ -45,8 +45,7 @@ module tt_um_jtag_example_stevej (
       .tdi(ui_in[1]),
       .tms(ui_in[2]),
       .trst_n(ui_in[3]),
-      .tdo(tdo),
-      .reset(reset)
+      .tdo(tdo)
   );
 
   // A hard configured interrupt rising high every 10 cycles for 1 cycle.
diff --git a/test/test.py b/test/test.py
index 2e89ffb..7e7fc03 100644
--- a/test/test.py
+++ b/test/test.py
@@ -27,8 +27,8 @@ async def test_tms_five_high_for_reset(dut):
         dut.rst_n.value = 0
         await ClockCycles(dut.clk, 1)
         dut.rst_n.value = 1
-        dut.ui_in.value = 0b0000_1000
-        await ClockCycles(dut.clk, 1)
+        #dut.ui_in.value = 0b0000_1000
+        #await ClockCycles(dut.clk, 1)
 
         # Drive TRST low and TCK high then low to reset tap controller
         dut._log.info("Reset the jtag tap controller")