diff --git a/src/test.py b/src/test.py index 9258198..c66c782 100644 --- a/src/test.py +++ b/src/test.py @@ -40,10 +40,49 @@ async def test_one_shot(dut): await ClockCycles(dut.clk, 2) dut.uio_in.value = 0xA0 # set we high and config_address to 0b10 - dut.ui_in.value = 0x10 + dut.ui_in.value = 0x0A await ClockCycles(dut.clk, 10) dut.uio_in.value = 0x0 # unset we so we no longer configure registers. await ClockCycles(dut.clk, 10) dut._log.info("checking that interrupt is high") assert dut.uo_out.value == 0b01000000 + + +@cocotb.test() +async def repeating_no_divider(dut): + + dut._log.info("start") + clock = Clock(dut.clk, 10, units="us") + cocotb.start_soon(clock.start()) + + # reset + dut._log.info("reset") + dut.rst_n.value = 0 + await ClockCycles(dut.clk, 2) + + dut.rst_n.value = 1 + # set WE high, config_address to 0b00 + dut.uio_in.value = 0b1000_0000 + # divider off, repeat on. + dut.ui_in.value = 0b0100_0000 + # TODO: set repeating on in the payload + await ClockCycles(dut.clk, 1) + dut.uio_in.value = 0x01 + dut.ui_in.value = 0x00 + # set WE high and config_address to 0b01 + dut.uio_in.value = 0xC0 + dut.ui_in.value = 0x00 # should not set temp_counter + await ClockCycles(dut.clk, 2) + + dut.uio_in.value = 0xA0 # set we high and config_address to 0b10 + dut.ui_in.value = 0x0A + await ClockCycles(dut.clk, 10) + dut._log.info("checking that interrupt is high") + assert dut.uo_out.value == 0b01000000 + + dut.uio_in.value = 0x0 # unset we so we no longer configure registers. + await ClockCycles(dut.clk, 10) + dut._log.info("checking that interrupt is high") + assert dut.uo_out.value == 0b01000000 + await ClockCycles(dut.clk, 10) diff --git a/src/tt_um_minipit_stevej.v b/src/tt_um_minipit_stevej.v index 5709320..5e1b68e 100644 --- a/src/tt_um_minipit_stevej.v +++ b/src/tt_um_minipit_stevej.v @@ -92,6 +92,9 @@ module tt_um_minipit_stevej ( if (counter_set && (current_count == counter)) begin // pull interrupt line high for one clock cycle interrupting <= 1; + if (repeating) begin + current_count <= 0; + end end else begin interrupting <= 0; end