From 42646eab787993f0295bf841cdb67bc6280f4d4c Mon Sep 17 00:00:00 2001
From: Steve Jenson <stevej@gmail.com>
Date: Thu, 2 Nov 2023 11:46:07 -0700
Subject: [PATCH] adding back load-bearing empty module

---
 src/Makefile  | 2 +-
 src/minipit.v | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)
 create mode 100644 src/minipit.v

diff --git a/src/Makefile b/src/Makefile
index a908e50..ab4340e 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -9,7 +9,7 @@ TOPLEVEL_LANG ?= verilog
 ifneq ($(GATES),yes)
 
 # this is the only part you should need to modify:
-VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_minipit_stevej.v
+VERILOG_SOURCES += $(PWD)/tb.v $(PWD)/tt_um_minipit_stevej.v $(PWD)/minipit.v
 
 else
 
diff --git a/src/minipit.v b/src/minipit.v
new file mode 100644
index 0000000..8d8ece8
--- /dev/null
+++ b/src/minipit.v
@@ -0,0 +1,9 @@
+`default_nettype none
+`timescale 1ns/1ps
+
+
+module minipit();
+
+
+
+endmodule