Note: Chipathon 2024 contributions will be made directly to the OpenFASOC/GLAYOUT Repository using the layout automation tool - GLayout. Final Generators and Tapeout-ready designs will be pushed to this repo with their final simulations results.
| Date | Topics | Presenters | Pre-meeting Assignments | Slides |
|---|---|---|---|---|
| 6/6/2024 | Meetup kick-off | Boris Murmann, Mehdi Saligane | Slides and Recording | |
| 6/13/2024 | Session on tools installation | Sakib Pathen, Arlene Dai, Chetanya Goyal, Mehdi Saligane | Play with Notebooks, Go through the installation and GLayout Doc | Slides and Recording |
| 6/20/2024 | Intro to GLayout + Addressing remaining installation issues | Sakib Pathen, Arlene Dai, Chetanya Goyal, Kwantae Kim, Mehdi Saligane | Kwantae's blog, Running GLayout example in CLI, Poke around the openfasoc repo | Slides and Recording |
| 6/27/2024 | Intro to GLayout + Examples | Sakib Pathen, Arlene Dai, Chetanya Goyal, Mehdi Saligane | Review previous meeting | Slides and Recording |
| 7/4/2024 | Break | Vacation | NA | NA |
| 7/11/2024 | 50 nifty Transistors - Intro | Harald Pretl | Going through basic analog components | Slides and Recording |
| 7/18/2024 | Main Topic: Creating Components | Mehdi Saligane | Learn how to build your own cells | Slides and Recording |
| 7/25/2024 | Sizing Simple Circuits - 50 Nifty + Teaming up | Boris Murmann | Review Preview Meetings | Slides and Recording |
| 8/1/2024 | Sizing Simple Circuits - Blocks | Boris Murmann | Learn how to size your circuit - Fundamentals | Slides and Recording |
| 8/8/2024 | Main Topic: DRC and LVS Checks | Mitch Bailey | Review Layout Verification tools | Slides and Recording |
| 8/15/2024 | Main Topic: Verification | Tim Edwards | Review Simulation Tools and CACE | Slides and Recording |
| 8/22/2024 | Projects Presentations I | Participants | Prepare Demo, notebook and Presentation | Slides and Recording |
| 8/29/2024 | Projects Presentations II | Participants | Prepare Demo, notebook and Presentation | Recording |
| 9/5/2024 | Projects Presentations III | Participants | Prepare Demo, notebook and Presentation | Recording |
| 9/12/2024 | Projects Presentations IV | Participants | Prepare Demo, notebook and Presentation | Link |
For links to the slides of individual presentations, see the Groups sheet on GLayout Components Plan - Chipathon 2024
- Glayout Installation Guide
- Glayout Introduction Guide
- Glayout Videos (links to the OpenFASOC youtube, all introductory videos can be found here)
- Prospective PCells
- Pcell Notebooks
The IEEE Solid-State Circuits Society is pleased to announce its third open-source integrated circuit (IC) design contest under the umbrella of its PICO Program (Platform for IC Design Outreach). While this contest is open to any individual or team, we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community.
We have a detailed installation guide here. This guide will help you set up the following:
- A python environment (version
$\ge$ 3.10) - Conda packages with python 3.10
a. Magic
b. Netgen
c. Yosys
c. OpenROAD
d. Open PDKs (GF180MCU and SKY130)
e. NGSpice
f. Klayout
Note: To test your installation, there is a script called test_glayout.py in the openfasoc/generators/glayout. Run this script to check if all the tools are installed correctly.
A detailed introduction to Glayout and its codebase can be found here. It is recommended that all contributors read through the document to learn how to create pcells.
Some examples of pcells, with their generated layouts have been shown below (refer to the links to see PCell code or Notebooks).
- Via
The notebook demonstrates how to place a rectangular via by using specified metal layers. This is the simplest pcell and a must know.
- Current Mirror
The notebook linked goes over the placement, movement and routing of 2 transistor current mirror.
- Opamp
This cell linked creates a two stage Operational Amplifier + an nfet output stage. The opamp uses a differential to single ended converter and a pmos load with miller compensation as the first two stages. A coaxial driver is also connected.
