From 68031a91ef5527b85dde86e0488db7bc8d8ad936 Mon Sep 17 00:00:00 2001
From: Amin Abdulrahman <amin@abdulrahman.de>
Date: Wed, 27 Nov 2024 11:32:25 +0100
Subject: [PATCH 1/5] Add Armv7m Arch and CM7 uArch models

---
 example.py                                  |   58 +
 examples/naive/armv7m/armv7m_simple0.s      |    9 +
 examples/naive/armv7m/loop_cmp.s            |   10 +
 examples/naive/armv7m/loop_subs.s           |    4 +
 examples/opt/armv7m/armv7m_simple0_opt_m7.s |   33 +
 examples/opt/armv7m/loop_cmp_opt_m7.s       |   29 +
 examples/opt/armv7m/loop_subs_opt_m7.s      |   11 +
 slothy/targets/arm_v7m/arch_v7m.py          | 1882 +++++++++++++++++++
 slothy/targets/arm_v7m/cortex_m4.py         |   75 +
 slothy/targets/arm_v7m/cortex_m7.py         |  353 ++++
 slothy/targets/query.py                     |    7 +-
 11 files changed, 2470 insertions(+), 1 deletion(-)
 create mode 100644 examples/naive/armv7m/armv7m_simple0.s
 create mode 100644 examples/naive/armv7m/loop_cmp.s
 create mode 100644 examples/naive/armv7m/loop_subs.s
 create mode 100644 examples/opt/armv7m/armv7m_simple0_opt_m7.s
 create mode 100644 examples/opt/armv7m/loop_cmp_opt_m7.s
 create mode 100644 examples/opt/armv7m/loop_subs_opt_m7.s
 create mode 100644 slothy/targets/arm_v7m/arch_v7m.py
 create mode 100644 slothy/targets/arm_v7m/cortex_m4.py
 create mode 100644 slothy/targets/arm_v7m/cortex_m7.py

diff --git a/example.py b/example.py
index 89a295d6..6e38f856 100644
--- a/example.py
+++ b/example.py
@@ -31,7 +31,9 @@
 
 from slothy import Slothy, Config
 
+import slothy.targets.arm_v7m.arch_v7m as Arch_Armv7M
 import slothy.targets.arm_v81m.arch_v81m as Arch_Armv81M
+import slothy.targets.arm_v7m.cortex_m7 as Target_CortexM7
 import slothy.targets.arm_v81m.cortex_m55r1 as Target_CortexM55r1
 import slothy.targets.arm_v81m.cortex_m85r1 as Target_CortexM85r1
 
@@ -43,6 +45,7 @@
 
 target_label_dict = {Target_CortexA55: "a55",
                      Target_CortexA72: "a72",
+                     Target_CortexM7: "m7",
                      Target_CortexM55r1: "m55",
                      Target_CortexM85r1: "m85",
                      Target_AppleM1_firestorm: "m1_firestorm",
@@ -76,6 +79,8 @@ def __init__(self, infile, name=None, funcname=None, suffix="opt",
         subfolder = ""
         if self.arch == AArch64_Neon:
             subfolder = "aarch64/"
+        elif self.arch == Arch_Armv7M:
+            subfolder = "armv7m/"
         self.infile_full = f"examples/naive/{subfolder}{self.infile}.s"
         self.outfile_full = f"examples/opt/{subfolder}{self.outfile}.s"
         self.name = name
@@ -634,7 +639,55 @@ def core(self,slothy):
         slothy.config.sw_pipelining.optimize_postamble = False
         slothy.optimize_loop("start")
 
+class Armv7mExample0(Example):
+    def __init__(self, var="", arch=Arch_Armv7M, target=Target_CortexM7):
+        name = "armv7m_simple0"
+        infile = name
+
+        if var != "":
+            name += f"_{var}"
+            infile += f"_{var}"
+        name += f"_{target_label_dict[target]}"
+
+        super().__init__(infile, name, rename=True, arch=arch, target=target)
+
+    def core(self,slothy):
+        slothy.config.variable_size=True
+        slothy.config.inputs_are_outputs = True
+        slothy.optimize(start="start", end="end")
+
+class Armv7mLoopSubs(Example):
+    def __init__(self, var="", arch=Arch_Armv7M, target=Target_CortexM7):
+        name = "loop_subs"
+        infile = name
 
+        if var != "":
+            name += f"_{var}"
+            infile += f"_{var}"
+        name += f"_{target_label_dict[target]}"
+
+        super().__init__(infile, name, rename=True, arch=arch, target=target)
+
+    def core(self,slothy):
+        slothy.config.variable_size=True
+        slothy.optimize_loop("start")
+
+class Armv7mLoopCmp(Example):
+    def __init__(self, var="", arch=Arch_Armv7M, target=Target_CortexM7):
+        name = "loop_cmp"
+        infile = name
+
+        if var != "":
+            name += f"_{var}"
+            infile += f"_{var}"
+        name += f"_{target_label_dict[target]}"
+
+        super().__init__(infile, name, rename=True, arch=arch, target=target)
+
+    def core(self,slothy):
+        slothy.config.variable_size=True
+        slothy.config.outputs = ["r6"]
+        slothy.optimize_loop("start")
 
 class ntt_kyber_123_4567(Example):
     def __init__(self, var="", arch=AArch64_Neon, target=Target_CortexA55, timeout=None):
@@ -1425,9 +1478,14 @@ def main():
                  AArch64Example2(),
                  AArch64Example2(target=Target_CortexA72),
 
+                # Armv7m examples
+                 Armv7mExample0(),
+
                 # Loop examples
                  AArch64LoopSubs(),
                  LoopLe(),
+                 Armv7mLoopSubs(),
+                 Armv7mLoopCmp(),
 
                  CRT(),
 
diff --git a/examples/naive/armv7m/armv7m_simple0.s b/examples/naive/armv7m/armv7m_simple0.s
new file mode 100644
index 00000000..1b3e77c4
--- /dev/null
+++ b/examples/naive/armv7m/armv7m_simple0.s
@@ -0,0 +1,9 @@
+
+start:
+ldr r1, [r0, #4]
+add r1, r2, r1
+eor.w r1, r1, r3
+smlabt r3, r2, r2, r1
+asrs r3, r3, #1
+str r3, [r0, #4]
+end:
\ No newline at end of file
diff --git a/examples/naive/armv7m/loop_cmp.s b/examples/naive/armv7m/loop_cmp.s
new file mode 100644
index 00000000..be8d09a7
--- /dev/null
+++ b/examples/naive/armv7m/loop_cmp.s
@@ -0,0 +1,10 @@
+/* For example, r5 represents an address where we will stop iterating and r6 is
+the actual pointer which is incremented inside the loop. */
+
+mov.w r6, #0
+add.w r5, r6, #64
+
+start:
+    add r6, r6, #4
+    cmp.w r6, r5
+    bne.w start
\ No newline at end of file
diff --git a/examples/naive/armv7m/loop_subs.s b/examples/naive/armv7m/loop_subs.s
new file mode 100644
index 00000000..5dd05c9c
--- /dev/null
+++ b/examples/naive/armv7m/loop_subs.s
@@ -0,0 +1,4 @@
+movw r5, #16
+start:
+    subs.w r5, #1
+    bne.w start
\ No newline at end of file
diff --git a/examples/opt/armv7m/armv7m_simple0_opt_m7.s b/examples/opt/armv7m/armv7m_simple0_opt_m7.s
new file mode 100644
index 00000000..87fd5e61
--- /dev/null
+++ b/examples/opt/armv7m/armv7m_simple0_opt_m7.s
@@ -0,0 +1,33 @@
+
+        start:
+                                       // Instructions:    6
+                                       // Expected cycles: 5
+                                       // Expected IPC:    1.20
+                                       //
+                                       // Cycle bound:     5.0
+                                       // IPC bound:       1.20
+                                       //
+                                       // Wall time:     0.01s
+                                       // User time:     0.01s
+                                       //
+                                       // ----- cycle (expected) ------>
+                                       // 0                        25
+                                       // |------------------------|----
+        ldr r7, [r0, #4]               // *.............................
+        add r7, r2, r7                 // .*............................
+        eor.w r12, r7, r3              // ..*...........................
+        smlabt r12, r2, r2, r12        // ..*...........................
+        asrs r3, r12, #1               // ....*.........................
+        str r3, [r0, #4]               // ....*.........................
+
+                                      // ------ cycle (expected) ------>
+                                      // 0                        25
+                                      // |------------------------|-----
+        // ldr r1, [r0, #4]           // *..............................
+        // add r1, r2, r1             // .*.............................
+        // eor.w r1, r1, r3           // ..*............................
+        // smlabt r3, r2, r2, r1      // ..*............................
+        // asrs r3, r3, #1            // ....*..........................
+        // str r3, [r0, #4]           // ....*..........................
+
+        end:
diff --git a/examples/opt/armv7m/loop_cmp_opt_m7.s b/examples/opt/armv7m/loop_cmp_opt_m7.s
new file mode 100644
index 00000000..4524a7e2
--- /dev/null
+++ b/examples/opt/armv7m/loop_cmp_opt_m7.s
@@ -0,0 +1,29 @@
+/* For example, r5 represents an address where we will stop iterating and r6 is
+the actual pointer which is incremented inside the loop. */
+
+mov.w r6, #0
+add.w r5, r6, #64
+
+1:
+                              // Instructions:    1
+                              // Expected cycles: 1
+                              // Expected IPC:    1.00
+                              //
+                              // Cycle bound:     1.0
+                              // IPC bound:       1.00
+                              //
+                              // Wall time:     0.02s
+                              // User time:     0.02s
+                              //
+                              // ----- cycle (expected) ------>
+                              // 0                        25
+                              // |------------------------|----
+        add r6, r6, #4        // *.............................
+
+                               // ------ cycle (expected) ------>
+                               // 0                        25
+                               // |------------------------|-----
+        // add r6, r6, #4      // *..............................
+
+        cmp r6, r5
+        bne 1b
\ No newline at end of file
diff --git a/examples/opt/armv7m/loop_subs_opt_m7.s b/examples/opt/armv7m/loop_subs_opt_m7.s
new file mode 100644
index 00000000..f1bcc451
--- /dev/null
+++ b/examples/opt/armv7m/loop_subs_opt_m7.s
@@ -0,0 +1,11 @@
+movw r5, #16
+start:
+                // Instructions:    0
+                // Expected cycles: 0
+                // Expected IPC:    0.00
+                //
+                // Wall time:     0.00s
+                // User time:     0.00s
+                //
+        subs r5, #1
+        bne start
\ No newline at end of file
diff --git a/slothy/targets/arm_v7m/arch_v7m.py b/slothy/targets/arm_v7m/arch_v7m.py
new file mode 100644
index 00000000..43154983
--- /dev/null
+++ b/slothy/targets/arm_v7m/arch_v7m.py
@@ -0,0 +1,1882 @@
+import logging
+import inspect
+import re
+import math
+from enum import Enum
+from functools import cache
+
+from slothy.helper import SourceLine, Loop
+from sympy import simplify
+
+llvm_mca_arch = "arm"  # TODO
+
+
+class RegisterType(Enum):
+    GPR = 1
+    FPR = 2
+    STACK_FPR = 3
+    STACK_GPR = 4
+    FLAGS = 5
+    HINT = 6
+
+    def __str__(self):
+        return self.name
+    def __repr__(self):
+        return self.name
+
+    @cache
+    @staticmethod
+    def spillable(reg_type):
+        return reg_type in [RegisterType.GPR]
+
+    @cache
+    @staticmethod
+    def list_registers(reg_type, only_extra=False, only_normal=False, with_variants=False):
+        """Return the list of all registers of a given type"""
+
+        stack_locations  = [ f"STACK{i}"  for i in range(8) ]
+        fpstack_locations  = [ f"STACK{i}"  for i in range(8) ]
+
+        gprs_normal  = [ f"r{i}" for i in range(15) ]
+        fprs_normal  = [ f"s{i}" for i in range(31) ]
+
+        gprs_extra  = []
+        fprs_extra  = []
+
+        gprs  = []
+        fprs  = []
+        # TODO: What are hints?
+        hints = [ f"t{i}" for i in range(100) ] + \
+                [ f"t{i}{j}" for i in range(8) for j in range(8) ] + \
+                [ f"t{i}_{j}" for i in range(16) for j in range(16) ]
+
+        flags = ["flags"]
+        if not only_extra:
+            gprs  += gprs_normal
+            fprs += fprs_normal
+        if not only_normal:
+            gprs  += gprs_extra
+            fprs += fprs_extra
+
+        return { RegisterType.GPR       : gprs,
+                 RegisterType.STACK_GPR : stack_locations,
+                 RegisterType.FPR       : fprs,
+                 RegisterType.STACK_FPR : fpstack_locations,
+                 RegisterType.HINT      : hints,
+                 RegisterType.FLAGS     : flags}[reg_type]
+
+    @staticmethod
+    def find_type(r):
+        """Find type of architectural register"""
+
+        if r.startswith("hint_"):
+            return RegisterType.HINT
+
+        for ty in RegisterType:
+            if r in RegisterType.list_registers(ty):
+                return ty
+
+        return None
+
+    @staticmethod
+    def is_renamed(ty):
+        """Indicate if register type should be subject to renaming"""
+        if ty == RegisterType.HINT:
+            return False
+        return True
+
+    @staticmethod
+    def from_string(string):
+        """Find registe type from string"""
+        string = string.lower()
+        return { "fprstack"    : RegisterType.STACK_FPR,
+                 "stack"     : RegisterType.STACK_GPR,
+                 "fpr"      : RegisterType.FPR,
+                 "gpr"       : RegisterType.GPR,
+                 "hint"      : RegisterType.HINT,
+                 "flags"     : RegisterType.FLAGS}.get(string,None)
+
+    @staticmethod
+    def default_reserved():
+        """Return the list of registers that should be reserved by default"""
+        # r13 is the stack pointer
+        return set(["flags", "r13"] + RegisterType.list_registers(RegisterType.HINT))
+
+    @staticmethod
+    def default_aliases():
+        "Register aliases used by the architecture"
+        return {
+                 "lr": "r14",
+                }
+
+# TODO: Comparison can also be done with {add,sub,...}s
+class Branch:
+    """Helper for emitting branches"""
+
+    @staticmethod
+    def if_equal(cnt, val, lbl):
+        """Emit assembly for a branch-if-equal sequence"""
+        yield f"cmp {cnt}, #{val}"
+        yield f"beq {lbl}"
+
+    @staticmethod
+    def if_greater_equal(cnt, val, lbl):
+        """Emit assembly for a branch-if-greater-equal sequence"""
+        yield f"cmp {cnt}, #{val}"
+        yield f"bge {lbl}"
+
+    @staticmethod
+    def unconditional(lbl):
+        """Emit unconditional branch"""
+        yield f"b {lbl}"
+
+
+class VmovCmpLoop(Loop):
+    def __init__(self, lbl="lbl", lbl_start="1", lbl_end="2", loop_init="lr") -> None:
+        super().__init__(lbl_start=lbl_start, lbl_end=lbl_end, loop_init=loop_init)
+        self.lbl = lbl
+        self.lbl_regex = r"^\s*(?P<label>\w+)\s*:(?P<remainder>.*)$"
+        self.end_regex = (r"^\s*vmov(?:\.w)?\s+(?P<end>\w+),\s*(?P<endf>\w+)",
+                          r"^\s*cmp(?:\.w)?\s+(?P<cnt>\w+),\s*(?P<end>\w+)",
+                               rf"^\s*(cbnz|cbz|bne)(?:\.w)?\s+{lbl}")
+
+    def start(self, loop_cnt, indentation=0, fixup=0, unroll=1, jump_if_empty=None, preamble_code=None, body_code=None, postamble_code=None, register_aliases=None):
+        """Emit starting instruction(s) and jump label for loop"""
+        indent = ' ' * indentation
+        if unroll > 1:
+            assert unroll in [1,2,4,8,16,32]
+            yield f"{indent}lsr {self.additional_data['end']}, {self.additional_data['end']}, #{int(math.log2(unroll))}"
+
+        # Find out by how much the loop counter is modified in one iteration
+        inc_per_iter = 0
+        if body_code is not None:
+            try:
+                loop_cnt_reg = register_aliases[loop_cnt]
+            except KeyError:
+                loop_cnt_reg = loop_cnt
+            for l in body_code:
+                if l.text == "":
+                    continue
+                inst = Instruction.parser(l)
+                if loop_cnt_reg.lower() == inst[0].addr and inst[0].increment is not None:
+                    inc_per_iter = inc_per_iter + simplify(inst[0].increment)
+        logging.debug(f"Loop counter {loop_cnt} is incremented by {inc_per_iter} per iteration")
+        # Check whether instructions modifying the loop count moved to
+        # pre/postamble and adjust the fixup based on that.
+        new_fixup = 0
+        if postamble_code is not None:
+            new_fixup = 0
+            for l in postamble_code:
+                if l.text == "":
+                    continue
+                inst = Instruction.parser(l)
+                if loop_cnt in inst[0].args_in_out and inst[0].increment is not None:
+                    new_fixup = new_fixup + simplify(inst[0].increment)
+
+        if new_fixup != 0 or fixup != 0:
+            yield f"{indent}push {{{self.additional_data['end']}}}"
+            yield f"{indent}vmov {self.additional_data['end']}, {self.additional_data['endf']}"
+
+        if new_fixup != 0:
+            yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{new_fixup}"
+        if fixup != 0:
+            yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{fixup*inc_per_iter}"
+        if new_fixup != 0 or fixup != 0:
+            yield f"{indent}vmov {self.additional_data['endf']}, {self.additional_data['end']}"
+            yield f"{indent}pop {{{self.additional_data['end']}}}"
+        if jump_if_empty is not None:
+            yield f"cbz {loop_cnt}, {jump_if_empty}"
+        yield f"{self.lbl}:"
+
+    def end(self, other, indentation=0):
+        """Emit compare-and-branch at the end of the loop"""
+        indent = ' ' * indentation
+        lbl_start = self.lbl
+        if lbl_start.isdigit():
+            lbl_start += "b"
+
+        yield f'{indent}vmov {other["end"]}, {other["endf"]}'
+        yield f'{indent}cmp {other["cnt"]}, {other["end"]}'
+        yield f'{indent}bne {lbl_start}'
+
+class CmpLoop(Loop):
+    def __init__(self, lbl="lbl", lbl_start="1", lbl_end="2", loop_init="lr") -> None:
+        super().__init__(lbl_start=lbl_start, lbl_end=lbl_end, loop_init=loop_init)
+        self.lbl_regex = r"^\s*(?P<label>\w+)\s*:(?P<remainder>.*)$"
+        self.end_regex = (r"^\s*cmp(?:\.w)?\s+(?P<cnt>\w+),\s*(?P<end>\w+)",
+                               rf"^\s*(cbnz|cbz|bne)(?:\.w)?\s+{lbl}")
+
+    def start(self, loop_cnt, indentation=0, fixup=0, unroll=1, jump_if_empty=None, preamble_code=None, body_code=None, postamble_code=None, register_aliases=None):
+        """Emit starting instruction(s) and jump label for loop"""
+        indent = ' ' * indentation
+        if unroll > 1:
+            assert unroll in [1,2,4,8,16,32]
+            yield f"{indent}lsr {self.additional_data['end']}, {self.additional_data['end']}, #{int(math.log2(unroll))}"
+
+        # Find out by how much the loop counter is modified in one iteration
+        inc_per_iter = 0
+        if body_code is not None:
+            try:
+                loop_cnt_reg = register_aliases[loop_cnt]
+            except KeyError:
+                loop_cnt_reg = loop_cnt
+            for l in body_code:
+                if l.text == "":
+                    continue
+                inst = Instruction.parser(l)
+                if loop_cnt_reg.lower() == inst[0].addr and inst[0].increment is not None:
+                    inc_per_iter = inc_per_iter + simplify(inst[0].increment)
+        logging.debug(f"Loop counter {loop_cnt} is incremented by {inc_per_iter} per iteration")
+
+        # Check whether instructions modifying the loop count moved to
+        # pre/postamble and adjust the fixup based on that.
+        new_fixup = 0
+        if postamble_code is not None:
+            new_fixup = 0
+            for l in postamble_code:
+                if l.text == "":
+                    continue
+                inst = Instruction.parser(l)
+                if loop_cnt in inst[0].args_in_out and inst[0].increment is not None:
+                    new_fixup = new_fixup + simplify(inst[0].increment)
+
+        if new_fixup != 0:
+            yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{new_fixup}"
+
+        if fixup != 0:
+            yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{fixup*inc_per_iter}"
+
+        if jump_if_empty is not None:
+            yield f"cbz {loop_cnt}, {jump_if_empty}"
+        yield f"{self.lbl_start}:"
+
+    def end(self, other, indentation=0):
+        """Emit compare-and-branch at the end of the loop"""
+        indent = ' ' * indentation
+        lbl_start = self.lbl_start
+        if lbl_start.isdigit():
+            lbl_start += "b"
+
+        yield f'{indent}cmp {other["cnt"]}, {other["end"]}'
+        yield f'{indent}bne {lbl_start}'
+
+class SubsLoop(Loop):
+    def __init__(self, lbl_start="1", lbl_end="2", loop_init="lr") -> None:
+        super().__init__(lbl_start=lbl_start, lbl_end=lbl_end, loop_init=loop_init)
+        self.lbl_regex = r"^\s*(?P<label>\w+)\s*:(?P<remainder>.*)$"
+        self.end_regex = (r"^\s*sub[s]?(?:\.w)?\s+(?P<cnt>\w+),(?:\s*(?P<reg1>\w+),)?\s*(?P<imm>#1)",
+                               rf"^\s*(cbnz|cbz|bne)(?:\.w)?\s+{lbl_start}")
+
+    def start(self, loop_cnt, indentation=0, fixup=0, unroll=1, jump_if_empty=None, preamble_code=None, body_code=None, postamble_code=None, register_aliases=None):
+        """Emit starting instruction(s) and jump label for loop"""
+        indent = ' ' * indentation
+        if unroll > 1:
+            assert unroll in [1,2,4,8,16,32]
+            yield f"{indent}lsr {loop_cnt}, {loop_cnt}, #{int(math.log2(unroll))}"
+        if fixup != 0:
+            yield f"{indent}sub {loop_cnt}, {loop_cnt}, #{fixup}"
+        if jump_if_empty is not None:
+            yield f"cbz {loop_cnt}, {jump_if_empty}"
+        yield f"{self.lbl_start}:"
+
+    def end(self, other, indentation=0):
+        """Emit compare-and-branch at the end of the loop"""
+        indent = ' ' * indentation
+        lbl_start = self.lbl_start
+        if lbl_start.isdigit():
+            lbl_start += "b"
+        if other["reg1"] is None:
+            yield f'{indent}subs {other["cnt"]}, #1'
+        else:
+            yield f'{indent}subs {other["cnt"]}, {other["reg1"]}, {other["imm"]}'  # `subs` sets flags
+        yield f'{indent}bne {lbl_start}'
+
+class FatalParsingException(Exception):
+    """A fatal error happened during instruction parsing"""
+
+class UnknownInstruction(Exception):
+    """The parent instruction class for the given object could not be found"""
+
+class UnknownRegister(Exception):
+    """The register could not be found"""
+
+class Instruction:
+
+    class ParsingException(Exception):
+        """An attempt to parse an assembly line as a specific instruction failed
+
+        This is a frequently encountered exception since assembly lines are parsed by
+        trial and error, iterating over all instruction parsers."""
+        def __init__(self, err=None):
+            super().__init__(err)
+
+    def __init__(self, *, mnemonic,
+                 arg_types_in= None, arg_types_in_out = None, arg_types_out = None):
+
+        if arg_types_in is None:
+            arg_types_in = []
+        if arg_types_out is None:
+            arg_types_out = []
+        if arg_types_in_out is None:
+            arg_types_in_out = []
+
+        self.mnemonic = mnemonic
+
+        self.args_out_combinations = None
+        self.args_in_combinations = None
+        self.args_in_out_combinations = None
+        self.args_in_out_different = None
+        self.args_inout_out_different = None
+        self.args_in_inout_different = None
+
+        self.arg_types_in     = arg_types_in
+        self.arg_types_out    = arg_types_out
+        self.arg_types_in_out = arg_types_in_out
+        self.num_in           = len(arg_types_in)
+        self.num_out          = len(arg_types_out)
+        self.num_in_out       = len(arg_types_in_out)
+
+        self.args_out_restrictions    = [ None for _ in range(self.num_out)    ]
+        self.args_in_restrictions     = [ None for _ in range(self.num_in)     ]
+        self.args_in_out_restrictions = [ None for _ in range(self.num_in_out) ]
+
+        self.args_in     = []
+        self.args_out    = []
+        self.args_in_out = []
+
+        self.addr = None
+        self.increment = None
+        self.pre_index = None
+        self.offset_adjustable = True
+
+        self.immediate = None
+        self.datatype = None
+        self.index = None
+        self.flag = None
+        self.width = None
+        self.barrel = None
+        self.range = None
+
+    def extract_read_writes(self):
+        """Extracts 'reads'/'writes' clauses from the source line of the instruction"""
+
+        src_line = self.source_line
+
+        def hint_register_name(tag):
+            return f"hint_{tag}"
+
+        # Check if the source line is tagged as reading/writing from memory
+        def add_memory_write(tag):
+            self.num_out += 1
+            self.pattern_outputs.append((hint_register_name(tag), RegisterType.HINT))
+            self.args_out_restrictions.append(None)
+            self.args_out.append(hint_register_name(tag))
+            self.arg_types_out.append(RegisterType.HINT)
+
+        def add_memory_read(tag):
+            self.num_in += 1
+            self.pattern_inputs.append((hint_register_name(tag), RegisterType.HINT))
+            self.args_in_restrictions.append(None)
+            self.args_in.append(hint_register_name(tag))
+            self.arg_types_in.append(RegisterType.HINT)
+
+        write_tags = src_line.tags.get("writes", [])
+        read_tags = src_line.tags.get("reads", [])
+
+        if not isinstance(write_tags, list):
+            write_tags = [write_tags]
+
+        if not isinstance(read_tags, list):
+            read_tags = [read_tags]
+
+        for w in write_tags:
+            add_memory_write(w)
+
+        for r in read_tags:
+            add_memory_read(r)
+
+        return self
+
+    def global_parsing_cb(self, a, log=None):
+        """Parsing callback triggered after DataFlowGraph parsing which allows modification
+        of the instruction in the context of the overall computation.
+
+        This is primarily used to remodel input-outputs as outputs in jointly destructive
+        instruction patterns (See Section 4.4, https://eprint.iacr.org/2022/1303.pdf)."""
+        _ = log # log is not used
+        return False
+
+    def global_fusion_cb(self, a, log=None):
+        """Fusion callback triggered after DataFlowGraph parsing which allows fusing
+        of the instruction in the context of the overall computation.
+
+        This can be used e.g. to detect eor-eor pairs and replace them by eor3."""
+        _ = log # log is not used
+        return False
+
+    def write(self):
+        """Write the instruction"""
+        args = self.args_out + self.args_in_out + self.args_in
+        return self.mnemonic + ' ' + ', '.join(args)
+
+    @staticmethod
+    def unfold_abbrevs(mnemonic):
+        return mnemonic
+
+    def _is_instance_of(self, inst_list):
+        for inst in inst_list:
+            if isinstance(self,inst):
+                return True
+        return False
+
+    def is_ldr(self):
+         return self._is_instance_of([ ldr, ldr_with_imm, ldr_with_imm_stack, ldr_with_postinc, ldr_with_inc_writeback,])
+
+    def is_load(self):
+        """Indicates if an instruction is a load instruction"""
+        return self._is_instance_of([ ldr,
+                                      ldr_with_imm,
+                                      ldrb_with_imm,
+                                      ldrh_with_imm,
+                                      ldr_with_imm_stack,
+                                      ldr_with_postinc,
+                                      ldrh_with_postinc,
+                                      ldrd_imm,
+                                      ldrd_with_postinc,
+                                      ldr_with_inc_writeback,
+                                      ldm_interval,
+                                      ldm_interval_inc_writeback,
+                                      vldr_with_imm,
+                                      vldr_with_postinc,
+                                      vldm_interval_inc_writeback])
+    def is_store(self):
+        """Indicates if an instruction is a store instruction"""
+        return self._is_instance_of([ str_no_off,
+                                      strh_with_imm,
+                                      str_with_imm,
+                                      str_with_imm_stack,
+                                      str_with_postinc,
+                                      strh_with_postinc,
+                                      stm_interval_inc_writeback])
+    def is_load_store_instruction(self):
+        """Indicates if an instruction is a load or store instruction"""
+        return self.is_load() or self.is_store()
+
+    @classmethod
+    def make(cls, src):
+        """Abstract factory method parsing a string into an instruction instance."""
+
+    @staticmethod
+    def build(c, src, mnemonic, **kwargs):
+        """Attempt to parse a string as an instance of an instruction.
+
+        Args:
+            c: The target instruction the string should be attempted to be parsed as.
+            src: The string to parse.
+            mnemonic: The mnemonic of instruction c
+
+        Returns:
+            Upon success, the result of parsing src as an instance of c.
+
+        Raises:
+            ParsingException: The str argument cannot be parsed as an
+                instance of c.
+            FatalParsingException: A fatal error during parsing happened
+                that's likely a bug in the model.
+        """
+
+        if src.split(' ')[0] != mnemonic:
+            raise Instruction.ParsingException(f"Mnemonic does not match: {src.split(' ')[0]} vs. {mnemonic}")
+
+        obj = c(mnemonic=mnemonic, **kwargs)
+
+        # Replace <dt> by list of all possible datatypes
+        mnemonic = Instruction.unfold_abbrevs(obj.mnemonic)
+
+        expected_args = obj.num_in + obj.num_out + obj.num_in_out
+        regexp_txt  = rf"^\s*{mnemonic}"
+        if expected_args > 0:
+            regexp_txt += r"\s+"
+        regexp_txt += ','.join([r"\s*(\w+)\s*" for _ in range(expected_args)])
+        regexp = re.compile(regexp_txt)
+
+        p = regexp.match(src)
+        if p is None:
+            raise Instruction.ParsingException(
+                f"Doesn't match basic instruction template {regexp_txt}")
+
+        operands = list(p.groups())
+
+        if obj.num_out > 0:
+            obj.args_out = operands[:obj.num_out]
+            idx_args_in = obj.num_out
+        elif obj.num_in_out > 0:
+            obj.args_in_out = operands[:obj.num_in_out]
+            idx_args_in = obj.num_in_out
+        else:
+            idx_args_in = 0
+
+        obj.args_in = operands[idx_args_in:]
+
+        if not len(obj.args_in) == obj.num_in:
+            raise FatalParsingException(f"Something wrong parsing {src}: Expect {obj.num_in} input,"
+                f" but got {len(obj.args_in)} ({obj.args_in})")
+
+        return obj
+
+    @staticmethod
+    def parser(src_line):
+        """Global factory method parsing an assembly line into an instance
+        of a subclass of Instruction."""
+        insts = []
+        exceptions = {}
+        instnames = []
+
+        src = src_line.text.strip()
+
+        # Iterate through all derived classes and call their parser
+        # until one of them hopefully succeeds
+        for inst_class in Instruction.all_subclass_leaves:
+            try:
+                inst = inst_class.make(src)
+                instnames = [inst_class.__name__]
+                insts = [inst]
+                break
+            except Instruction.ParsingException as e:
+                exceptions[inst_class.__name__] = e
+
+        for i in insts:
+            i.source_line = src_line
+            i.extract_read_writes()
+
+        if len(insts) == 0:
+            logging.error("Failed to parse instruction %s", src)
+            logging.error("A list of attempted parsers and their exceptions follows.")
+            for i,e in exceptions.items():
+                msg = f"* {i + ':':20s} {e}"
+                logging.error(msg)
+            raise Instruction.ParsingException(
+                f"Couldn't parse {src}\nYou may need to add support "\
+                  "for a new instruction (variant)?")
+
+        logging.debug("Parsing result for '%s': %s", src, instnames)
+        return insts
+
+    def __repr__(self):
+        return self.write()
+
+class Armv7mInstruction(Instruction):
+    """Abstract class representing Armv7m instructions"""
+
+    PARSERS = {}
+
+    @staticmethod
+    def _unfold_pattern(src):
+
+        src = re.sub(r"\.",  "\\\\s*\\\\.\\\\s*", src)
+        src = re.sub(r"\[", "\\\\s*\\\\[\\\\s*", src)
+        src = re.sub(r"\]", "\\\\s*\\\\]\\\\s*", src)
+
+        def pattern_transform(g):
+            return \
+                f"([{g.group(1).lower()}{g.group(1)}]" +\
+                f"(?P<raw_{g.group(1)}{g.group(2)}>[0-9_][0-9_]*)|" +\
+                f"([{g.group(1).lower()}{g.group(1)}]<(?P<symbol_{g.group(1)}{g.group(2)}>\\w+)>))"
+        src = re.sub(r"<([RS])(\w+)>", pattern_transform, src)
+
+        # Replace <key> or <key0>, <key1>, ... with pattern
+        def replace_placeholders(src, mnemonic_key, regexp, group_name):
+            prefix = f"<{mnemonic_key}"
+            pattern = f"<{mnemonic_key}>"
+            def pattern_i(i):
+                return f"<{mnemonic_key}{i}>"
+
+            cnt = src.count(prefix)
+            if cnt > 1:
+                for i in range(cnt):
+                    src = re.sub(pattern_i(i),  f"(?P<{group_name}{i}>{regexp})", src)
+            else:
+                src = re.sub(pattern, f"(?P<{group_name}>{regexp})", src)
+
+            return src
+
+        flaglist = ["eq","ne","cs","hs","cc","lo","mi","pl","vs","vc","hi","ls","ge","lt","gt","le"]
+
+        flag_pattern = '|'.join(flaglist)
+        dt_pattern = "(?:|2|4|8|16)(?:B|H|S|D|b|h|s|d)"  # TODO: Notion of dt can be placed with notion for size in FP instructions
+        imm_pattern = "#(\\\\w|\\\\s|/| |-|\\*|\\+|\\(|\\)|=|,)+"
+        index_pattern = "[0-9]+"
+        width_pattern = "(?:\.w|\.n|)"
+        barrel_pattern = "(?:lsl|ror|lsr|asr)"
+        range_pattern = "\{(?P<range_type>[rs])(?P<range_start>\\\\d+)-[rs](?P<range_end>\\\\d+)\}"
+
+        src = re.sub(" ", "\\\\s+", src)
+        src = re.sub(",", "\\\\s*,\\\\s*", src)
+
+        src = replace_placeholders(src, "imm", imm_pattern, "imm")
+        src = replace_placeholders(src, "dt", dt_pattern, "datatype")
+        src = replace_placeholders(src, "index", index_pattern, "index")
+        src = replace_placeholders(src, "flag", flag_pattern, "flag") # TODO: Are any changes required for IT syntax?
+        src = replace_placeholders(src, "width", width_pattern, "width")
+        src = replace_placeholders(src, "barrel", barrel_pattern, "barrel")
+        src = replace_placeholders(src, "range", range_pattern, "range")
+
+        src = r"\s*" + src + r"\s*(//.*)?\Z"
+        return src
+
+    @staticmethod
+    def _build_parser(src):
+        regexp_txt = Armv7mInstruction._unfold_pattern(src)
+        regexp = re.compile(regexp_txt)
+
+        def _parse(line):
+            regexp_result = regexp.match(line)
+            if regexp_result is None:
+                raise Instruction.ParsingException(f"Does not match instruction pattern {src}"\
+                                                   f"[regex: {regexp_txt}]")
+            res = regexp.match(line).groupdict()
+            items = list(res.items())
+            for k, v in items:
+                for l in ["symbol_", "raw_"]:
+                    if k.startswith(l):
+                        del res[k]
+                        if v is None:
+                            continue
+                        k = k[len(l):]
+                        res[k] = v
+            return res
+        return _parse
+
+    @staticmethod
+    def get_parser(pattern):
+        """Build parser for given AArch64 instruction pattern"""
+        if pattern in Armv7mInstruction.PARSERS:
+            return Armv7mInstruction.PARSERS[pattern]
+        parser = Armv7mInstruction._build_parser(pattern)
+        Armv7mInstruction.PARSERS[pattern] = parser
+        return parser
+
+    @cache
+    @staticmethod
+    def _infer_register_type(ptrn):
+        if ptrn[0].upper() in ["R"]:
+            return RegisterType.GPR
+        if ptrn[0].upper() in ["S"]:
+            return RegisterType.FPR
+        if ptrn[0].upper() in ["T"]:
+            return RegisterType.HINT
+        raise FatalParsingException(f"Unknown pattern: {ptrn}")
+
+    def __init__(self, pattern, *, inputs=None, outputs=None, in_outs=None, modifiesFlags=False,
+                 dependsOnFlags=False):
+
+        self.mnemonic = pattern.split(" ")[0]
+
+        if inputs is None:
+            inputs = []
+        if outputs is None:
+            outputs = []
+        if in_outs is None:
+            in_outs = []
+        arg_types_in     = [Armv7mInstruction._infer_register_type(r) for r in inputs]
+        arg_types_out    = [Armv7mInstruction._infer_register_type(r) for r in outputs]
+        arg_types_in_out = [Armv7mInstruction._infer_register_type(r) for r in in_outs]
+
+        if modifiesFlags:
+            arg_types_out += [RegisterType.FLAGS]
+            outputs       += ["flags"]
+
+        if dependsOnFlags:
+            arg_types_in += [RegisterType.FLAGS]
+            inputs += ["flags"]
+
+        super().__init__(mnemonic=pattern,
+                     arg_types_in=arg_types_in,
+                     arg_types_out=arg_types_out,
+                     arg_types_in_out=arg_types_in_out)
+
+        self.inputs = inputs
+        self.outputs = outputs
+        self.in_outs = in_outs
+
+        self.pattern = pattern
+        self.pattern_inputs = list(zip(inputs, arg_types_in, strict=True))
+        self.pattern_outputs = list(zip(outputs, arg_types_out, strict=True))
+        self.pattern_in_outs = list(zip(in_outs, arg_types_in_out, strict=True))
+
+
+
+    @staticmethod
+    def _to_reg(ty, s):
+        if ty == RegisterType.GPR:
+            c = "r"
+        elif ty == RegisterType.FPR:
+            c = "s"
+        elif ty == RegisterType.HINT:
+            c = "t"
+        else:
+            assert False
+        if s.replace('_','').isdigit():
+            return f"{c}{s}"
+        return s
+
+    @staticmethod
+    def _build_pattern_replacement(s, ty, arg):
+        if ty == RegisterType.GPR:
+            if arg[0] != "r":
+                return f"{s[0].upper()}<{arg}>"
+            return s[0].lower() + arg[1:]
+        if ty == RegisterType.FPR:
+            if arg[0] != "s":
+                return f"{s[0].upper()}<{arg}>"
+            return s[0].lower() + arg[1:]
+        if ty == RegisterType.HINT:
+            if arg[0] != "t":
+                return f"{s[0].upper()}<{arg}>"
+            return s[0].lower() + arg[1:]
+        raise FatalParsingException(f"Unknown register type ({s}, {ty}, {arg})")
+
+    @staticmethod
+    def _instantiate_pattern(s, ty, arg, out):
+        if ty == RegisterType.FLAGS or ty == RegisterType.HINT:
+            return out
+        rep = Armv7mInstruction._build_pattern_replacement(s, ty, arg)
+        res = out.replace(f"<{s}>", rep)
+        if res == out:
+            raise FatalParsingException(f"Failed to replace <{s}> by {rep} in {out}!")
+        return res
+
+    @staticmethod
+    def build_core(obj, res):
+
+        def group_to_attribute(group_name, attr_name, f=None):
+            def f_default(x):
+                return x
+            def group_name_i(i):
+                return f"{group_name}{i}"
+            if f is None:
+                f = f_default
+            if group_name in res.keys():
+                setattr(obj, attr_name, f(res[group_name]))
+            else:
+                idxs = [ i for i in range(4) if group_name_i(i) in res.keys() ]
+                if len(idxs) == 0:
+                    return
+                assert idxs == list(range(len(idxs)))
+                setattr(obj, attr_name,
+                        list(map(lambda i: f(res[group_name_i(i)]), idxs)))
+
+        group_to_attribute('datatype', 'datatype', lambda x: x.lower())
+        group_to_attribute('imm', 'immediate', lambda x:x[1:]) # Strip '#'
+        group_to_attribute('index', 'index', int)
+        group_to_attribute('flag', 'flag')
+        group_to_attribute('width', 'width')
+        group_to_attribute('barrel', 'barrel')
+        group_to_attribute('range', 'range')
+        group_to_attribute('range_start', 'range_start', int)
+        group_to_attribute('range_end', 'range_end', int)
+        group_to_attribute('range_type', 'range_type')
+
+        for s, ty in obj.pattern_inputs:
+            if ty == RegisterType.FLAGS:
+                obj.args_in.append("flags")
+            else:
+                obj.args_in.append(Armv7mInstruction._to_reg(ty, res[s]))
+        for s, ty in obj.pattern_outputs:
+            if ty == RegisterType.FLAGS:
+                obj.args_out.append("flags")
+            else:
+                obj.args_out.append(Armv7mInstruction._to_reg(ty, res[s]))
+
+        for s, ty in obj.pattern_in_outs:
+            obj.args_in_out.append(Armv7mInstruction._to_reg(ty, res[s]))
+
+    @staticmethod
+    def build(c, src):
+        pattern = getattr(c, "pattern")
+        inputs = getattr(c, "inputs", []).copy()
+        outputs = getattr(c, "outputs", []).copy()
+        in_outs = getattr(c, "in_outs", []).copy()
+        modifies_flags = getattr(c,"modifiesFlags", False)
+        depends_on_flags = getattr(c,"dependsOnFlags", False)
+
+        if isinstance(src, str):
+            # Leave checking the mnemonic out for now; not strictly required
+            # Allows xxx.w and xxx.n syntax
+            res = Armv7mInstruction.get_parser(pattern)(src)
+        else:
+            assert isinstance(src, dict)
+            res = src
+
+        obj = c(pattern, inputs=inputs, outputs=outputs, in_outs=in_outs,
+                modifiesFlags=modifies_flags, dependsOnFlags=depends_on_flags)
+
+        Armv7mInstruction.build_core(obj, res)
+        return obj
+
+    @classmethod
+    def make(cls, src):
+        return Armv7mInstruction.build(cls, src)
+
+    def write(self):
+        out = self.pattern
+        l = list(zip(self.args_in, self.pattern_inputs))     + \
+            list(zip(self.args_out, self.pattern_outputs))   + \
+            list(zip(self.args_in_out, self.pattern_in_outs))
+        for arg, (s, ty) in l:
+            out = Armv7mInstruction._instantiate_pattern(s, ty, arg, out)
+
+        def replace_pattern(txt, attr_name, mnemonic_key, t=None):
+            def t_default(x):
+                return x
+            if t is None:
+                t = t_default
+
+            a = getattr(self, attr_name)
+            if a is None:
+                return txt
+            if not isinstance(a, list):
+                txt = txt.replace(f"<{mnemonic_key}>", t(a))
+                return txt
+            for i, v in enumerate(a):
+                txt = txt.replace(f"<{mnemonic_key}{i}>", t(v))
+            return txt
+
+        out = replace_pattern(out, "immediate", "imm", lambda x: f"#{x}")
+        out = replace_pattern(out, "datatype", "dt", lambda x: x.upper())
+        out = replace_pattern(out, "flag", "flag")
+        out = replace_pattern(out, "index", "index", str)
+        out = replace_pattern(out, "width", "width", lambda x: x.lower())
+        out = replace_pattern(out, "barrel", "barrel", lambda x: x.lower())
+        out = replace_pattern(out, "range", "range", lambda x: x.lower())
+
+        out = out.replace("\\[", "[")
+        out = out.replace("\\]", "]")
+        return out
+
+class Armv7mBasicArithmetic(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+class Armv7mShiftedArithmetic(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+class Armv7mMultiplication(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+class Armv7mLogical(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+class Armv7mShiftedLogical(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+class Armv7mLoadInstruction(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+class Armv7mStoreInstruction(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+class Armv7mFPInstruction(Armv7mInstruction): # pylint: disable=missing-docstring,invalid-name
+    pass
+
+# FP
+class vmov_gpr(Armv7mFPInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "vmov<width> <Rd>, <Sa>"
+    inputs = ["Sa"]
+    outputs = ["Rd"]
+
+class vmov_gpr2(Armv7mFPInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "vmov<width> <Sd>, <Ra>"
+    inputs = ["Ra"]
+    outputs = ["Sd"]
+
+class vmov_gpr2_dual(Armv7mFPInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "vmov<width> <Sd1>, <Sd2>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Sd1", "Sd2"]
+
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.args_out_combinations = [
+                ( [0,1], [ [ f"s{i}", f"s{i+1}" ] for i in range(0,len(RegisterType.list_registers(RegisterType.FPR))) ] )
+            ]
+        return obj
+
+# movs
+class movw_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "movw <Rd>, <imm>"
+    outputs = ["Rd"]
+
+class movt_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "movt <Rd>, <imm>"
+    in_outs = ["Rd"]
+
+# Addition
+class add(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "add<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class add_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "add<width> <Rd>, <Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+
+class add_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "add<width> <Rd>, <Ra>, <imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
+class add_imm_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "add<width> <Rd>, <imm>"
+    in_outs = ["Rd"]
+
+class add_shifted(Armv7mShiftedArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "add<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class adds(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "adds<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+    modifiesFlags=True
+
+class uadd16(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "uadd16<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class sadd16(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "sadd16<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+# Subtraction
+class sub(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "sub<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class sub_shifted(Armv7mShiftedArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "sub<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class sub_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "sub<width> <Rd>, <Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+
+class sub_imm_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "sub<width> <Ra>, <imm>"
+    in_outs = ["Ra"]
+
+class subs_imm_short(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "subs<width> <Ra>, <imm>"
+    in_outs = ["Ra"]
+    modifiesFlags = True
+
+class usub16(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "usub16<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class ssub16(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ssub16<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+# Multiplication
+class mul(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "mul<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class mul_short(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "mul<width> <Rd>, <Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+
+class mla(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "mla<width> <Rd>, <Ra>, <Rb>, <Rc>"
+    inputs = ["Ra","Rb", "Rc"]
+    outputs = ["Rd"]
+
+class mls(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "mls<width> <Rd>, <Ra>, <Rb>, <Rc>"
+    inputs = ["Ra","Rb", "Rc"]
+    outputs = ["Rd"]
+
+class smulwb(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smulwb<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class smulwt(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smulwt<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class smultb(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smultb<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class smultt(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smultt<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class smulbb(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smulbb<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra","Rb"]
+    outputs = ["Rd"]
+
+class smlabt(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smlabt<width> <Rd>, <Ra>, <Rb>, <Rc>"
+    inputs = ["Ra","Rb", "Rc"]
+    outputs = ["Rd"]
+
+class smlabb(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smlabb<width> <Rd>, <Ra>, <Rb>, <Rc>"
+    inputs = ["Ra","Rb", "Rc"]
+    outputs = ["Rd"]
+
+class smlatt(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smlatt<width> <Rd>, <Ra>, <Rb>, <Rc>"
+    inputs = ["Ra","Rb", "Rc"]
+    outputs = ["Rd"]
+
+class smull(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smull<width> <Ra>, <Rb>, <Rc>, <Rd>"
+    inputs = ["Rc","Rd"]
+    outputs = ["Ra", "Rb"]
+
+class smlal(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smlal<width> <Ra>, <Rb>, <Rc>, <Rd>"
+    inputs = ["Rc","Rd"]
+    in_outs = ["Ra", "Rb"]
+
+class smlad(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smlad<width> <Ra>, <Rb>, <Rc>, <Rd>"
+    inputs = ["Rb", "Rc","Rd"]
+    outputs = ["Ra"]
+
+class smladx(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smladx<width> <Ra>, <Rb>, <Rc>, <Rd>"
+    inputs = ["Rb", "Rc","Rd"]
+    outputs = ["Ra"]
+
+class smmulr(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smmulr<width> <Ra>, <Rb>, <Rc>"
+    inputs = ["Rb","Rc"]
+    outputs = ["Ra"]
+
+class smuad(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smuad<width> <Ra>, <Rb>, <Rc>"
+    inputs = ["Rb","Rc"]
+    outputs = ["Ra"]
+
+class smuadx(Armv7mMultiplication): # pylint: disable=missing-docstring,invalid-name
+    pattern = "smuadx<width> <Ra>, <Rb>, <Rc>"
+    inputs = ["Rb","Rc"]
+    outputs = ["Ra"]
+
+
+# Logical
+
+class neg_short(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "neg<width> <Rd>, <Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+class log_and(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "and<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class log_and_shifted(Armv7mShiftedLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "and<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class log_or(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "orr<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class log_or_shifted(Armv7mShiftedLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "orr<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class eor(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "eor<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class eor_short(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "eor<width> <Rd>, <Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+
+class eors(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "eors<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+    modifiesFlags = True
+
+class eors_short(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "eors<width> <Rd>, <Ra>"
+    inputs = ["Ra"]
+    in_outs = ["Rd"]
+    modifiesFlags = True
+
+class eor_shifted(Armv7mShiftedLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "eor<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+    def write(self):
+        self.immediate = simplify(self.immediate)
+        return super().write()
+
+class bic(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "bic<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class bics(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "bics<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+    modifiesFlags = True
+
+class bic_shifted(Armv7mShiftedLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "bic<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class ubfx_imm(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ubfx<width> <Rd>, <Ra>, <imm0>, <imm1>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
+class ror(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ror<width> <Rd>, <Ra>, <imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
+class ror_short(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ror<width> <Rd>, <imm>"
+    in_outs = ["Rd"]
+
+class rors_short(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "rors<width> <Rd>, <imm>"
+    in_outs = ["Rd"]
+    modifiesFlags = True
+
+class lsl(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "lsl<width> <Rd>, <Ra>, <imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
+class asr(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "asr<width> <Rd>, <Ra>, <imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+
+class asrs(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "asrs<width> <Rd>, <Ra>, <imm>"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+    modifiesFlags = True
+
+class pkhtb(Armv7mShiftedLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "pkhtb<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class pkhbt(Armv7mLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "pkhbt<width> <Rd>, <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+class pkhbt_shifted(Armv7mShiftedLogical): # pylint: disable=missing-docstring,invalid-name
+    pattern = "pkhbt<width> <Rd>, <Ra>, <Rb>, <barrel> <imm>"
+    inputs = ["Ra", "Rb"]
+    outputs = ["Rd"]
+
+# Load
+class ldr(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldr<width> <Rd>, [<Ra>]"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = 0
+        obj.addr = obj.args_in[0]
+        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
+        return obj
+
+    def write(self):
+        if int(self.pre_index) != 0:
+            self.immediate = simplify(self.pre_index)
+            self.pattern = ldr_with_imm.pattern
+        return super().write()
+
+class ldr_with_imm(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldr<width> <Rd>, [<Ra>, <imm>]"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = obj.args_in[0]
+        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+class ldrb_with_imm(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldrb<width> <Rd>, [<Ra>, <imm>]"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
+        obj.addr = obj.args_in[0]
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+class ldrh_with_imm(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldrh<width> <Rd>, [<Ra>, <imm>]"
+    inputs = ["Ra"]
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.args_in_out_different = [(0,0)] # Can't have Rd==Ra
+        obj.addr = obj.args_in[0]
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+class ldr_with_imm_stack(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldr<width> <Rd>, [sp, <imm>]"
+    inputs = []
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = "sp"
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+class ldr_with_postinc(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldr<width> <Rd>, [<Ra>], <imm>"
+    in_outs = [ "Ra" ]
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        obj.increment = obj.immediate
+        obj.pre_index = None
+        obj.args_inout_out_different = [(0,0)] # Can't have Rd==Ra
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class ldrh_with_postinc(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldrh<width> <Rd>, [<Ra>], <imm>"
+    in_outs = [ "Ra" ]
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        obj.increment = obj.immediate
+        obj.args_inout_out_different = [(0,0)] # Can't have Rd==Ra
+        obj.pre_index = None
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class Ldrd(Armv7mLoadInstruction):
+    pass
+
+class ldrd_imm(Ldrd): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldrd<width> <Ra>, <Rb>, [<Rc>, <imm>]"
+    in_outs = [ "Rc" ]
+    outputs = ["Ra", "Rb"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class ldrd_with_postinc(Ldrd): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldrd<width> <Ra>, <Rb>, [<Rc>], <imm>"
+    in_outs = [ "Rc" ]
+    outputs = ["Ra", "Rb"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        obj.increment = obj.immediate
+        obj.pre_index = None
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class ldr_with_inc_writeback(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldr<width> <Rd>, [<Ra>, <imm>]!"
+    in_outs = [ "Ra" ]
+    outputs = ["Rd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = obj.immediate
+        obj.pre_index = None
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class ldm_interval(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldm<width> <Ra>, <range>"
+    inputs = ["Ra"]
+    outputs = []
+
+    def write(self):
+        reg_from = self.args_out[0]
+        reg_to = self.args_out[-1]
+        self.range = f"{{{reg_from}-{reg_to}}}"
+        return super().write()
+
+
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        reg_type = Armv7mInstruction._infer_register_type(obj.range_type)
+        num_regs = len(RegisterType.list_registers(reg_type))
+        obj.increment = (obj.range_end-obj.range_start+1) * 4 # word sized loads
+        obj.args_out =  [f"{obj.range_type}{i}" for i in range(obj.range_start, obj.range_end+1)]
+        obj.num_out = len(obj.args_out)
+        obj.arg_types_out = [RegisterType.GPR] * obj.num_out
+        obj.args_out_restrictions    = [[ f"r{i+j}"  for j in range(0, num_regs-obj.num_out)] for i in range(0, obj.num_out) ]
+        obj.args_out_combinations = [ ( list(range(0, obj.num_out)), [ [ f"r{i+j}" for i in range(0, obj.num_out)] for j in range(0, num_regs-obj.num_out) ] )]
+        return obj
+
+class ldm_interval_inc_writeback(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "ldm<width> <Ra>!, <range>"
+    in_outs = ["Ra"]
+    outputs = []
+
+    def write(self):
+        reg_from = self.args_out[0]
+        reg_to = self.args_out[-1]
+        self.range = f"{{{reg_from}-{reg_to}}}"
+        return super().write()
+
+
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        reg_type = Armv7mInstruction._infer_register_type(obj.range_type)
+        num_regs = len(RegisterType.list_registers(reg_type))
+        obj.increment = (obj.range_end-obj.range_start+1) * 4 # word sized loads
+        obj.args_out =  [f"{obj.range_type}{i}" for i in range(obj.range_start, obj.range_end+1)]
+        obj.num_out = len(obj.args_out)
+        obj.arg_types_out = [RegisterType.GPR] * obj.num_out
+        obj.args_out_restrictions    = [[ f"r{i+j}"  for j in range(0, num_regs-obj.num_out)] for i in range(0, obj.num_out) ]
+        obj.args_out_combinations = [ ( list(range(0, obj.num_out)), [ [ f"r{i+j}" for i in range(0, obj.num_out)] for j in range(0, num_regs-obj.num_out) ] )]
+        return obj
+
+class vldr_with_imm(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "vldr<width> <Sd>, [<Ra>, <imm>]"
+    inputs = ["Ra"]
+    outputs = ["Sd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = obj.args_in[0]
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+
+class vldr_with_postinc(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "vldr<width> <Sd>, [<Ra>], <imm>"
+    in_outs = ["Ra"]
+    outputs = ["Sd"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        obj.increment = obj.immediate
+        obj.pre_index = None
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class vldm_interval_inc_writeback(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "vldm<width> <Ra>!, <range>"
+    in_outs = ["Ra"]
+    outputs = []
+    def write(self):
+        reg_from = self.args_out[0]
+        reg_to = self.args_out[-1]
+        self.range = f"{{{reg_from}-{reg_to}}}"
+        return super().write()
+
+
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        reg_type = Armv7mInstruction._infer_register_type(obj.range_type)
+        num_regs = len(RegisterType.list_registers(reg_type))
+        obj.increment = (obj.range_end-obj.range_start+1) * 4 # word sized loads
+        obj.args_out =  [f"{obj.range_type}{i}" for i in range(obj.range_start, obj.range_end+1)]
+        obj.num_out = len(obj.args_out)
+        obj.arg_types_out = [RegisterType.FPR] * obj.num_out
+        obj.args_out_restrictions    = [[ f"s{i+j}"  for j in range(0, num_regs-obj.num_out)] for i in range(0, obj.num_out) ]
+        obj.args_out_combinations = [ ( list(range(0, obj.num_out)), [ [ f"s{i+j}" for i in range(0, obj.num_out)] for j in range(0, num_regs-obj.num_out) ] )]
+        return obj
+# Store
+
+class str_no_off(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "str<width> <Rd>, [<Ra>]"
+    inputs = ["Ra", "Rd"]
+    outputs = []
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = 0
+        obj.addr = obj.args_in[0]
+        return obj
+
+    def write(self):
+        if int(self.pre_index) != 0:
+            self.immediate = simplify(self.pre_index)
+            self.pattern = str_with_imm.pattern
+        return super().write()
+
+class strh_with_imm(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "strh<width> <Rd>, [<Ra>, <imm>]"
+    inputs = ["Ra", "Rd"]
+    outputs = []
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = obj.args_in[0]
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+class str_with_imm(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "str<width> <Rd>, [<Ra>, <imm>]"
+    inputs = ["Ra", "Rd"]
+    outputs = []
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = obj.args_in[0]
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+class str_with_imm_stack(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "str<width> <Rd>, [sp, <imm>]"
+    inputs = ["Rd"]
+    outputs = []
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mInstruction.build(cls, src)
+        obj.increment = None
+        obj.pre_index = obj.immediate
+        obj.addr = "sp"
+        return obj
+
+    def write(self):
+        self.immediate = simplify(self.pre_index)
+        return super().write()
+
+class str_with_postinc(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "str<width> <Rd>, [<Ra>], <imm>"
+    inputs = ["Rd"]
+    in_outs = ["Ra"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mStoreInstruction.build(cls, src)
+        obj.increment = obj.immediate
+        obj.pre_index = None
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class strh_with_postinc(Armv7mStoreInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "strh<width> <Rd>, [<Ra>], <imm>"
+    inputs = ["Rd"]
+    in_outs = ["Ra"]
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mStoreInstruction.build(cls, src)
+        obj.increment = obj.immediate
+        obj.pre_index = None
+        obj.addr = obj.args_in_out[0]
+        return obj
+
+class stm_interval_inc_writeback(Armv7mLoadInstruction): # pylint: disable=missing-docstring,invalid-name
+    pattern = "stm<width> <Ra>!, <range>"
+    in_outs = ["Ra"]
+    outputs = []
+
+    def write(self):
+        reg_from = self.args_in[0]
+        reg_to = self.args_in[-1]
+        self.range = f"{{{reg_from}-{reg_to}}}"
+        return super().write()
+
+    @classmethod
+    def make(cls, src):
+        obj = Armv7mLoadInstruction.build(cls, src)
+        reg_type = Armv7mInstruction._infer_register_type(obj.range_type)
+        num_regs = len(RegisterType.list_registers(reg_type))
+        obj.increment = (obj.range_end-obj.range_start+1) * 4 # word sized loads
+        obj.args_in =  [f"{obj.range_type}{i}" for i in range(obj.range_start, obj.range_end+1)]
+        obj.num_in = len(obj.args_in)
+        obj.arg_types_in = [RegisterType.GPR] * obj.num_in
+        obj.args_in_restrictions    = [[ f"r{i+j}"  for j in range(0, num_regs-obj.num_in)] for i in range(0, obj.num_in) ]
+        obj.args_in_combinations = [ ( list(range(0, obj.num_in)), [ [ f"r{i+j}" for i in range(0, obj.num_in)] for j in range(0, num_regs-obj.num_in) ] )]
+        return obj
+# Other
+class cmp(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "cmp<width> <Ra>, <Rb>"
+    inputs = ["Ra", "Rb"]
+    modifiesFlags=True
+    dependsOnFlags=True
+
+class cmp_imm(Armv7mBasicArithmetic): # pylint: disable=missing-docstring,invalid-name
+    pattern = "cmp<width> <Ra>, <imm>"
+    inputs = ["Ra"]
+    modifiesFlags=True
+
+class Spill:
+    def spill(reg, loc, spill_to_vreg=None):
+        """Generates the instruction text for a spill to either
+        the stack or the FPR. If spill_to_vreg is None (default),
+        the spill goes to the stack. Otherwise, spill_to_vreg must
+        be an integer defining the base of the registers in the FPR
+        which should be used as a stack. For example, passing 8 would
+        spill to s8,s9,.. ."""
+        if spill_to_vreg is None:
+            return f"str {reg}, [sp, #STACK_LOC_{loc}]"
+        else:
+            vreg_base = int(spill_to_vreg)
+            return f"vmov s{vreg_base+int(loc)}, {reg}"
+    def restore(reg, loc, spill_to_vreg=None):
+        """Generates the instruction text for a spill restore from either
+        the stack or the FPR. If spill_to_vreg is None (default),
+        the spill goes to the stack. Otherwise, spill_to_vreg must
+        be an integer defining the base of the registers in the FPR
+        which should be used as a stack. For example, passing 8 would
+        spill to s8,s9,.. ."""
+        if spill_to_vreg is None:
+            return  f"ldr {reg}, [sp, #STACK_LOC_{loc}]"
+        else:
+            vreg_base = int(spill_to_vreg)
+            return f"vmov {reg}, s{vreg_base+int(loc)}"
+
+def ldm_interval_splitting_cb():
+    def core(inst,t,log=None):
+
+        ptr = inst.args_in[0]
+        regs = inst.args_out
+        width = inst.width
+
+        ldrs = []
+        offset = 0
+        for r in regs:
+            ldr = Armv7mInstruction.build(
+                ldr_with_imm, {"width": width, "Rd": r, "Ra": ptr, "imm": f"#{offset}"})
+            ldr.pre_index = offset
+            ldrs.append(ldr)
+            offset += 4
+
+            ldr_src = SourceLine(ldr.write()).\
+                add_tags(inst.source_line.tags).\
+                add_comments(inst.source_line.comments)
+            ldr.source_line = ldr_src
+
+        if log is not None:
+            log(f"ldm splitting: {t.inst}; {[ldr for ldr in ldrs]}")
+
+        t.changed = True
+        t.inst = ldrs
+        return True
+
+    return core
+
+ldm_interval.global_fusion_cb  = ldm_interval_splitting_cb()
+
+def stm_interval_inc_writeback_splitting_cb():
+    def core(inst,t,log=None):
+
+        ptr = inst.args_in_out[0]
+        regs = inst.args_in
+        width = inst.width
+
+        strs = []
+        offset = (len(regs) - 1) * 4
+        for r in regs[:0:-1]:
+            store = Armv7mInstruction.build(
+                str_with_imm, {"width": width, "Rd": r, "Ra": ptr, "imm": f"#{offset}"})
+            store.pre_index = offset
+            strs.append(store)
+            offset -= 4
+        # Final store includes increment
+        store = Armv7mInstruction.build(
+                str_with_postinc, {"width": width, "Rd": regs[0], "Ra": ptr, "imm": f"#{len(regs) * 4}"})
+        strs.append(store)
+
+        for store in strs:
+            store_src = SourceLine(store.write()).\
+                add_tags(inst.source_line.tags).\
+                add_comments(inst.source_line.comments)
+            store.source_line = store_src
+
+        if log is not None:
+            log(f"stm! splitting: {t.inst}; {[store for store in strs]}")
+
+        t.changed = True
+        t.inst = strs
+        return True
+
+    return core
+
+stm_interval_inc_writeback.global_fusion_cb  = stm_interval_inc_writeback_splitting_cb()
+
+def ldm_interval_inc_writeback_splitting_cb():
+    def core(inst,t,log=None):
+
+        ptr = inst.args_in_out[0]
+        regs = inst.args_out
+        width = inst.width
+
+        ldrs = []
+        offset = (len(regs) - 1) * 4
+        for r in regs[:0:-1]:
+            ldr = Armv7mInstruction.build(
+                ldr_with_imm, {"width": width, "Rd": r, "Ra": ptr, "imm": f"#{offset}"})
+            ldr.pre_index = offset
+            ldrs.append(ldr)
+            offset -= 4
+        # Final load includes increment
+        ldr = Armv7mInstruction.build(
+                ldr_with_postinc, {"width": width, "Rd": regs[0], "Ra": ptr, "imm": f"#{len(regs) * 4}"})
+        ldrs.append(ldr)
+
+        for ldr in ldrs:
+            ldr_src = SourceLine(ldr.write()).\
+                add_tags(inst.source_line.tags).\
+                add_comments(inst.source_line.comments)
+            ldr.source_line = ldr_src
+
+        if log is not None:
+            log(f"ldm! splitting: {t.inst}; {[ldr for ldr in ldrs]}")
+
+        t.changed = True
+        t.inst = ldrs
+        return True
+
+    return core
+
+ldm_interval_inc_writeback.global_fusion_cb  = ldm_interval_inc_writeback_splitting_cb()
+
+def vldm_interval_inc_writeback_splitting_cb():
+    def core(inst,t,log=None):
+
+        ptr = inst.args_in_out[0]
+        regs = inst.args_out
+        width = inst.width
+
+        ldrs = []
+        offset = 0
+        for r in regs:
+            ldr = Armv7mInstruction.build(
+                vldr_with_imm, {"width": width, "Sd": r, "Ra": ptr, "imm": f"#{offset}"})
+            ldr.pre_index = offset
+            ldrs.append(ldr)
+            offset += 4
+
+        add_ptr = Armv7mInstruction.build(
+                add_imm, {"width": width, "Rd": ptr, "Ra": ptr, "imm": f"#{offset}"})
+        ldrs.append(add_ptr)
+
+        for ldr in ldrs:
+            ldr_src = SourceLine(ldr.write()).\
+                add_tags(inst.source_line.tags).\
+                add_comments(inst.source_line.comments)
+            ldr.source_line = ldr_src
+
+        if log is not None:
+            log(f"ldm! splitting: {t.inst}; {[ldr for ldr in ldrs]}")
+
+        t.changed = True
+        t.inst = ldrs
+        return True
+
+    return core
+
+vldm_interval_inc_writeback.global_fusion_cb  = vldm_interval_inc_writeback_splitting_cb()
+
+def ldrd_postinc_splitting_cb():
+    def core(inst,t,log=None):
+
+        ptr = inst.args_in_out[0]
+        regs = inst.args_out
+        width = inst.width
+
+        ldrs = []
+
+        ldr = Armv7mInstruction.build(
+            ldr_with_imm, {"width": width, "Rd": regs[1], "Ra": ptr, "imm": "#4"})
+        ldr.pre_index = 4
+        ldrs.append(ldr)
+        # Final load includes increment
+        ldr = Armv7mInstruction.build(
+                ldr_with_postinc, {"width": width, "Rd": regs[0], "Ra": ptr, "imm": "#8"})
+        ldr.increment = 8
+        ldr.pre_index = None
+        ldr.addr = ptr
+        ldrs.append(ldr)
+
+        for ldr in ldrs:
+            ldr_src = SourceLine(ldr.write()).\
+                add_tags(inst.source_line.tags).\
+                add_comments(inst.source_line.comments)
+            ldr.source_line = ldr_src
+
+        if log is not None:
+            log(f"ldrd splitting: {t.inst}; {[ldr for ldr in ldrs]}")
+
+        t.changed = True
+        t.inst = ldrs
+        return True
+
+    return core
+
+ldrd_with_postinc.global_fusion_cb  = ldrd_postinc_splitting_cb()
+
+
+
+def ldrd_imm_splitting_cb():
+    def core(inst,t,log=None):
+
+        ptr = inst.args_in_out[0]
+        regs = inst.args_out
+        width = inst.width
+
+        ldrs = []
+
+        ldr = Armv7mInstruction.build(
+            ldr_with_imm, {"width": width, "Rd": regs[0], "Ra": ptr, "imm": inst.pre_index })
+        ldr.pre_index = inst.pre_index
+        ldrs.append(ldr)
+        # Final load includes increment
+        ldr = Armv7mInstruction.build(
+                ldr_with_imm, {"width": width, "Rd": regs[1], "Ra": ptr, "imm": f"{inst.pre_index}+4"})
+        ldr.pre_index = f"{inst.pre_index}+4"
+        ldr.addr = ptr
+        ldrs.append(ldr)
+
+        for ldr in ldrs:
+            ldr_src = SourceLine(ldr.write()).\
+                add_tags(inst.source_line.tags).\
+                add_comments(inst.source_line.comments)
+            ldr.source_line = ldr_src
+
+        if log is not None:
+            log(f"ldrd splitting: {t.inst}; {[ldr for ldr in ldrs]}")
+
+        t.changed = True
+        t.inst = ldrs
+        return True
+
+    return core
+
+ldrd_imm.global_fusion_cb = ldrd_imm_splitting_cb()
+
+# Returns the list of all subclasses of a class which don't have
+# subclasses themselves
+def all_subclass_leaves(c):
+
+    def has_subclasses(cl):
+        return len(cl.__subclasses__()) > 0
+    def is_leaf(c):
+        return not has_subclasses(c)
+
+    def all_subclass_leaves_core(leaf_lst, todo_lst):
+        leaf_lst += filter(is_leaf, todo_lst)
+        todo_lst = [ csub
+                     for c in filter(has_subclasses, todo_lst)
+                     for csub in c.__subclasses__() ]
+        if len(todo_lst) == 0:
+            return leaf_lst
+        return all_subclass_leaves_core(leaf_lst, todo_lst)
+
+    return all_subclass_leaves_core([], [c])
+
+Instruction.all_subclass_leaves = all_subclass_leaves(Instruction)
+
+def iter_armv7m_instructions():
+    yield from all_subclass_leaves(Instruction)
+
+def find_class(src):
+    for inst_class in iter_armv7m_instructions():
+        if isinstance(src,inst_class):
+            return inst_class
+    raise UnknownInstruction(f"Couldn't find instruction class for {src} (type {type(src)})")
+
+def lookup_multidict(d, inst, default=None):
+    instclass = find_class(inst)
+    for l,v in d.items():
+        # Multidict entries can be the following:
+        # - An instruction class. It matches any instruction of that class.
+        # - A callable. It matches any instruction returning `True` when passed
+        #   to the callable.
+        # - A tuple of instruction classes or callables. It matches any instruction
+        #   which matches at least one element in the tuple.
+        def match(x):
+            if inspect.isclass(x):
+                return isinstance(inst, x)
+            assert callable(x)
+            return x(inst)
+        if not isinstance(l, tuple):
+            l = [l]
+        for lp in l:
+            if match(lp):
+                return v
+    if default is None:
+        raise UnknownInstruction(f"Couldn't find {instclass} for {inst}")
+    return default
diff --git a/slothy/targets/arm_v7m/cortex_m4.py b/slothy/targets/arm_v7m/cortex_m4.py
new file mode 100644
index 00000000..6a573411
--- /dev/null
+++ b/slothy/targets/arm_v7m/cortex_m4.py
@@ -0,0 +1,75 @@
+
+"""
+Experimental Cortex-M4 microarchitecture model for SLOTHY
+
+WARNING: The data in this module is approximate and may contain errors.
+"""
+
+################################### NOTE ###############################################
+###                                                                                  ###
+### WARNING: The data in this module is approximate and may contain errors.          ###
+###          They are _NOT_ an official software optimization guide for Cortex-M4.  ###
+###                                                                                  ###
+########################################################################################
+
+from enum import Enum
+from slothy.targets.arm_v7m.arch_v7m import *
+
+issue_rate = 1
+llvm_mca_target = "cortex-m4"
+
+class ExecutionUnit(Enum):
+    """Enumeration of execution units in Cortex-M4 model"""
+    UNIT=0
+    def __repr__(self):
+        return self.name
+
+# Opaque function called by SLOTHY to add further microarchitecture-
+# specific constraints which are not encapsulated by the general framework.
+def add_further_constraints(slothy):
+    if slothy.config.constraints.functional_only:
+        return
+
+# Opaque function called by SLOTHY to add further microarchitecture-
+# specific objectives.
+def has_min_max_objective(config):
+    """Adds Cortex-"""
+    _ = config
+    return False
+def get_min_max_objective(slothy):
+    _ = slothy
+    return
+
+execution_units = {
+    (adds, add, add_short, add_imm, add_imm_short, add_shifted, sub_shifted, sub_imm_short, mul, smull, smlal, log_and, log_or, eor, eor_shifted, bic, bic_shifted, ror, ldr_with_imm, str_with_imm): ExecutionUnit.UNIT,
+}
+
+inverse_throughput = {
+    ( adds, add, add_short, add_imm, add_imm_short, add_shifted, sub_shifted, sub_imm_short, mul, smull, smlal, log_and, log_or, eor, eor_shifted, bic, bic_shifted, ror ) : 1,
+    (ldr_with_imm, str_with_imm) : 2}
+
+default_latencies = {
+    (adds, add, add_short, add_imm, add_imm_short, add_shifted, sub_shifted, sub_imm_short, mul, smull, smlal, log_and, log_or, eor, eor_shifted, bic, bic_shifted, ror): 1,
+    (ldr_with_imm, str_with_imm) : 2
+}
+
+def get_latency(src, out_idx, dst):
+    _ = out_idx # out_idx unused
+
+    instclass_src = find_class(src)
+    instclass_dst = find_class(dst)
+
+    latency = lookup_multidict(
+        default_latencies, src)
+
+    return latency
+
+def get_units(src):
+    units = lookup_multidict(execution_units, src)
+    if isinstance(units,list):
+        return units
+    return [units]
+
+def get_inverse_throughput(src):
+    return lookup_multidict(
+        inverse_throughput, src)
diff --git a/slothy/targets/arm_v7m/cortex_m7.py b/slothy/targets/arm_v7m/cortex_m7.py
new file mode 100644
index 00000000..f6c2ac2c
--- /dev/null
+++ b/slothy/targets/arm_v7m/cortex_m7.py
@@ -0,0 +1,353 @@
+"""
+Experimental Cortex-M7 microarchitecture model for SLOTHY
+
+WARNING: The data in this module is approximate and may contain errors.
+"""
+
+################################### NOTE ###############################################
+###                                                                                  ###
+### WARNING: The data in this module is approximate and may contain errors.          ###
+###          They are _NOT_ an official software optimization guide for Cortex-M7.   ###
+###                                                                                  ###
+### Sources used in constructing this model:                                         ###
+### - ARMv7-M Architecture Reference Manual (ARM DDI 0403E.e)                        ###
+### - https://github.com/jnk0le/random/tree/master/pipeline%20cycle%20test#cortex-m7 ###
+### - https://www.quinapalus.com/cm7cycles.html                                      ###
+########################################################################################
+
+from enum import Enum
+from itertools import product
+from slothy.targets.arm_v7m.arch_v7m import *
+import re
+from sympy import simplify
+
+issue_rate = 2
+llvm_mca_target = "cortex-m7"
+
+
+class ExecutionUnit(Enum):
+    """Enumeration of execution units in Cortex-M7 model"""
+
+    STORE = 0
+    ALU0 = 1
+    ALU1 = 2
+    MAC = 5
+    FPU = 6
+    LOAD0 = 7
+    LOAD1 = 8
+    SIMD = 9
+
+    def __repr__(self):
+        return self.name
+    def ALU(): # pylint: disable=invalid-name
+        return [ExecutionUnit.ALU0, ExecutionUnit.ALU1]
+    def SHIFT(): # pylint: disable=invalid-name
+        return [ExecutionUnit.SHIFT0, ExecutionUnit.SHIFT1]
+    def LOAD(): # pylint: disable=invalid-name
+        return [ExecutionUnit.LOAD0, ExecutionUnit.LOAD1]
+
+
+# Opaque function called by SLOTHY to add further microarchitecture-
+# specific constraints which are not encapsulated by the general framework.
+def add_further_constraints(slothy):
+    if slothy.config.constraints.functional_only:
+        return
+    # add_slot_constraints(slothy)
+    add_st_hazard(slothy)
+
+    add_dsp_slot_constraint(slothy)
+
+def add_dsp_slot_constraint(slothy):
+    slothy.restrict_slots_for_instructions_by_class(
+        [pkhbt, pkhtb, pkhbt_shifted, ubfx_imm, uadd16, usub16, sadd16, ssub16], [0])
+
+# TODO: this seems incorrect
+def add_slot_constraints(slothy):
+    slothy.restrict_slots_for_instructions_by_class(
+        [str_with_imm, str_with_imm_stack, str_with_postinc, strh_with_imm,
+         strh_with_postinc, stm_interval_inc_writeback, str_no_off, str], [1])
+
+
+def add_st_hazard(slothy):
+    def is_st_ld_pair(inst_a, inst_b):
+        return (isinstance(inst_a.inst, ldr_with_imm) or isinstance(inst_a.inst, ldr_with_imm_stack)) \
+            and (isinstance(inst_b.inst, str_with_imm) or isinstance(inst_b.inst, str_with_imm_stack))
+
+    def evaluate_immediate(string_expr):
+        if string_expr is None:
+            return 0
+        string_expr = str(string_expr)
+        return int(simplify(string_expr))
+
+    for t_load, t_store in slothy.get_inst_pairs(cond=is_st_ld_pair):
+        if t_load.is_locked and t_store.is_locked:
+            continue
+
+        ldr_imm = evaluate_immediate(t_load.inst.immediate)
+        str_imm = evaluate_immediate(t_store.inst.immediate)
+
+        if abs(ldr_imm - str_imm) >= 8:
+            continue
+
+        ldr_before_str = slothy._NewBoolVar("")
+        ldr_after_str = slothy._NewBoolVar("")
+        slothy._AddExactlyOne([ldr_before_str, ldr_after_str])
+        slothy._Add(t_load.program_start_var < t_store.program_start_var).OnlyEnforceIf(ldr_before_str)
+        slothy._Add(t_load.program_start_var >= t_store.program_start_var + 8).OnlyEnforceIf(ldr_after_str)
+
+
+# Opaque function called by SLOTHY to add further microarchitecture-
+# specific objectives.
+def has_min_max_objective(config):
+    _ = config
+    return False
+
+
+def get_min_max_objective(slothy):
+    _ = slothy
+    return
+
+
+execution_units = {
+    (
+        ldr,
+        ldr_with_imm,
+        ldr_with_imm_stack,
+        ldr_with_inc_writeback,
+        ldr_with_postinc,
+        ldrb_with_imm,
+        ldrh_with_imm,
+        ldrh_with_postinc,
+        vldr_with_imm, vldr_with_postinc  # TODO: also FPU?
+        ): ExecutionUnit.LOAD(),
+    (
+        Ldrd,
+        ldm_interval,
+        ldm_interval_inc_writeback,
+        vldm_interval_inc_writeback): [ExecutionUnit.LOAD()],
+    (
+        str_with_imm,
+        str_with_imm_stack,
+        str_with_postinc,
+        str_no_off,
+        strh_with_imm,
+        strh_with_postinc,
+        stm_interval_inc_writeback
+    ): [[ExecutionUnit.STORE, ExecutionUnit.MAC]],
+    (
+        movw_imm,
+        movt_imm,
+        adds,
+        add,
+        add_short,
+        add_imm,
+        add_imm_short,
+        sub, subs_imm_short, sub_imm_short,
+        neg_short,
+        log_and,
+        log_or,
+        eor, eor_short, eors, eors_short,
+        bic, bics,
+        cmp, cmp_imm,
+    ): ExecutionUnit.ALU(),
+    (ror, ror_short, rors_short, lsl, asr, asrs): [[ExecutionUnit.ALU0], [ExecutionUnit.ALU1]],
+    (mul, mul_short, smull, smlal, mla, mls, smulwb, smulwt, smultb, smultt,
+     smulbb, smlabt, smlabb, smlatt, smlad, smladx, smuad, smuadx, smmulr): [ExecutionUnit.MAC],
+    (vmov_gpr, vmov_gpr2, vmov_gpr2_dual): [ExecutionUnit.FPU],
+    (uadd16, sadd16, usub16, ssub16): list(map(list, product(ExecutionUnit.ALU(), [ExecutionUnit.SIMD]))),
+    (pkhbt, pkhtb, pkhbt_shifted, ubfx_imm): [[ExecutionUnit.ALU0, ExecutionUnit.SIMD]],
+    (Armv7mShiftedArithmetic): [[ExecutionUnit.ALU0]],
+    (Armv7mShiftedLogical): [[ExecutionUnit.ALU0]],
+}
+inverse_throughput = {
+    (
+        ldr,
+        ldr_with_imm,
+        ldr_with_imm_stack,
+        ldr_with_inc_writeback,
+        ldr_with_postinc,
+        Ldrd,
+        ldrb_with_imm,
+        ldrh_with_imm,
+        ldrh_with_postinc,
+        vldr_with_imm, vldr_with_postinc,  # TODO: double-check
+        # actually not, just placeholder
+        ldm_interval, ldm_interval_inc_writeback, vldm_interval_inc_writeback,
+        movw_imm,
+        movt_imm,
+        adds,
+        add,
+        add_short,
+        add_imm,
+        add_imm_short,
+        add_shifted,
+        sub_shifted,
+        sub_imm_short,
+        subs_imm_short,
+        uadd16, sadd16, usub16, ssub16,
+        mul, mul_short,
+        smull,
+        smlal,
+        mla, mls, smulwb, smulwt, smultb, smultt, smulbb, smlabt, smlabb, smlatt, smlad, smladx, smuad, smuadx, smmulr,
+        neg_short,
+        log_and, log_and_shifted,
+        log_or, log_or_shifted,
+        eor, eor_short, eors, eors_short,
+        eor_shifted,
+        bic, bics,
+        bic_shifted,
+        ror, ror_short, rors_short, lsl, asr, asrs,
+        cmp, cmp_imm,
+        vmov_gpr,
+        vmov_gpr2, vmov_gpr2_dual,  # verify for dual
+        pkhbt, pkhtb, pkhbt_shifted, ubfx_imm,
+        str_with_imm,
+        str_with_imm_stack,
+        str_with_postinc,
+        str_no_off,
+        strh_with_imm,
+        strh_with_postinc,
+
+    ): 1,
+    (
+        stm_interval_inc_writeback,  # actually not, just placeholder
+        vmov_gpr2_dual): 2
+}
+
+default_latencies = {
+    (
+        movw_imm,
+        movt_imm,
+        adds,
+        add,
+        add_short,
+        add_imm,
+        add_imm_short,
+        add_shifted,
+        sub_shifted,
+        sub_imm_short,
+        subs_imm_short,
+        uadd16, sadd16, usub16, ssub16,
+        neg_short,
+        log_and, log_and_shifted,
+        log_or, log_or_shifted,
+        eor, eor_short, eors, eors_short,
+        bic, bics,
+        bic_shifted,
+        ror, ror_short, rors_short, lsl, asr, asrs,
+        cmp, cmp_imm,
+        pkhbt, pkhtb, pkhbt_shifted, ubfx_imm,
+        vldr_with_imm, vldr_with_postinc,  # according to Jan
+        # actually not, just placeholder
+        ldm_interval, ldm_interval_inc_writeback, vldm_interval_inc_writeback,
+        str_with_imm,
+        str_with_imm_stack,
+        str_with_postinc,
+        str_no_off,
+        strh_with_imm,
+        strh_with_postinc,
+    ): 1,
+    (
+        mul, mul_short,
+        smull,
+        smlal,
+        mla, mls, smulwb, smulwt, smultb, smultt, smulbb, smlabt, smlabb, smlatt, smlad, smladx, smuad, smuadx, smmulr,
+        # TODO: Verify load latency
+        stm_interval_inc_writeback,  # actually not, just placeholder
+        ldr,
+        ldr_with_imm,
+        ldr_with_imm_stack,
+        ldr_with_inc_writeback,
+        ldr_with_postinc,
+        ldrb_with_imm,
+        ldrh_with_imm,
+        ldrh_with_postinc,
+        eor_shifted
+    ): 2,
+    (Ldrd): 3,
+    (vmov_gpr2, vmov_gpr2_dual): 3,
+    (vmov_gpr): 1
+}
+
+
+def get_latency(src, out_idx, dst):
+    _ = out_idx  # out_idx unused
+
+    instclass_src = find_class(src)
+    instclass_dst = find_class(dst)
+
+    latency = lookup_multidict(default_latencies, src)
+
+    # Forwarding path to MAC instructions
+    if instclass_dst in [mla, mls, smlabb, smlabt, smlatt] and src.args_out[0] == dst.args_in[2]:
+        latency =  latency - 1
+
+    if instclass_dst in [smlal] and \
+            (src.args_out[0] == dst.args_in_out[0] or src.args_out[0] == dst.args_in_out[1]):
+        latency = latency - 1
+
+    # Multiply accumulate chain latency is 1
+    if instclass_src in [smlal] and instclass_dst in [smlal] and \
+            src.args_in_out[0] == dst.args_in_out[0] and \
+            src.args_in_out[1] == dst.args_in_out[1]:
+        return 1
+
+    # Load latency is 1 cycle if the destination is an arithmetic/logical instruction
+    if instclass_src in [ldr_with_imm, ldr_with_imm_stack, ldr_with_inc_writeback] and \
+    sum([issubclass(instclass_dst, pc) for pc in [Armv7mBasicArithmetic, Armv7mLogical]]) and \
+       src.args_out[0] in dst.args_in:
+        latency = latency - 1
+
+    # Shifted operand needs to be available one cycle early
+    # TODO: verify how this applies to ubfx with imm
+    if sum([issubclass(instclass_dst, pc) for pc in [Armv7mShiftedLogical, Armv7mShiftedArithmetic, pkhbt, pkhtb, pkhbt_shifted]]) and \
+       dst.args_in[1] in src.args_out or \
+            sum([issubclass(instclass_dst, pc) for pc in [ubfx_imm]]) and \
+            dst.args_in[0] in src.args_out:
+        return latency + 1
+
+
+    # Load and store multiples take a long time to complete
+    if instclass_src in [ldm_interval, ldm_interval_inc_writeback, stm_interval_inc_writeback, vldm_interval_inc_writeback]:
+        latency = (src.range_end - src.range_start) + 1
+
+    # Can always store result in the same cycle
+    # TODO: double-check this
+    if dst.is_store():
+        return 0
+
+    return latency
+
+
+def get_units(src):
+    units = lookup_multidict(execution_units, src)
+
+
+    def evaluate_immediate(string_expr):
+        if string_expr is None:
+            return 0
+        string_expr = str(string_expr)
+        return int(simplify(string_expr))
+
+    # The Cortex-M7 has two memory banks
+    # If two loads use the same memory bank, they cannot dual issue
+    # There are no constraints which load can go to which issue slot
+    # Approximiation: Only look at immediates, i.e., assume all pointers are aligned to 8 bytes
+    if src.is_ldr():
+        imm = evaluate_immediate(src.immediate)
+
+        if (imm % 8) // 4 == 0:
+            return [ExecutionUnit.LOAD0]
+        else:
+            return [ExecutionUnit.LOAD1]
+
+    if isinstance(units, list):
+        return units
+    return [units]
+
+def get_inverse_throughput(src):
+    itp = lookup_multidict(inverse_throughput, src)
+    if find_class(src) in [ldm_interval, ldm_interval_inc_writeback, stm_interval_inc_writeback, vldm_interval_inc_writeback]:
+        itp = (src.range_end - src.range_start) + 1
+
+    return itp
diff --git a/slothy/targets/query.py b/slothy/targets/query.py
index 7e4b27c6..dbebf7a7 100644
--- a/slothy/targets/query.py
+++ b/slothy/targets/query.py
@@ -30,6 +30,9 @@
 and microarchitecture models for SLOTHY.
 """
 
+from slothy.targets.arm_v7m import arch_v7m as Arch_Armv7M
+from slothy.targets.arm_v7m import cortex_m7 as Target_CortexM7
+
 from slothy.targets.arm_v81m import arch_v81m as Arch_Armv81M
 from slothy.targets.arm_v81m import cortex_m55r1 as Target_CortexM55r1
 from slothy.targets.arm_v81m import cortex_m85r1 as Target_CortexM85r1
@@ -50,12 +53,14 @@ class UnknownTarget(Exception):
 class Archery:
     """This is a small helper class for querying architectures"""
 
-    _archs = { "Arm_v81M" : Arch_Armv81M,
+    _archs = { "Arm_v7M" : Arch_Armv7M,
+               "Arm_v81M" : Arch_Armv81M,
                "Arm_AArch64" : AArch64_Neon }
 
     _targets = { "Arm_Cortex_M55" : Target_CortexM55r1,
                  "Arm_Cortex_M85" : Target_CortexM85r1,
                  "Arm_Helium_Experimental" : Target_Helium_Experimental,
+                 "Arm_Cortex_M7" : Target_CortexM7,
                  "Arm_Cortex_A55" : Target_CortexA55,
                  "Arm_Cortex_A72_frontend" : Target_CortexA72_Frontend,
                  "Arm_Neoverse_N1_experimental" : Target_NeoverseN1_Experimental,

From a8a4fbb3731869b2534bd0b866bd7877bcc25cb2 Mon Sep 17 00:00:00 2001
From: Amin Abdulrahman <amin@abdulrahman.de>
Date: Mon, 2 Dec 2024 12:05:30 +0100
Subject: [PATCH 2/5] Armv7m: Remove stack register types

---
 slothy/targets/arm_v7m/arch_v7m.py | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/slothy/targets/arm_v7m/arch_v7m.py b/slothy/targets/arm_v7m/arch_v7m.py
index 43154983..0e9eb014 100644
--- a/slothy/targets/arm_v7m/arch_v7m.py
+++ b/slothy/targets/arm_v7m/arch_v7m.py
@@ -14,10 +14,8 @@
 class RegisterType(Enum):
     GPR = 1
     FPR = 2
-    STACK_FPR = 3
-    STACK_GPR = 4
-    FLAGS = 5
-    HINT = 6
+    FLAGS = 3
+    HINT = 4
 
     def __str__(self):
         return self.name
@@ -34,9 +32,6 @@ def spillable(reg_type):
     def list_registers(reg_type, only_extra=False, only_normal=False, with_variants=False):
         """Return the list of all registers of a given type"""
 
-        stack_locations  = [ f"STACK{i}"  for i in range(8) ]
-        fpstack_locations  = [ f"STACK{i}"  for i in range(8) ]
-
         gprs_normal  = [ f"r{i}" for i in range(15) ]
         fprs_normal  = [ f"s{i}" for i in range(31) ]
 
@@ -59,9 +54,7 @@ def list_registers(reg_type, only_extra=False, only_normal=False, with_variants=
             fprs += fprs_extra
 
         return { RegisterType.GPR       : gprs,
-                 RegisterType.STACK_GPR : stack_locations,
                  RegisterType.FPR       : fprs,
-                 RegisterType.STACK_FPR : fpstack_locations,
                  RegisterType.HINT      : hints,
                  RegisterType.FLAGS     : flags}[reg_type]
 
@@ -89,9 +82,7 @@ def is_renamed(ty):
     def from_string(string):
         """Find registe type from string"""
         string = string.lower()
-        return { "fprstack"    : RegisterType.STACK_FPR,
-                 "stack"     : RegisterType.STACK_GPR,
-                 "fpr"      : RegisterType.FPR,
+        return { "fpr"      : RegisterType.FPR,
                  "gpr"       : RegisterType.GPR,
                  "hint"      : RegisterType.HINT,
                  "flags"     : RegisterType.FLAGS}.get(string,None)

From 00b2a6fd4499344504b89184659899fe1c6343d9 Mon Sep 17 00:00:00 2001
From: "Matthias J. Kannwischer" <matthias@kannwischer.eu>
Date: Thu, 28 Nov 2024 16:03:39 +0800
Subject: [PATCH 3/5] remove new_fixup from software pipelining for M7

---
 slothy/targets/arm_v7m/arch_v7m.py | 54 ++++++++++++++++--------------
 1 file changed, 28 insertions(+), 26 deletions(-)

diff --git a/slothy/targets/arm_v7m/arch_v7m.py b/slothy/targets/arm_v7m/arch_v7m.py
index 0e9eb014..1ce30e4f 100644
--- a/slothy/targets/arm_v7m/arch_v7m.py
+++ b/slothy/targets/arm_v7m/arch_v7m.py
@@ -154,25 +154,27 @@ def start(self, loop_cnt, indentation=0, fixup=0, unroll=1, jump_if_empty=None,
         logging.debug(f"Loop counter {loop_cnt} is incremented by {inc_per_iter} per iteration")
         # Check whether instructions modifying the loop count moved to
         # pre/postamble and adjust the fixup based on that.
-        new_fixup = 0
-        if postamble_code is not None:
-            new_fixup = 0
-            for l in postamble_code:
-                if l.text == "":
-                    continue
-                inst = Instruction.parser(l)
-                if loop_cnt in inst[0].args_in_out and inst[0].increment is not None:
-                    new_fixup = new_fixup + simplify(inst[0].increment)
-
-        if new_fixup != 0 or fixup != 0:
+        # new_fixup = 0
+        # if postamble_code is not None:
+        #     new_fixup = 0
+        #     for l in postamble_code:
+        #         if l.text == "":
+        #             continue
+        #         inst = Instruction.parser(l)
+        #         if loop_cnt in inst[0].args_in_out and inst[0].increment is not None:
+        #             new_fixup = new_fixup + simplify(inst[0].increment)
+
+        # if new_fixup != 0 or fixup != 0:
+        if fixup != 0:
             yield f"{indent}push {{{self.additional_data['end']}}}"
             yield f"{indent}vmov {self.additional_data['end']}, {self.additional_data['endf']}"
 
-        if new_fixup != 0:
-            yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{new_fixup}"
+        # if new_fixup != 0:
+        #     yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{new_fixup}"
         if fixup != 0:
             yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{fixup*inc_per_iter}"
-        if new_fixup != 0 or fixup != 0:
+        #if new_fixup != 0 or fixup != 0:
+        if fixup != 0:
             yield f"{indent}vmov {self.additional_data['endf']}, {self.additional_data['end']}"
             yield f"{indent}pop {{{self.additional_data['end']}}}"
         if jump_if_empty is not None:
@@ -221,18 +223,18 @@ def start(self, loop_cnt, indentation=0, fixup=0, unroll=1, jump_if_empty=None,
 
         # Check whether instructions modifying the loop count moved to
         # pre/postamble and adjust the fixup based on that.
-        new_fixup = 0
-        if postamble_code is not None:
-            new_fixup = 0
-            for l in postamble_code:
-                if l.text == "":
-                    continue
-                inst = Instruction.parser(l)
-                if loop_cnt in inst[0].args_in_out and inst[0].increment is not None:
-                    new_fixup = new_fixup + simplify(inst[0].increment)
-
-        if new_fixup != 0:
-            yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{new_fixup}"
+        # new_fixup = 0
+        # if postamble_code is not None:
+        #     new_fixup = 0
+        #     for l in postamble_code:
+        #         if l.text == "":
+        #             continue
+        #         inst = Instruction.parser(l)
+        #         if loop_cnt in inst[0].args_in_out and inst[0].increment is not None:
+        #             new_fixup = new_fixup + simplify(inst[0].increment)
+
+        # if new_fixup != 0:
+        #     yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{new_fixup}"
 
         if fixup != 0:
             yield f"{indent}sub {self.additional_data['end']}, {self.additional_data['end']}, #{fixup*inc_per_iter}"

From 528321cb4deb9d4941cb2697894e208f85e3a58b Mon Sep 17 00:00:00 2001
From: Amin Abdulrahman <amin@abdulrahman.de>
Date: Mon, 2 Dec 2024 13:46:28 +0100
Subject: [PATCH 4/5] Armv7m: Add vmov cmp loop example

---
 example.py                                  | 18 ++++++++++
 examples/opt/armv7m/armv7m_simple0_opt_m7.s | 38 ++++++++++-----------
 examples/opt/armv7m/loop_vmov_cmp_opt_m7.s  | 31 +++++++++++++++++
 3 files changed, 68 insertions(+), 19 deletions(-)
 create mode 100644 examples/opt/armv7m/loop_vmov_cmp_opt_m7.s

diff --git a/example.py b/example.py
index 6e38f856..9f2a360e 100644
--- a/example.py
+++ b/example.py
@@ -688,6 +688,23 @@ def core(self,slothy):
         slothy.config.variable_size=True
         slothy.config.outputs = ["r6"]
         slothy.optimize_loop("start")
+        
+class Armv7mLoopVmovCmp(Example):
+    def __init__(self, var="", arch=Arch_Armv7M, target=Target_CortexM7):
+        name = "loop_vmov_cmp"
+        infile = name
+
+        if var != "":
+            name += f"_{var}"
+            infile += f"_{var}"
+        name += f"_{target_label_dict[target]}"
+
+        super().__init__(infile, name, rename=True, arch=arch, target=target)
+
+    def core(self,slothy):
+        slothy.config.variable_size=True
+        slothy.config.outputs = ["r6"]
+        slothy.optimize_loop("start")
 
 class ntt_kyber_123_4567(Example):
     def __init__(self, var="", arch=AArch64_Neon, target=Target_CortexA55, timeout=None):
@@ -1486,6 +1503,7 @@ def main():
                  LoopLe(),
                  Armv7mLoopSubs(),
                  Armv7mLoopCmp(),
+                 Armv7mLoopVmovCmp(),
 
                  CRT(),
 
diff --git a/examples/opt/armv7m/armv7m_simple0_opt_m7.s b/examples/opt/armv7m/armv7m_simple0_opt_m7.s
index 87fd5e61..98abb396 100644
--- a/examples/opt/armv7m/armv7m_simple0_opt_m7.s
+++ b/examples/opt/armv7m/armv7m_simple0_opt_m7.s
@@ -1,24 +1,24 @@
 
         start:
-                                       // Instructions:    6
-                                       // Expected cycles: 5
-                                       // Expected IPC:    1.20
-                                       //
-                                       // Cycle bound:     5.0
-                                       // IPC bound:       1.20
-                                       //
-                                       // Wall time:     0.01s
-                                       // User time:     0.01s
-                                       //
-                                       // ----- cycle (expected) ------>
-                                       // 0                        25
-                                       // |------------------------|----
-        ldr r7, [r0, #4]               // *.............................
-        add r7, r2, r7                 // .*............................
-        eor.w r12, r7, r3              // ..*...........................
-        smlabt r12, r2, r2, r12        // ..*...........................
-        asrs r3, r12, #1               // ....*.........................
-        str r3, [r0, #4]               // ....*.........................
+                                      // Instructions:    6
+                                      // Expected cycles: 5
+                                      // Expected IPC:    1.20
+                                      //
+                                      // Cycle bound:     5.0
+                                      // IPC bound:       1.20
+                                      //
+                                      // Wall time:     0.02s
+                                      // User time:     0.02s
+                                      //
+                                      // ----- cycle (expected) ------>
+                                      // 0                        25
+                                      // |------------------------|----
+        ldr r6, [r0, #4]              // *.............................
+        add r6, r2, r6                // .*............................
+        eor.w r3, r6, r3              // ..*...........................
+        smlabt r12, r2, r2, r3        // ..*...........................
+        asrs r3, r12, #1              // ....*.........................
+        str r3, [r0, #4]              // ....*.........................
 
                                       // ------ cycle (expected) ------>
                                       // 0                        25
diff --git a/examples/opt/armv7m/loop_vmov_cmp_opt_m7.s b/examples/opt/armv7m/loop_vmov_cmp_opt_m7.s
new file mode 100644
index 00000000..c75f8b9b
--- /dev/null
+++ b/examples/opt/armv7m/loop_vmov_cmp_opt_m7.s
@@ -0,0 +1,31 @@
+/* For example, r5 represents an address where we will stop iterating and r6 is
+the actual pointer which is incremented inside the loop. */
+
+mov.w r6, #0
+add.w r5, r6, #64
+vmov s0, r5
+
+start:
+                              // Instructions:    1
+                              // Expected cycles: 1
+                              // Expected IPC:    1.00
+                              //
+                              // Cycle bound:     1.0
+                              // IPC bound:       1.00
+                              //
+                              // Wall time:     0.02s
+                              // User time:     0.02s
+                              //
+                              // ----- cycle (expected) ------>
+                              // 0                        25
+                              // |------------------------|----
+        add r6, r6, #4        // *.............................
+
+                               // ------ cycle (expected) ------>
+                               // 0                        25
+                               // |------------------------|-----
+        // add r6, r6, #4      // *..............................
+
+        vmov r5, s0
+        cmp r6, r5
+        bne start
\ No newline at end of file

From 98e876cfb567a104765e54d1285ac7a1773f32ad Mon Sep 17 00:00:00 2001
From: Amin Abdulrahman <amin@abdulrahman.de>
Date: Mon, 2 Dec 2024 13:53:46 +0100
Subject: [PATCH 5/5] Armv7m: Add comments explaining loop types

---
 slothy/targets/arm_v7m/arch_v7m.py | 49 ++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/slothy/targets/arm_v7m/arch_v7m.py b/slothy/targets/arm_v7m/arch_v7m.py
index 1ce30e4f..fd0dc73b 100644
--- a/slothy/targets/arm_v7m/arch_v7m.py
+++ b/slothy/targets/arm_v7m/arch_v7m.py
@@ -123,6 +123,28 @@ def unconditional(lbl):
 
 
 class VmovCmpLoop(Loop):
+    """
+    Loop ending in a vmov, a compare, and a branch.
+    
+    The modification to the value we compare against happens inside the loop
+    body. The value that is being compared to is stashed to a floating point
+    register before the loop starts and therefore needs to be recovered before
+    the comparison. 
+    
+    WARNING: This type of loop is experimental as slothy has no knowledge about
+    what happens inside the loop boundary! Especially, a register is written
+    inside the boundary which may be used for renaming by slothy. Use with
+    caution.
+
+    Example:
+    ```
+           loop_lbl:
+               {code}
+               vmov <end>, <endf>
+               cmp <cnt>, <end>
+               (cbnz|bnz|bne) loop_lbl
+    ``` where cnt is the loop counter in lr.
+    """
     def __init__(self, lbl="lbl", lbl_start="1", lbl_end="2", loop_init="lr") -> None:
         super().__init__(lbl_start=lbl_start, lbl_end=lbl_end, loop_init=loop_init)
         self.lbl = lbl
@@ -193,6 +215,21 @@ def end(self, other, indentation=0):
         yield f'{indent}bne {lbl_start}'
 
 class CmpLoop(Loop):
+    """
+    Loop ending in a compare and a branch.
+    The modification to the value we compare against happens inside the loop body.
+    WARNING: This type of loop is experimental as slothy has no knowledge about 
+    what happens inside the loop boundary! Use with caution.
+
+    Example:
+    ```
+           loop_lbl:
+               {code}
+               cmp <cnt>, <end>
+               (cbnz|bnz|bne) loop_lbl
+    ```
+    where cnt is the loop counter in lr.
+    """
     def __init__(self, lbl="lbl", lbl_start="1", lbl_end="2", loop_init="lr") -> None:
         super().__init__(lbl_start=lbl_start, lbl_end=lbl_end, loop_init=loop_init)
         self.lbl_regex = r"^\s*(?P<label>\w+)\s*:(?P<remainder>.*)$"
@@ -254,6 +291,18 @@ def end(self, other, indentation=0):
         yield f'{indent}bne {lbl_start}'
 
 class SubsLoop(Loop):
+    """
+    Loop ending in a flag setting subtraction and a branch.
+
+    Example:
+    ```
+           loop_lbl:
+               {code}
+               sub[s] <cnt>, <cnt>, #1
+               (cbnz|bnz|bne) loop_lbl
+    ```
+    where cnt is the loop counter in lr.
+    """
     def __init__(self, lbl_start="1", lbl_end="2", loop_init="lr") -> None:
         super().__init__(lbl_start=lbl_start, lbl_end=lbl_end, loop_init=loop_init)
         self.lbl_regex = r"^\s*(?P<label>\w+)\s*:(?P<remainder>.*)$"