From 852dd779601e0e581024689edea13f58365aba01 Mon Sep 17 00:00:00 2001 From: "Matthias J. Kannwischer" Date: Tue, 10 Dec 2024 15:42:03 +0800 Subject: [PATCH 1/5] fix setter of config.selftest --- slothy/core/config.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/slothy/core/config.py b/slothy/core/config.py index bdf5b570..083983ed 100644 --- a/slothy/core/config.py +++ b/slothy/core/config.py @@ -1303,8 +1303,6 @@ def variable_size(self,val): self._variable_size = val @selftest.setter def selftest(self,val): - if hasattr(self.arch, "Checker") is False: - raise InvalidConfig("Trying to enable checker, but architecture model does not seem to support it") self._selftest = val @selftest_iterations.setter def selftest_iterations(self,val): From 898c9a77eba6335198a20aa5b289ec84808c6654 Mon Sep 17 00:00:00 2001 From: "Matthias J. Kannwischer" Date: Sat, 14 Dec 2024 11:50:13 +0800 Subject: [PATCH 2/5] skip over hint registers in selftest --- slothy/helper.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/slothy/helper.py b/slothy/helper.py index 4ef6ebf0..1a33d49a 100644 --- a/slothy/helper.py +++ b/slothy/helper.py @@ -1371,6 +1371,9 @@ def run_code(code, txt=None): # Check that callee-saved registers are the same for r in output_registers: + # skip over hints + if r.startswith("hint_"): + continue if final_regs_old[r] != final_regs_new[r]: raise SelfTestException(f"Selftest failed: Register mismatch for {r}: {hex(final_regs_old[r])} != {hex(final_regs_new[r])}") From 05b2b64fdd5f20f2943757facc623fc79f4efdb4 Mon Sep 17 00:00:00 2001 From: "Matthias J. Kannwischer" Date: Sat, 14 Dec 2024 14:50:16 +0800 Subject: [PATCH 3/5] disable selftest if code contains symbolic registers --- slothy/core/core.py | 8 ++++++-- slothy/core/dataflow.py | 12 ++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/slothy/core/core.py b/slothy/core/core.py index ccdda70d..2beba96f 100644 --- a/slothy/core/core.py +++ b/slothy/core/core.py @@ -838,13 +838,17 @@ def selftest(self, log): log.warning("Selftest not supported on target architecture") return + tree = DFG(self._orig_code, log, DFGConfig(self.config, outputs=self.outputs)) + + if tree.has_symbolic_registers(): + log.info("Skipping selftest as input contains symbolic registers.") + return + log.info(f"Running selftest ({self._config.selftest_iterations} iterations)...") address_gprs = self._config.selftest_address_gprs if address_gprs is None: # Try to infer which registes need to be pointers - log_addresses = log.getChild("infer_address_gprs") - tree = DFG(self._orig_code, log_addresses, DFGConfig(self.config, outputs=self.outputs)) # Look for load/store instructions and remember addresses addresses = set() for t in tree.nodes: diff --git a/slothy/core/dataflow.py b/slothy/core/dataflow.py index 2e333dd5..a29ef122 100644 --- a/slothy/core/dataflow.py +++ b/slothy/core/dataflow.py @@ -763,6 +763,18 @@ def update_inputs(self): for i,v in enumerate(t.src_in_out): t.inst.args_in_out[i] = v.reduce().name() + def has_symbolic_registers(self): + rt = self.config._arch.RegisterType + for i in self.nodes: + instr = i.inst + for out, ty in zip(instr.args_out, instr.arg_types_out): + if out not in rt.list_registers(ty): + return True + for inout, ty in zip(instr.args_in_out, instr.arg_types_in_out): + if inout not in rt.list_registers(ty): + return True + return False + def ssa(self, filter_func=None): """Transform data flow graph into single static assignment (SSA) form.""" # Go through non-virtual instruction nodes and assign unique names to From 0791dc66ef314503f8e2f051eb676f27ddbd4b3d Mon Sep 17 00:00:00 2001 From: "Matthias J. Kannwischer" Date: Thu, 12 Dec 2024 16:49:02 +0800 Subject: [PATCH 4/5] fix typo in unicorn error handler --- slothy/helper.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/slothy/helper.py b/slothy/helper.py index 1a33d49a..494d1bf2 100644 --- a/slothy/helper.py +++ b/slothy/helper.py @@ -1337,7 +1337,7 @@ def run_code(code, txt=None): except: log.error("Failed to emulate code using unicorn engine") log.error("Code") - log.error(SouceLine.write_multiline(code)) + log.error(SourceLine.write_multiline(code)) final_register_contents = {} for r in regs: From 549bc31f1386da213093e060e616b9e4df195671 Mon Sep 17 00:00:00 2001 From: "Matthias J. Kannwischer" Date: Sun, 15 Dec 2024 10:58:19 +0800 Subject: [PATCH 5/5] add missing slothy annotations re dependencies through memory --- examples/naive/armv7m/armv7m_simple0.s | 16 +-- examples/opt/armv7m/armv7m_simple0_opt_m7.s | 112 ++++++++++---------- 2 files changed, 64 insertions(+), 64 deletions(-) diff --git a/examples/naive/armv7m/armv7m_simple0.s b/examples/naive/armv7m/armv7m_simple0.s index 937c22f2..311b016d 100644 --- a/examples/naive/armv7m/armv7m_simple0.s +++ b/examples/naive/armv7m/armv7m_simple0.s @@ -1,32 +1,32 @@ start: -ldr r1, [r0, #4] +ldr r1, [r0, #4] // @slothy:reads=a add r1, r2,r1 eor.w r1,r1, r3 smlabt r3,r2, r2, r1 asrs r3, r3,#1 -str r3, [r0,#4] +str r3, [r0,#4] // @slothy:writes=a -ldm r0, {r1-r2,r14} +ldm r0, {r1-r2,r14} // @slothy:reads=a add r1, r2,r1 eor.w r1,r1, r14 smlabt r3,r2, r2, r1 asrs r3, r3,#1 -str r3, [r0,#4] +str r3, [r0,#4] // @slothy:writes=a -ldm r0, {r1-r3} +ldm r0, {r1-r3} // @slothy:reads=a add r1, r2,r1 eor.w r1,r1, r3 smlabt r3,r2, r2, r1 asrs r3, r3,#1 -str r3, [r0,#4] +str r3, [r0,#4] // @slothy:writes=a -ldm r0, {r1,r2,r3} +ldm r0, {r1,r2,r3} // @slothy:reads=a add r1, r2,r1 eor.w r1,r1, r3 smlabt r3,r2, r2, r1 asrs r3, r3,#1 -str r3, [r0,#4] +str r3, [r0,#4] // @slothy:writes=a end: \ No newline at end of file diff --git a/examples/opt/armv7m/armv7m_simple0_opt_m7.s b/examples/opt/armv7m/armv7m_simple0_opt_m7.s index b88c82bc..24d327fe 100644 --- a/examples/opt/armv7m/armv7m_simple0_opt_m7.s +++ b/examples/opt/armv7m/armv7m_simple0_opt_m7.s @@ -1,42 +1,42 @@ start: - // Instructions: 24 - // Expected cycles: 14 - // Expected IPC: 1.71 - // - // Cycle bound: 14.0 - // IPC bound: 1.71 - // - // Wall time: 0.40s - // User time: 0.40s - // - // ----- cycle (expected) ------> - // 0 25 - // |------------------------|---- - ldr r10, [r0, #4] // *............................. - ldm r0, {r1,r7,r14} // .*............................ - add r10, r2, r10 // .*............................ - eor.w r10, r10, r3 // ..*........................... - smlabt r2, r2, r2, r10 // ..*........................... - ldm r0, {r10,r11,r12} // ....*......................... - add r1, r7, r1 // ....*......................... - eor.w r1, r1, r14 // .....*........................ - smlabt r6, r7, r7, r1 // .....*........................ - asrs r1, r2, #1 // ......*....................... - str r1, [r0, #4] // ......*....................... - add r4, r11, r10 // .......*...................... - ldm r0, {r1,r2,r14} // .......*...................... - asrs r10, r6, #1 // ........*..................... - eor.w r6, r4, r12 // ........*..................... - smlabt r11, r11, r11, r6 // .........*.................... - add r1, r2, r1 // ..........*................... - str r10, [r0, #4] // ..........*................... - eor.w r1, r1, r14 // ...........*.................. - smlabt r7, r2, r2, r1 // ...........*.................. - asrs r1, r11, #1 // ............*................. - str r1, [r0, #4] // ............*................. - asrs r3, r7, #1 // .............*................ - str r3, [r0, #4] // .............*................ + // Instructions: 24 + // Expected cycles: 26 + // Expected IPC: 0.92 + // + // Cycle bound: 26.0 + // IPC bound: 0.92 + // + // Wall time: 0.14s + // User time: 0.14s + // + // ----- cycle (expected) ------> + // 0 25 + // |------------------------|---- + ldr r1, [r0, #4] // *............................. // @slothy:reads=a + add r11, r2, r1 // .*............................ + eor.w r12, r11, r3 // ..*........................... + smlabt r4, r2, r2, r12 // ..*........................... + asrs r9, r4, #1 // ....*......................... + str r9, [r0, #4] // ....*......................... // @slothy:writes=a + ldm r0, {r2,r6,r14} // .....*........................ // @slothy:reads=a + add r3, r6, r2 // ........*..................... + eor.w r1, r3, r14 // .........*.................... + smlabt r6, r6, r6, r1 // .........*.................... + asrs r3, r6, #1 // ...........*.................. + str r3, [r0, #4] // ...........*.................. // @slothy:writes=a + ldm r0, {r5,r7,r8} // ............*................. // @slothy:reads=a + add r1, r7, r5 // ...............*.............. + eor.w r9, r1, r8 // ................*............. + smlabt r5, r7, r7, r9 // ................*............. + asrs r5, r5, #1 // ..................*........... + str r5, [r0, #4] // ..................*........... // @slothy:writes=a + ldm r0, {r1,r2,r10} // ...................*.......... // @slothy:reads=a + add r4, r2, r1 // ......................*....... + eor.w r11, r4, r10 // .......................*...... + smlabt r3, r2, r2, r11 // .......................*...... + asrs r3, r3, #1 // .........................*.... + str r3, [r0, #4] // .........................*.... // @slothy:writes=a // ------ cycle (expected) ------> // 0 25 @@ -45,25 +45,25 @@ // add r1, r2,r1 // .*............................. // eor.w r1,r1, r3 // ..*............................ // smlabt r3,r2, r2, r1 // ..*............................ - // asrs r3, r3,#1 // ......*........................ - // str r3, [r0,#4] // ......*........................ - // ldm r0, {r1-r2,r14} // ....*.......................... - // add r1, r2,r1 // .......*....................... - // eor.w r1,r1, r14 // ........*...................... + // asrs r3, r3,#1 // ....*.......................... + // str r3, [r0,#4] // ....*.......................... + // ldm r0, {r1-r2,r14} // .....*......................... + // add r1, r2,r1 // ........*...................... + // eor.w r1,r1, r14 // .........*..................... // smlabt r3,r2, r2, r1 // .........*..................... - // asrs r3, r3,#1 // ............*.................. - // str r3, [r0,#4] // ............*.................. - // ldm r0, {r1-r3} // .*............................. - // add r1, r2,r1 // ....*.......................... - // eor.w r1,r1, r3 // .....*......................... - // smlabt r3,r2, r2, r1 // .....*......................... - // asrs r3, r3,#1 // ........*...................... - // str r3, [r0,#4] // ..........*.................... - // ldm r0, {r1,r2,r3} // .......*....................... - // add r1, r2,r1 // ..........*.................... - // eor.w r1,r1, r3 // ...........*................... - // smlabt r3,r2, r2, r1 // ...........*................... - // asrs r3, r3,#1 // .............*................. - // str r3, [r0,#4] // .............*................. + // asrs r3, r3,#1 // ...........*................... + // str r3, [r0,#4] // ...........*................... + // ldm r0, {r1-r3} // ............*.................. + // add r1, r2,r1 // ...............*............... + // eor.w r1,r1, r3 // ................*.............. + // smlabt r3,r2, r2, r1 // ................*.............. + // asrs r3, r3,#1 // ..................*............ + // str r3, [r0,#4] // ..................*............ + // ldm r0, {r1,r2,r3} // ...................*........... + // add r1, r2,r1 // ......................*........ + // eor.w r1,r1, r3 // .......................*....... + // smlabt r3,r2, r2, r1 // .......................*....... + // asrs r3, r3,#1 // .........................*..... + // str r3, [r0,#4] // .........................*..... end: