-
Notifications
You must be signed in to change notification settings - Fork 0
/
CA_Project.qsf
90 lines (88 loc) · 4.73 KB
/
CA_Project.qsf
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 08:51:03 February 05, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CA_Project_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY CA_Project
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:51:03 FEBRUARY 05, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "D:/Desktop/CE/Courses/(3)Computer_Architecture/Processor_Simulation/Waveform.vwf"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name QIP_FILE fdmsakflmcxkmsd.qip
set_global_assignment -name SOURCE_FILE fdmsakflmcxkmsd.cmp
set_global_assignment -name QIP_FILE lpm_shift_to_right.qip
set_global_assignment -name SOURCE_FILE lpm_shift_to_right.cmp
set_global_assignment -name QIP_FILE lpm_add_to_129.qip
set_global_assignment -name SOURCE_FILE lpm_add_to_129.cmp
set_global_assignment -name BDF_FILE Block2.bdf
set_global_assignment -name BDF_FILE CA_Project.bdf
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_add_sub0.qip
set_global_assignment -name QIP_FILE altfp_compare0.qip
set_global_assignment -name QIP_FILE lpm_compare0.qip
set_global_assignment -name QIP_FILE lpm_constant0.qip
set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_mux1.qip
set_global_assignment -name SOURCE_FILE lpm_shiftreg0.cmp
set_global_assignment -name SOURCE_FILE lpm_mux1.cmp
set_global_assignment -name SOURCE_FILE lpm_mux0.cmp
set_global_assignment -name SOURCE_FILE lpm_constant0.cmp
set_global_assignment -name SOURCE_FILE lpm_compare0.cmp
set_global_assignment -name SOURCE_FILE lpm_add_sub0.cmp
set_global_assignment -name SOURCE_FILE altfp_compare0.cmp
set_global_assignment -name QIP_FILE RAM_DUAL_PORT.qip
set_global_assignment -name QIP_FILE ROM.qip
set_global_assignment -name QIP_FILE RAM.qip
set_global_assignment -name QIP_FILE INSTR_ROM.qip
set_global_assignment -name QIP_FILE CTRL_ROM.qip
set_global_assignment -name QIP_FILE ADD4.qip
set_global_assignment -name QIP_FILE zero.qip
set_global_assignment -name QIP_FILE one.qip
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name QIP_FILE lpm_decode0.qip
set_global_assignment -name QIP_FILE alu_forward_compare_a.qip
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_formal_verification
set_global_assignment -name QIP_FILE my_add_sub.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top