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ALU_COMPARE_syn.v
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// megafunction wizard: %LPM_COMPARE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COMPARE
// ============================================================
// File Name: ALU_COMPARE.v
// Megafunction Name(s):
// LPM_COMPARE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//lpm_compare DEVICE_FAMILY="Cyclone IV GX" LPM_REPRESENTATION="SIGNED" LPM_WIDTH=32 ageb alb dataa datab
//VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lut 54
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ALU_COMPARE_cmpr
(
ageb,
alb,
dataa,
datab) /* synthesis synthesis_clearbox=1 */;
output ageb;
output alb;
input [31:0] dataa;
input [31:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [31:0] dataa;
tri0 [31:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg wire_alb_int;
wire [31:0] dataa_int;
wire [31:0] datab_int;
assign
dataa_int = {~dataa[31:31], dataa[30:0]},
datab_int = {~datab[31:31], datab[30:0]};
always @(dataa_int or datab_int)
begin
if (dataa_int < datab_int)
begin
wire_alb_int = 1'b1;
end
else
begin
wire_alb_int = 1'b0;
end
end
assign
alb = wire_alb_int,
ageb = !wire_alb_int;
endmodule //ALU_COMPARE_cmpr
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ALU_COMPARE (
dataa,
datab,
ageb,
alb)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
output ageb;
output alb;
wire sub_wire0;
wire sub_wire1;
wire ageb = sub_wire0;
wire alb = sub_wire1;
ALU_COMPARE_cmpr ALU_COMPARE_cmpr_component (
.dataa (dataa),
.datab (datab),
.ageb (sub_wire0),
.alb (sub_wire1));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AeqB NUMERIC "0"
// Retrieval info: PRIVATE: AgeB NUMERIC "1"
// Retrieval info: PRIVATE: AgtB NUMERIC "0"
// Retrieval info: PRIVATE: AleB NUMERIC "0"
// Retrieval info: PRIVATE: AltB NUMERIC "1"
// Retrieval info: PRIVATE: AneB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: PortBValue NUMERIC "0"
// Retrieval info: PRIVATE: Radix NUMERIC "10"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SignedCompare NUMERIC "1"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ALU_COMPARE.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ALU_COMPARE.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ALU_COMPARE.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ALU_COMPARE.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ALU_COMPARE_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ALU_COMPARE_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ALU_COMPARE_syn.v TRUE
// Retrieval info: LIB_FILE: lpm