Bump svd2rust v0.31.5 and svdtool v0.3.9

CHANGELOG.md

@@ -10,7 +10,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Collect ADDR\_ENDP\* registers into an array
 - Add `host_poll_interval` field to EP\_CONTROL registers
 - add EPX\_CONTROL register to USBCTRL\_DPRAM
-- Rebuild with svdtools 0.3.1
+- Rebuild with svdtools 0.3.9
+- Rebuild with svd2rust 0.31.5
+- Rebuild with form 0.11.1
+- Add `VSEL_A` field to VREG register
 
 ## [0.5.0] [Crates.io](https://crates.io/crates/rp2040-pac/0.5.0) [Github](https://github.com/rp-rs/rp2040-pac/releases/tag/v0.5.0)
 

build.rs

@@ -1,3 +1,4 @@
+#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"]
 use std::env;
 use std::fs::File;
 use std::io::Write;

src/adc.rs

@@ -1,64 +1,150 @@
 #[doc = r"Register block"]
 #[repr(C)]
 pub struct RegisterBlock {
+    cs: CS,
+    result: RESULT,
+    fcs: FCS,
+    fifo: FIFO,
+    div: DIV,
+    intr: INTR,
+    inte: INTE,
+    intf: INTF,
+    ints: INTS,
+}
+impl RegisterBlock {
     #[doc = "0x00 - ADC Control and Status"]
-    pub cs: CS,
+    #[inline(always)]
+    pub const fn cs(&self) -> &CS {
+        &self.cs
+    }
     #[doc = "0x04 - Result of most recent ADC conversion"]
-    pub result: RESULT,
+    #[inline(always)]
+    pub const fn result(&self) -> &RESULT {
+        &self.result
+    }
     #[doc = "0x08 - FIFO control and status"]
-    pub fcs: FCS,
+    #[inline(always)]
+    pub const fn fcs(&self) -> &FCS {
+        &self.fcs
+    }
     #[doc = "0x0c - Conversion result FIFO"]
-    pub fifo: FIFO,
+    #[inline(always)]
+    pub const fn fifo(&self) -> &FIFO {
+        &self.fifo
+    }
     #[doc = "0x10 - Clock divider. If non-zero, CS_START_MANY will start conversions  
  at regular intervals rather than back-to-back.  
  The divider is reset when either of these fields are written.  
  Total period is 1 + INT + FRAC / 256"]
-    pub div: DIV,
+    #[inline(always)]
+    pub const fn div(&self) -> &DIV {
+        &self.div
+    }
     #[doc = "0x14 - Raw Interrupts"]
-    pub intr: INTR,
+    #[inline(always)]
+    pub const fn intr(&self) -> &INTR {
+        &self.intr
+    }
     #[doc = "0x18 - Interrupt Enable"]
-    pub inte: INTE,
+    #[inline(always)]
+    pub const fn inte(&self) -> &INTE {
+        &self.inte
+    }
     #[doc = "0x1c - Interrupt Force"]
-    pub intf: INTF,
+    #[inline(always)]
+    pub const fn intf(&self) -> &INTF {
+        &self.intf
+    }
     #[doc = "0x20 - Interrupt status after masking & forcing"]
-    pub ints: INTS,
+    #[inline(always)]
+    pub const fn ints(&self) -> &INTS {
+        &self.ints
+    }
 }
-#[doc = "CS (rw) register accessor: an alias for `Reg<CS_SPEC>`"]
+#[doc = "CS (rw) register accessor: ADC Control and Status  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@cs`]
+module"]
 pub type CS = crate::Reg<cs::CS_SPEC>;
 #[doc = "ADC Control and Status"]
 pub mod cs;
-#[doc = "RESULT (r) register accessor: an alias for `Reg<RESULT_SPEC>`"]
+#[doc = "RESULT (r) register accessor: Result of most recent ADC conversion  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`result::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@result`]
+module"]
 pub type RESULT = crate::Reg<result::RESULT_SPEC>;
 #[doc = "Result of most recent ADC conversion"]
 pub mod result;
-#[doc = "FCS (rw) register accessor: an alias for `Reg<FCS_SPEC>`"]
+#[doc = "FCS (rw) register accessor: FIFO control and status  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`fcs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@fcs`]
+module"]
 pub type FCS = crate::Reg<fcs::FCS_SPEC>;
 #[doc = "FIFO control and status"]
 pub mod fcs;
-#[doc = "FIFO (r) register accessor: an alias for `Reg<FIFO_SPEC>`"]
+#[doc = "FIFO (r) register accessor: Conversion result FIFO  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@fifo`]
+module"]
 pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
 #[doc = "Conversion result FIFO"]
 pub mod fifo;
-#[doc = "DIV (rw) register accessor: an alias for `Reg<DIV_SPEC>`"]
+#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions  
+ at regular intervals rather than back-to-back.  
+ The divider is reset when either of these fields are written.  
+ Total period is 1 + INT + FRAC / 256  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`div::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@div`]
+module"]
 pub type DIV = crate::Reg<div::DIV_SPEC>;
 #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions  
  at regular intervals rather than back-to-back.  
  The divider is reset when either of these fields are written.  
  Total period is 1 + INT + FRAC / 256"]
 pub mod div;
-#[doc = "INTR (r) register accessor: an alias for `Reg<INTR_SPEC>`"]
+#[doc = "INTR (r) register accessor: Raw Interrupts  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@intr`]
+module"]
 pub type INTR = crate::Reg<intr::INTR_SPEC>;
 #[doc = "Raw Interrupts"]
 pub mod intr;
-#[doc = "INTE (rw) register accessor: an alias for `Reg<INTE_SPEC>`"]
+#[doc = "INTE (rw) register accessor: Interrupt Enable  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@inte`]
+module"]
 pub type INTE = crate::Reg<inte::INTE_SPEC>;
 #[doc = "Interrupt Enable"]
 pub mod inte;
-#[doc = "INTF (rw) register accessor: an alias for `Reg<INTF_SPEC>`"]
+#[doc = "INTF (rw) register accessor: Interrupt Force  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@intf`]
+module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (r) register accessor: an alias for `Reg<INTS_SPEC>`"]
+#[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing  
+
+You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
+
+For information about available fields see [`mod@ints`]
+module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
 #[doc = "Interrupt status after masking &amp; forcing"]
 pub mod ints;

src/adc/cs.rs

@@ -1,57 +1,25 @@
 #[doc = "Register `CS` reader"]
-pub struct R(crate::R<CS_SPEC>);
-impl core::ops::Deref for R {
-    type Target = crate::R<CS_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl From<crate::R<CS_SPEC>> for R {
-    #[inline(always)]
-    fn from(reader: crate::R<CS_SPEC>) -> Self {
-        R(reader)
-    }
-}
+pub type R = crate::R<CS_SPEC>;
 #[doc = "Register `CS` writer"]
-pub struct W(crate::W<CS_SPEC>);
-impl core::ops::Deref for W {
-    type Target = crate::W<CS_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl core::ops::DerefMut for W {
-    #[inline(always)]
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
-    }
-}
-impl From<crate::W<CS_SPEC>> for W {
-    #[inline(always)]
-    fn from(writer: crate::W<CS_SPEC>) -> Self {
-        W(writer)
-    }
-}
+pub type W = crate::W<CS_SPEC>;
 #[doc = "Field `EN` reader - Power on ADC and enable its clock.  
  1 - enabled. 0 - disabled."]
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - Power on ADC and enable its clock.  
  1 - enabled. 0 - disabled."]
-pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."]
 pub type TS_EN_R = crate::BitReader;
 #[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."]
-pub type TS_EN_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type TS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
 pub type START_ONCE_R = crate::BitReader;
 #[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
-pub type START_ONCE_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type START_ONCE_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
 pub type START_MANY_R = crate::BitReader;
 #[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
-pub type START_MANY_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type START_MANY_W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.  
  0 whilst conversion in progress."]
 pub type READY_R = crate::BitReader;
@@ -60,11 +28,11 @@ pub type ERR_R = crate::BitReader;
 #[doc = "Field `ERR_STICKY` reader - Some past ADC conversion encountered an error. Write 1 to clear."]
 pub type ERR_STICKY_R = crate::BitReader;
 #[doc = "Field `ERR_STICKY` writer - Some past ADC conversion encountered an error. Write 1 to clear."]
-pub type ERR_STICKY_W<'a, const O: u8> = crate::BitWriter1C<'a, CS_SPEC, O>;
+pub type ERR_STICKY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[doc = "Field `AINSEL` reader - Select analog mux input. Updated automatically in round-robin mode."]
 pub type AINSEL_R = crate::FieldReader;
 #[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode."]
-pub type AINSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CS_SPEC, 3, O>;
+pub type AINSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
 #[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
  Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
  The first channel to be sampled will be the one currently indicated by AINSEL.  
@@ -74,7 +42,7 @@ pub type RROBIN_R = crate::FieldReader;
  Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
  The first channel to be sampled will be the one currently indicated by AINSEL.  
  AINSEL will be updated after each conversion with the newly-selected channel."]
-pub type RROBIN_W<'a, const O: u8> = crate::FieldWriter<'a, CS_SPEC, 5, O>;
+pub type RROBIN_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
 impl R {
     #[doc = "Bit 0 - Power on ADC and enable its clock.  
  1 - enabled. 0 - disabled."]
@@ -132,75 +100,74 @@ impl W {
  1 - enabled. 0 - disabled."]
     #[inline(always)]
     #[must_use]
-    pub fn en(&mut self) -> EN_W<0> {
-        EN_W::new(self)
+    pub fn en(&mut self) -> EN_W<CS_SPEC> {
+        EN_W::new(self, 0)
     }
     #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."]
     #[inline(always)]
     #[must_use]
-    pub fn ts_en(&mut self) -> TS_EN_W<1> {
-        TS_EN_W::new(self)
+    pub fn ts_en(&mut self) -> TS_EN_W<CS_SPEC> {
+        TS_EN_W::new(self, 1)
     }
     #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
     #[inline(always)]
     #[must_use]
-    pub fn start_once(&mut self) -> START_ONCE_W<2> {
-        START_ONCE_W::new(self)
+    pub fn start_once(&mut self) -> START_ONCE_W<CS_SPEC> {
+        START_ONCE_W::new(self, 2)
     }
     #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
     #[inline(always)]
     #[must_use]
-    pub fn start_many(&mut self) -> START_MANY_W<3> {
-        START_MANY_W::new(self)
+    pub fn start_many(&mut self) -> START_MANY_W<CS_SPEC> {
+        START_MANY_W::new(self, 3)
     }
     #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."]
     #[inline(always)]
     #[must_use]
-    pub fn err_sticky(&mut self) -> ERR_STICKY_W<10> {
-        ERR_STICKY_W::new(self)
+    pub fn err_sticky(&mut self) -> ERR_STICKY_W<CS_SPEC> {
+        ERR_STICKY_W::new(self, 10)
     }
     #[doc = "Bits 12:14 - Select analog mux input. Updated automatically in round-robin mode."]
     #[inline(always)]
     #[must_use]
-    pub fn ainsel(&mut self) -> AINSEL_W<12> {
-        AINSEL_W::new(self)
+    pub fn ainsel(&mut self) -> AINSEL_W<CS_SPEC> {
+        AINSEL_W::new(self, 12)
     }
     #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.  
  Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.  
  The first channel to be sampled will be the one currently indicated by AINSEL.  
  AINSEL will be updated after each conversion with the newly-selected channel."]
     #[inline(always)]
     #[must_use]
-    pub fn rrobin(&mut self) -> RROBIN_W<16> {
-        RROBIN_W::new(self)
+    pub fn rrobin(&mut self) -> RROBIN_W<CS_SPEC> {
+        RROBIN_W::new(self, 16)
     }
-    #[doc = "Writes raw bits to the register."]
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
     #[inline(always)]
     pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.0.bits(bits);
+        self.bits = bits;
         self
     }
 }
 #[doc = "ADC Control and Status  
 
-This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).  
-
-For information about available fields see [cs](index.html) module"]
+You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CS_SPEC;
 impl crate::RegisterSpec for CS_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [cs::R](R) reader structure"]
-impl crate::Readable for CS_SPEC {
-    type Reader = R;
-}
-#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"]
+#[doc = "`read()` method returns [`cs::R`](R) reader structure"]
+impl crate::Readable for CS_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"]
 impl crate::Writable for CS_SPEC {
-    type Writer = W;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0400;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400;
 }
 #[doc = "`reset()` method sets CS to value 0"]
 impl crate::Resettable for CS_SPEC {
-    const RESET_VALUE: Self::Ux = 0;
+    const RESET_VALUE: u32 = 0;
 }