From 17c8a013781445b01ac10caf4567a69fa648f111 Mon Sep 17 00:00:00 2001 From: Jan Niehusmann Date: Tue, 27 Feb 2024 20:35:49 +0000 Subject: [PATCH] Update generated files --- src/adc.rs | 2 +- src/adc/cs.rs | 11 +- src/adc/div.rs | 11 +- src/adc/fcs.rs | 11 +- src/adc/inte.rs | 11 +- src/adc/intf.rs | 11 +- src/busctrl.rs | 2 +- src/busctrl/bus_priority.rs | 11 +- src/busctrl/perfctr0.rs | 11 +- src/busctrl/perfctr1.rs | 11 +- src/busctrl/perfctr2.rs | 11 +- src/busctrl/perfctr3.rs | 11 +- src/busctrl/perfsel0.rs | 15 +- src/busctrl/perfsel1.rs | 15 +- src/busctrl/perfsel2.rs | 15 +- src/busctrl/perfsel3.rs | 15 +- src/clocks.rs | 2 +- src/clocks/clk_adc_ctrl.rs | 15 +- src/clocks/clk_adc_div.rs | 11 +- src/clocks/clk_gpout0_ctrl.rs | 15 +- src/clocks/clk_gpout0_div.rs | 11 +- src/clocks/clk_gpout1_ctrl.rs | 15 +- src/clocks/clk_gpout1_div.rs | 11 +- src/clocks/clk_gpout2_ctrl.rs | 15 +- src/clocks/clk_gpout2_div.rs | 11 +- src/clocks/clk_gpout3_ctrl.rs | 15 +- src/clocks/clk_gpout3_div.rs | 11 +- src/clocks/clk_peri_ctrl.rs | 15 +- src/clocks/clk_ref_ctrl.rs | 19 +- src/clocks/clk_ref_div.rs | 11 +- src/clocks/clk_rtc_ctrl.rs | 15 +- src/clocks/clk_rtc_div.rs | 11 +- src/clocks/clk_sys_ctrl.rs | 19 +- src/clocks/clk_sys_div.rs | 11 +- src/clocks/clk_sys_resus_ctrl.rs | 11 +- src/clocks/clk_usb_ctrl.rs | 15 +- src/clocks/clk_usb_div.rs | 11 +- src/clocks/fc0_delay.rs | 11 +- src/clocks/fc0_interval.rs | 11 +- src/clocks/fc0_max_khz.rs | 11 +- src/clocks/fc0_min_khz.rs | 11 +- src/clocks/fc0_ref_khz.rs | 11 +- src/clocks/fc0_src.rs | 15 +- src/clocks/inte.rs | 11 +- src/clocks/intf.rs | 11 +- src/clocks/sleep_en0.rs | 11 +- src/clocks/sleep_en1.rs | 11 +- src/clocks/wake_en0.rs | 11 +- src/clocks/wake_en1.rs | 11 +- src/dma.rs | 2 +- src/dma/ch.rs | 2 +- src/dma/ch/ch_al1_ctrl.rs | 31 ++- src/dma/ch/ch_al1_read_addr.rs | 14 +- src/dma/ch/ch_al1_trans_count_trig.rs | 14 +- src/dma/ch/ch_al1_write_addr.rs | 14 +- src/dma/ch/ch_al2_ctrl.rs | 31 ++- src/dma/ch/ch_al2_read_addr.rs | 14 +- src/dma/ch/ch_al2_trans_count.rs | 14 +- src/dma/ch/ch_al2_write_addr_trig.rs | 14 +- src/dma/ch/ch_al3_ctrl.rs | 31 ++- src/dma/ch/ch_al3_read_addr_trig.rs | 14 +- src/dma/ch/ch_al3_trans_count.rs | 14 +- src/dma/ch/ch_al3_write_addr.rs | 14 +- src/dma/ch/ch_ctrl_trig.rs | 31 ++- src/dma/ch/ch_read_addr.rs | 14 +- src/dma/ch/ch_trans_count.rs | 14 +- src/dma/ch/ch_write_addr.rs | 14 +- src/dma/ch0_dbg_ctdreq.rs | 11 +- src/dma/ch10_dbg_ctdreq.rs | 11 +- src/dma/ch11_dbg_ctdreq.rs | 11 +- src/dma/ch1_dbg_ctdreq.rs | 11 +- src/dma/ch2_dbg_ctdreq.rs | 11 +- src/dma/ch3_dbg_ctdreq.rs | 11 +- src/dma/ch4_dbg_ctdreq.rs | 11 +- src/dma/ch5_dbg_ctdreq.rs | 11 +- src/dma/ch6_dbg_ctdreq.rs | 11 +- src/dma/ch7_dbg_ctdreq.rs | 11 +- src/dma/ch8_dbg_ctdreq.rs | 11 +- src/dma/ch9_dbg_ctdreq.rs | 11 +- src/dma/chan_abort.rs | 11 +- src/dma/inte0.rs | 11 +- src/dma/inte1.rs | 11 +- src/dma/intf0.rs | 11 +- src/dma/intf1.rs | 11 +- src/dma/intr.rs | 11 +- src/dma/ints0.rs | 11 +- src/dma/ints1.rs | 11 +- src/dma/multi_chan_trigger.rs | 11 +- src/dma/sniff_ctrl.rs | 15 +- src/dma/sniff_data.rs | 14 +- src/dma/timer0.rs | 11 +- src/dma/timer1.rs | 11 +- src/dma/timer2.rs | 11 +- src/dma/timer3.rs | 11 +- src/generic.rs | 29 ++- src/i2c0.rs | 2 +- src/i2c0/ic_ack_general_call.rs | 15 +- src/i2c0/ic_con.rs | 95 +++++----- src/i2c0/ic_data_cmd.rs | 81 ++++---- src/i2c0/ic_dma_cr.rs | 19 +- src/i2c0/ic_dma_rdlr.rs | 11 +- src/i2c0/ic_dma_tdlr.rs | 11 +- src/i2c0/ic_enable.rs | 45 ++--- src/i2c0/ic_enable_status.rs | 68 +++---- src/i2c0/ic_fs_scl_hcnt.rs | 11 +- src/i2c0/ic_fs_scl_lcnt.rs | 11 +- src/i2c0/ic_fs_spklen.rs | 11 +- src/i2c0/ic_intr_mask.rs | 115 ++++++----- src/i2c0/ic_intr_stat.rs | 104 +++++----- src/i2c0/ic_raw_intr_stat.rs | 118 ++++++------ src/i2c0/ic_rx_tl.rs | 11 +- src/i2c0/ic_sar.rs | 11 +- src/i2c0/ic_sda_hold.rs | 11 +- src/i2c0/ic_sda_setup.rs | 11 +- src/i2c0/ic_slv_data_nack_only.rs | 19 +- src/i2c0/ic_ss_scl_hcnt.rs | 11 +- src/i2c0/ic_ss_scl_lcnt.rs | 11 +- src/i2c0/ic_status.rs | 32 ++-- src/i2c0/ic_tar.rs | 19 +- src/i2c0/ic_tx_abrt_source.rs | 210 ++++++++++----------- src/i2c0/ic_tx_tl.rs | 11 +- src/io_bank0.rs | 2 +- src/io_bank0/dormant_wake_inte.rs | 11 +- src/io_bank0/dormant_wake_intf.rs | 11 +- src/io_bank0/gpio.rs | 2 +- src/io_bank0/gpio/gpio_ctrl.rs | 31 ++- src/io_bank0/intr.rs | 11 +- src/io_bank0/proc0_inte.rs | 11 +- src/io_bank0/proc0_intf.rs | 11 +- src/io_bank0/proc1_inte.rs | 11 +- src/io_bank0/proc1_intf.rs | 11 +- src/io_qspi.rs | 2 +- src/io_qspi/dormant_wake_inte.rs | 11 +- src/io_qspi/dormant_wake_intf.rs | 11 +- src/io_qspi/gpio_qspi.rs | 2 +- src/io_qspi/gpio_qspi/gpio_ctrl.rs | 33 ++-- src/io_qspi/intr.rs | 11 +- src/io_qspi/proc0_inte.rs | 11 +- src/io_qspi/proc0_intf.rs | 11 +- src/io_qspi/proc1_inte.rs | 11 +- src/io_qspi/proc1_intf.rs | 11 +- src/lib.rs | 4 +- src/pads_bank0.rs | 2 +- src/pads_bank0/gpio.rs | 15 +- src/pads_bank0/swclk.rs | 15 +- src/pads_bank0/swd.rs | 15 +- src/pads_bank0/voltage_select.rs | 15 +- src/pads_qspi.rs | 2 +- src/pads_qspi/gpio_qspi_sclk.rs | 15 +- src/pads_qspi/gpio_qspi_sd0.rs | 15 +- src/pads_qspi/gpio_qspi_sd1.rs | 15 +- src/pads_qspi/gpio_qspi_sd2.rs | 15 +- src/pads_qspi/gpio_qspi_sd3.rs | 15 +- src/pads_qspi/gpio_qspi_ss.rs | 15 +- src/pads_qspi/voltage_select.rs | 15 +- src/pio0.rs | 2 +- src/pio0/ctrl.rs | 11 +- src/pio0/fdebug.rs | 11 +- src/pio0/input_sync_bypass.rs | 14 +- src/pio0/instr_mem.rs | 11 +- src/pio0/irq.rs | 11 +- src/pio0/irq_force.rs | 11 +- src/pio0/sm.rs | 2 +- src/pio0/sm/sm_clkdiv.rs | 11 +- src/pio0/sm/sm_execctrl.rs | 15 +- src/pio0/sm/sm_instr.rs | 11 +- src/pio0/sm/sm_pinctrl.rs | 11 +- src/pio0/sm/sm_shiftctrl.rs | 11 +- src/pio0/sm_irq.rs | 2 +- src/pio0/sm_irq/irq_inte.rs | 11 +- src/pio0/sm_irq/irq_intf.rs | 11 +- src/pio0/txf.rs | 14 +- src/pll_sys.rs | 2 +- src/pll_sys/cs.rs | 11 +- src/pll_sys/fbdiv_int.rs | 11 +- src/pll_sys/prim.rs | 11 +- src/pll_sys/pwr.rs | 11 +- src/ppb.rs | 2 +- src/ppb/aircr.rs | 11 +- src/ppb/icsr.rs | 11 +- src/ppb/mpu_ctrl.rs | 11 +- src/ppb/mpu_rasr.rs | 11 +- src/ppb/mpu_rbar.rs | 11 +- src/ppb/mpu_rnr.rs | 11 +- src/ppb/nvic_icer.rs | 11 +- src/ppb/nvic_icpr.rs | 11 +- src/ppb/nvic_ipr0.rs | 11 +- src/ppb/nvic_ipr1.rs | 11 +- src/ppb/nvic_ipr2.rs | 11 +- src/ppb/nvic_ipr3.rs | 11 +- src/ppb/nvic_ipr4.rs | 11 +- src/ppb/nvic_ipr5.rs | 11 +- src/ppb/nvic_ipr6.rs | 11 +- src/ppb/nvic_ipr7.rs | 11 +- src/ppb/nvic_iser.rs | 11 +- src/ppb/nvic_ispr.rs | 11 +- src/ppb/scr.rs | 11 +- src/ppb/shcsr.rs | 11 +- src/ppb/shpr2.rs | 11 +- src/ppb/shpr3.rs | 11 +- src/ppb/syst_csr.rs | 11 +- src/ppb/syst_cvr.rs | 11 +- src/ppb/syst_rvr.rs | 11 +- src/ppb/vtor.rs | 11 +- src/psm.rs | 2 +- src/psm/frce_off.rs | 11 +- src/psm/frce_on.rs | 11 +- src/psm/wdsel.rs | 11 +- src/pwm.rs | 2 +- src/pwm/ch.rs | 2 +- src/pwm/ch/cc.rs | 11 +- src/pwm/ch/csr.rs | 15 +- src/pwm/ch/ctr.rs | 11 +- src/pwm/ch/div.rs | 11 +- src/pwm/ch/top.rs | 11 +- src/pwm/en.rs | 11 +- src/pwm/inte.rs | 11 +- src/pwm/intf.rs | 11 +- src/pwm/intr.rs | 11 +- src/resets.rs | 2 +- src/resets/reset.rs | 11 +- src/resets/wdsel.rs | 11 +- src/rosc.rs | 2 +- src/rosc/ctrl.rs | 37 ++-- src/rosc/div.rs | 23 +-- src/rosc/dormant.rs | 14 +- src/rosc/freqa.rs | 17 +- src/rosc/freqb.rs | 17 +- src/rosc/phase.rs | 11 +- src/rtc.rs | 2 +- src/rtc/clkdiv_m1.rs | 11 +- src/rtc/ctrl.rs | 11 +- src/rtc/inte.rs | 11 +- src/rtc/intf.rs | 11 +- src/rtc/irq_setup_0.rs | 11 +- src/rtc/irq_setup_1.rs | 11 +- src/rtc/setup_0.rs | 11 +- src/rtc/setup_1.rs | 11 +- src/sio.rs | 2 +- src/sio/div_quotient.rs | 14 +- src/sio/div_remainder.rs | 14 +- src/sio/div_sdividend.rs | 14 +- src/sio/div_sdivisor.rs | 14 +- src/sio/div_udividend.rs | 14 +- src/sio/div_udivisor.rs | 14 +- src/sio/fifo_st.rs | 11 +- src/sio/fifo_wr.rs | 14 +- src/sio/gpio_hi_oe.rs | 11 +- src/sio/gpio_hi_oe_clr.rs | 11 +- src/sio/gpio_hi_oe_set.rs | 11 +- src/sio/gpio_hi_oe_xor.rs | 11 +- src/sio/gpio_hi_out.rs | 11 +- src/sio/gpio_hi_out_clr.rs | 11 +- src/sio/gpio_hi_out_set.rs | 11 +- src/sio/gpio_hi_out_xor.rs | 11 +- src/sio/gpio_oe.rs | 11 +- src/sio/gpio_oe_clr.rs | 11 +- src/sio/gpio_oe_set.rs | 11 +- src/sio/gpio_oe_xor.rs | 11 +- src/sio/gpio_out.rs | 11 +- src/sio/gpio_out_clr.rs | 11 +- src/sio/gpio_out_set.rs | 11 +- src/sio/gpio_out_xor.rs | 11 +- src/sio/interp0_accum0.rs | 14 +- src/sio/interp0_accum0_add.rs | 11 +- src/sio/interp0_accum1.rs | 14 +- src/sio/interp0_accum1_add.rs | 11 +- src/sio/interp0_base0.rs | 14 +- src/sio/interp0_base1.rs | 14 +- src/sio/interp0_base2.rs | 14 +- src/sio/interp0_base_1and0.rs | 14 +- src/sio/interp0_ctrl_lane0.rs | 11 +- src/sio/interp0_ctrl_lane1.rs | 11 +- src/sio/interp1_accum0.rs | 14 +- src/sio/interp1_accum0_add.rs | 11 +- src/sio/interp1_accum1.rs | 14 +- src/sio/interp1_accum1_add.rs | 11 +- src/sio/interp1_base0.rs | 14 +- src/sio/interp1_base1.rs | 14 +- src/sio/interp1_base2.rs | 14 +- src/sio/interp1_base_1and0.rs | 14 +- src/sio/interp1_ctrl_lane0.rs | 11 +- src/sio/interp1_ctrl_lane1.rs | 11 +- src/sio/spinlock.rs | 14 +- src/spi0.rs | 2 +- src/spi0/sspcpsr.rs | 11 +- src/spi0/sspcr0.rs | 15 +- src/spi0/sspcr1.rs | 11 +- src/spi0/sspdmacr.rs | 11 +- src/spi0/sspdr.rs | 11 +- src/spi0/sspicr.rs | 11 +- src/spi0/sspimsc.rs | 11 +- src/syscfg.rs | 2 +- src/syscfg/dbgforce.rs | 11 +- src/syscfg/mempowerdown.rs | 11 +- src/syscfg/proc0_nmi_mask.rs | 14 +- src/syscfg/proc1_nmi_mask.rs | 14 +- src/syscfg/proc_config.rs | 11 +- src/syscfg/proc_in_sync_bypass.rs | 11 +- src/syscfg/proc_in_sync_bypass_hi.rs | 11 +- src/sysinfo.rs | 2 +- src/tbman.rs | 2 +- src/timer.rs | 2 +- src/timer/alarm0.rs | 14 +- src/timer/alarm1.rs | 14 +- src/timer/alarm2.rs | 14 +- src/timer/alarm3.rs | 14 +- src/timer/armed.rs | 11 +- src/timer/dbgpause.rs | 11 +- src/timer/inte.rs | 11 +- src/timer/intf.rs | 11 +- src/timer/intr.rs | 11 +- src/timer/pause.rs | 11 +- src/timer/timehw.rs | 14 +- src/timer/timelw.rs | 14 +- src/uart0.rs | 2 +- src/uart0/uartcr.rs | 11 +- src/uart0/uartdmacr.rs | 11 +- src/uart0/uartdr.rs | 11 +- src/uart0/uartfbrd.rs | 11 +- src/uart0/uartibrd.rs | 11 +- src/uart0/uarticr.rs | 11 +- src/uart0/uartifls.rs | 11 +- src/uart0/uartilpr.rs | 11 +- src/uart0/uartimsc.rs | 11 +- src/uart0/uartlcr_h.rs | 11 +- src/uart0/uartrsr.rs | 11 +- src/usbctrl_dpram.rs | 2 +- src/usbctrl_dpram/ep_buffer_control.rs | 17 +- src/usbctrl_dpram/ep_control.rs | 15 +- src/usbctrl_dpram/epx_control.rs | 15 +- src/usbctrl_dpram/setup_packet_high.rs | 11 +- src/usbctrl_dpram/setup_packet_low.rs | 11 +- src/usbctrl_regs.rs | 2 +- src/usbctrl_regs/addr_endp.rs | 11 +- src/usbctrl_regs/buff_status.rs | 11 +- src/usbctrl_regs/ep_abort.rs | 11 +- src/usbctrl_regs/ep_abort_done.rs | 11 +- src/usbctrl_regs/ep_stall_arm.rs | 11 +- src/usbctrl_regs/ep_status_stall_nak.rs | 11 +- src/usbctrl_regs/host_addr_endp.rs | 11 +- src/usbctrl_regs/int_ep_ctrl.rs | 11 +- src/usbctrl_regs/inte.rs | 11 +- src/usbctrl_regs/intf.rs | 11 +- src/usbctrl_regs/main_ctrl.rs | 11 +- src/usbctrl_regs/nak_poll.rs | 11 +- src/usbctrl_regs/sie_ctrl.rs | 11 +- src/usbctrl_regs/sie_status.rs | 15 +- src/usbctrl_regs/sof_wr.rs | 11 +- src/usbctrl_regs/usb_muxing.rs | 11 +- src/usbctrl_regs/usb_pwr.rs | 11 +- src/usbctrl_regs/usbphy_direct.rs | 11 +- src/usbctrl_regs/usbphy_direct_override.rs | 11 +- src/usbctrl_regs/usbphy_trim.rs | 11 +- src/vreg_and_chip_reset.rs | 2 +- src/vreg_and_chip_reset/bod.rs | 11 +- src/vreg_and_chip_reset/chip_reset.rs | 11 +- src/vreg_and_chip_reset/vreg.rs | 15 +- src/watchdog.rs | 2 +- src/watchdog/ctrl.rs | 11 +- src/watchdog/load.rs | 11 +- src/watchdog/scratch0.rs | 14 +- src/watchdog/scratch1.rs | 14 +- src/watchdog/scratch2.rs | 14 +- src/watchdog/scratch3.rs | 14 +- src/watchdog/scratch4.rs | 14 +- src/watchdog/scratch5.rs | 14 +- src/watchdog/scratch6.rs | 14 +- src/watchdog/scratch7.rs | 14 +- src/watchdog/tick.rs | 11 +- src/xip_ctrl.rs | 2 +- src/xip_ctrl/ctr_acc.rs | 14 +- src/xip_ctrl/ctr_hit.rs | 14 +- src/xip_ctrl/ctrl.rs | 11 +- src/xip_ctrl/flush.rs | 11 +- src/xip_ctrl/stream_addr.rs | 11 +- src/xip_ctrl/stream_ctr.rs | 11 +- src/xip_ssi.rs | 2 +- src/xip_ssi/baudr.rs | 11 +- src/xip_ssi/ctrlr0.rs | 19 +- src/xip_ssi/ctrlr1.rs | 11 +- src/xip_ssi/dmacr.rs | 11 +- src/xip_ssi/dmardlr.rs | 11 +- src/xip_ssi/dmatdlr.rs | 11 +- src/xip_ssi/dr0.rs | 11 +- src/xip_ssi/imr.rs | 11 +- src/xip_ssi/mwcr.rs | 11 +- src/xip_ssi/rx_sample_dly.rs | 11 +- src/xip_ssi/rxftlr.rs | 11 +- src/xip_ssi/ser.rs | 11 +- src/xip_ssi/spi_ctrlr0.rs | 19 +- src/xip_ssi/ssienr.rs | 11 +- src/xip_ssi/txd_drive_edge.rs | 11 +- src/xip_ssi/txftlr.rs | 11 +- src/xosc.rs | 2 +- src/xosc/ctrl.rs | 23 +-- src/xosc/dormant.rs | 14 +- src/xosc/startup.rs | 11 +- src/xosc/status.rs | 15 +- 399 files changed, 1079 insertions(+), 4304 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index a39136e6c..ba68c8111 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { cs: CS, result: RESULT, diff --git a/src/adc/cs.rs b/src/adc/cs.rs index d7efee089..4f22e80f2 100644 --- a/src/adc/cs.rs +++ b/src/adc/cs.rs @@ -142,16 +142,6 @@ impl W { pub fn rrobin(&mut self) -> RROBIN_W { RROBIN_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "ADC Control and Status @@ -164,6 +154,7 @@ impl crate::RegisterSpec for CS_SPEC { impl crate::Readable for CS_SPEC {} #[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400; } diff --git a/src/adc/div.rs b/src/adc/div.rs index 5045174fa..4bd141132 100644 --- a/src/adc/div.rs +++ b/src/adc/div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. @@ -60,6 +50,7 @@ impl crate::RegisterSpec for DIV_SPEC { impl crate::Readable for DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/adc/fcs.rs b/src/adc/fcs.rs index fccfeb96d..6889daa89 100644 --- a/src/adc/fcs.rs +++ b/src/adc/fcs.rs @@ -131,16 +131,6 @@ impl W { pub fn thresh(&mut self) -> THRESH_W { THRESH_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "FIFO control and status @@ -153,6 +143,7 @@ impl crate::RegisterSpec for FCS_SPEC { impl crate::Readable for FCS_SPEC {} #[doc = "`write(|w| ..)` method takes [`fcs::W`](W) writer structure"] impl crate::Writable for FCS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c00; } diff --git a/src/adc/inte.rs b/src/adc/inte.rs index 050efa964..48ddb4a7f 100644 --- a/src/adc/inte.rs +++ b/src/adc/inte.rs @@ -24,16 +24,6 @@ impl W { pub fn fifo(&mut self) -> FIFO_W { FIFO_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable @@ -46,6 +36,7 @@ impl crate::RegisterSpec for INTE_SPEC { impl crate::Readable for INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/adc/intf.rs b/src/adc/intf.rs index 41bc4c391..aec4073f3 100644 --- a/src/adc/intf.rs +++ b/src/adc/intf.rs @@ -24,16 +24,6 @@ impl W { pub fn fifo(&mut self) -> FIFO_W { FIFO_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force @@ -46,6 +36,7 @@ impl crate::RegisterSpec for INTF_SPEC { impl crate::Readable for INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/busctrl.rs b/src/busctrl.rs index 9c78f0df9..308d0eda9 100644 --- a/src/busctrl.rs +++ b/src/busctrl.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { bus_priority: BUS_PRIORITY, bus_priority_ack: BUS_PRIORITY_ACK, diff --git a/src/busctrl/bus_priority.rs b/src/busctrl/bus_priority.rs index f657b2f59..c338724e1 100644 --- a/src/busctrl/bus_priority.rs +++ b/src/busctrl/bus_priority.rs @@ -65,16 +65,6 @@ impl W { pub fn dma_w(&mut self) -> DMA_W_W { DMA_W_W::new(self, 12) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Set the priority of each master for bus arbitration. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for BUS_PRIORITY_SPEC { impl crate::Readable for BUS_PRIORITY_SPEC {} #[doc = "`write(|w| ..)` method takes [`bus_priority::W`](W) writer structure"] impl crate::Writable for BUS_PRIORITY_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/busctrl/perfctr0.rs b/src/busctrl/perfctr0.rs index e5147e96a..24c7eef13 100644 --- a/src/busctrl/perfctr0.rs +++ b/src/busctrl/perfctr0.rs @@ -28,16 +28,6 @@ impl W { pub fn perfctr0(&mut self) -> PERFCTR0_W { PERFCTR0_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance counter 0 @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR0_SPEC { impl crate::Readable for PERFCTR0_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfctr0::W`](W) writer structure"] impl crate::Writable for PERFCTR0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; } diff --git a/src/busctrl/perfctr1.rs b/src/busctrl/perfctr1.rs index 213c54dbd..5d755ae07 100644 --- a/src/busctrl/perfctr1.rs +++ b/src/busctrl/perfctr1.rs @@ -28,16 +28,6 @@ impl W { pub fn perfctr1(&mut self) -> PERFCTR1_W { PERFCTR1_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance counter 1 @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR1_SPEC { impl crate::Readable for PERFCTR1_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfctr1::W`](W) writer structure"] impl crate::Writable for PERFCTR1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; } diff --git a/src/busctrl/perfctr2.rs b/src/busctrl/perfctr2.rs index 295109562..d93cd401b 100644 --- a/src/busctrl/perfctr2.rs +++ b/src/busctrl/perfctr2.rs @@ -28,16 +28,6 @@ impl W { pub fn perfctr2(&mut self) -> PERFCTR2_W { PERFCTR2_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance counter 2 @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR2_SPEC { impl crate::Readable for PERFCTR2_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfctr2::W`](W) writer structure"] impl crate::Writable for PERFCTR2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; } diff --git a/src/busctrl/perfctr3.rs b/src/busctrl/perfctr3.rs index 99758ce3f..6946cf253 100644 --- a/src/busctrl/perfctr3.rs +++ b/src/busctrl/perfctr3.rs @@ -28,16 +28,6 @@ impl W { pub fn perfctr3(&mut self) -> PERFCTR3_W { PERFCTR3_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance counter 3 @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR3_SPEC { impl crate::Readable for PERFCTR3_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfctr3::W`](W) writer structure"] impl crate::Writable for PERFCTR3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff; } diff --git a/src/busctrl/perfsel0.rs b/src/busctrl/perfsel0.rs index 494ab0c40..ce44b8c5b 100644 --- a/src/busctrl/perfsel0.rs +++ b/src/busctrl/perfsel0.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `PERFSEL0` writer"] pub type W = crate::W; -#[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL0_R = crate::FieldReader; #[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. Value on reset: 31"] @@ -60,6 +58,8 @@ impl From for u8 { impl crate::FieldSpec for PERFSEL0_A { type Ux = u8; } +#[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] +pub type PERFSEL0_R = crate::FieldReader; impl PERFSEL0_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -311,16 +311,6 @@ impl W { pub fn perfsel0(&mut self) -> PERFSEL0_W { PERFSEL0_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance event select for PERFCTR0 @@ -333,6 +323,7 @@ impl crate::RegisterSpec for PERFSEL0_SPEC { impl crate::Readable for PERFSEL0_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfsel0::W`](W) writer structure"] impl crate::Writable for PERFSEL0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/busctrl/perfsel1.rs b/src/busctrl/perfsel1.rs index a7c78cb17..01daabc0f 100644 --- a/src/busctrl/perfsel1.rs +++ b/src/busctrl/perfsel1.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `PERFSEL1` writer"] pub type W = crate::W; -#[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL1_R = crate::FieldReader; #[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. Value on reset: 31"] @@ -60,6 +58,8 @@ impl From for u8 { impl crate::FieldSpec for PERFSEL1_A { type Ux = u8; } +#[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] +pub type PERFSEL1_R = crate::FieldReader; impl PERFSEL1_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -311,16 +311,6 @@ impl W { pub fn perfsel1(&mut self) -> PERFSEL1_W { PERFSEL1_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance event select for PERFCTR1 @@ -333,6 +323,7 @@ impl crate::RegisterSpec for PERFSEL1_SPEC { impl crate::Readable for PERFSEL1_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfsel1::W`](W) writer structure"] impl crate::Writable for PERFSEL1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/busctrl/perfsel2.rs b/src/busctrl/perfsel2.rs index 907e362de..1a39e60f0 100644 --- a/src/busctrl/perfsel2.rs +++ b/src/busctrl/perfsel2.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `PERFSEL2` writer"] pub type W = crate::W; -#[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL2_R = crate::FieldReader; #[doc = "Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. Value on reset: 31"] @@ -60,6 +58,8 @@ impl From for u8 { impl crate::FieldSpec for PERFSEL2_A { type Ux = u8; } +#[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] +pub type PERFSEL2_R = crate::FieldReader; impl PERFSEL2_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -311,16 +311,6 @@ impl W { pub fn perfsel2(&mut self) -> PERFSEL2_W { PERFSEL2_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance event select for PERFCTR2 @@ -333,6 +323,7 @@ impl crate::RegisterSpec for PERFSEL2_SPEC { impl crate::Readable for PERFSEL2_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfsel2::W`](W) writer structure"] impl crate::Writable for PERFSEL2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/busctrl/perfsel3.rs b/src/busctrl/perfsel3.rs index cf999aade..2f34e1e83 100644 --- a/src/busctrl/perfsel3.rs +++ b/src/busctrl/perfsel3.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `PERFSEL3` writer"] pub type W = crate::W; -#[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] -pub type PERFSEL3_R = crate::FieldReader; #[doc = "Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. Value on reset: 31"] @@ -60,6 +58,8 @@ impl From for u8 { impl crate::FieldSpec for PERFSEL3_A { type Ux = u8; } +#[doc = "Field `PERFSEL3` reader - Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."] +pub type PERFSEL3_R = crate::FieldReader; impl PERFSEL3_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -311,16 +311,6 @@ impl W { pub fn perfsel3(&mut self) -> PERFSEL3_W { PERFSEL3_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bus fabric performance event select for PERFCTR3 @@ -333,6 +323,7 @@ impl crate::RegisterSpec for PERFSEL3_SPEC { impl crate::Readable for PERFSEL3_SPEC {} #[doc = "`write(|w| ..)` method takes [`perfsel3::W`](W) writer structure"] impl crate::Writable for PERFSEL3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks.rs b/src/clocks.rs index 34290d863..92a0dda46 100644 --- a/src/clocks.rs +++ b/src/clocks.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { clk_gpout0_ctrl: CLK_GPOUT0_CTRL, clk_gpout0_div: CLK_GPOUT0_DIV, diff --git a/src/clocks/clk_adc_ctrl.rs b/src/clocks/clk_adc_ctrl.rs index 8f01d709c..b22f652f0 100644 --- a/src/clocks/clk_adc_ctrl.rs +++ b/src/clocks/clk_adc_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_ADC_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -32,6 +30,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -197,16 +197,6 @@ impl W { pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -219,6 +209,7 @@ impl crate::RegisterSpec for CLK_ADC_CTRL_SPEC { impl crate::Readable for CLK_ADC_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_adc_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_ADC_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_adc_div.rs b/src/clocks/clk_adc_div.rs index c5a1fec3e..3d257c5db 100644 --- a/src/clocks/clk_adc_div.rs +++ b/src/clocks/clk_adc_div.rs @@ -20,16 +20,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CLK_ADC_DIV_SPEC { impl crate::Readable for CLK_ADC_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_adc_div::W`](W) writer structure"] impl crate::Writable for CLK_ADC_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout0_ctrl.rs b/src/clocks/clk_gpout0_ctrl.rs index 917d4078a..4edce962e 100644 --- a/src/clocks/clk_gpout0_ctrl.rs +++ b/src/clocks/clk_gpout0_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_GPOUT0_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -42,6 +40,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -277,16 +277,6 @@ impl W { pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -299,6 +289,7 @@ impl crate::RegisterSpec for CLK_GPOUT0_CTRL_SPEC { impl crate::Readable for CLK_GPOUT0_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout0_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT0_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout0_div.rs b/src/clocks/clk_gpout0_div.rs index 913d4ca8b..f96a67f2b 100644 --- a/src/clocks/clk_gpout0_div.rs +++ b/src/clocks/clk_gpout0_div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -57,6 +47,7 @@ impl crate::RegisterSpec for CLK_GPOUT0_DIV_SPEC { impl crate::Readable for CLK_GPOUT0_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout0_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT0_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout1_ctrl.rs b/src/clocks/clk_gpout1_ctrl.rs index e3a992112..eab13e0a1 100644 --- a/src/clocks/clk_gpout1_ctrl.rs +++ b/src/clocks/clk_gpout1_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_GPOUT1_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -42,6 +40,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -277,16 +277,6 @@ impl W { pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -299,6 +289,7 @@ impl crate::RegisterSpec for CLK_GPOUT1_CTRL_SPEC { impl crate::Readable for CLK_GPOUT1_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout1_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT1_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout1_div.rs b/src/clocks/clk_gpout1_div.rs index 23af8a3d6..3280a631c 100644 --- a/src/clocks/clk_gpout1_div.rs +++ b/src/clocks/clk_gpout1_div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -57,6 +47,7 @@ impl crate::RegisterSpec for CLK_GPOUT1_DIV_SPEC { impl crate::Readable for CLK_GPOUT1_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout1_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT1_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout2_ctrl.rs b/src/clocks/clk_gpout2_ctrl.rs index 58082e2d2..25badf597 100644 --- a/src/clocks/clk_gpout2_ctrl.rs +++ b/src/clocks/clk_gpout2_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_GPOUT2_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -42,6 +40,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -277,16 +277,6 @@ impl W { pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -299,6 +289,7 @@ impl crate::RegisterSpec for CLK_GPOUT2_CTRL_SPEC { impl crate::Readable for CLK_GPOUT2_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout2_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT2_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout2_div.rs b/src/clocks/clk_gpout2_div.rs index 5cad64b5d..653b2e7fb 100644 --- a/src/clocks/clk_gpout2_div.rs +++ b/src/clocks/clk_gpout2_div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -57,6 +47,7 @@ impl crate::RegisterSpec for CLK_GPOUT2_DIV_SPEC { impl crate::Readable for CLK_GPOUT2_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout2_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT2_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout3_ctrl.rs b/src/clocks/clk_gpout3_ctrl.rs index 135df8f8d..b5b5ed98d 100644 --- a/src/clocks/clk_gpout3_ctrl.rs +++ b/src/clocks/clk_gpout3_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_GPOUT3_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -42,6 +40,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -277,16 +277,6 @@ impl W { pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -299,6 +289,7 @@ impl crate::RegisterSpec for CLK_GPOUT3_CTRL_SPEC { impl crate::Readable for CLK_GPOUT3_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout3_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT3_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_gpout3_div.rs b/src/clocks/clk_gpout3_div.rs index d73adfded..282846899 100644 --- a/src/clocks/clk_gpout3_div.rs +++ b/src/clocks/clk_gpout3_div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -57,6 +47,7 @@ impl crate::RegisterSpec for CLK_GPOUT3_DIV_SPEC { impl crate::Readable for CLK_GPOUT3_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_gpout3_div::W`](W) writer structure"] impl crate::Writable for CLK_GPOUT3_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_peri_ctrl.rs b/src/clocks/clk_peri_ctrl.rs index 84677531a..3e2ef59ee 100644 --- a/src/clocks/clk_peri_ctrl.rs +++ b/src/clocks/clk_peri_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_PERI_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -34,6 +32,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -172,16 +172,6 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 11) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -194,6 +184,7 @@ impl crate::RegisterSpec for CLK_PERI_CTRL_SPEC { impl crate::Readable for CLK_PERI_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_peri_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_PERI_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_ref_ctrl.rs b/src/clocks/clk_ref_ctrl.rs index 6cb416fab..a81dc5705 100644 --- a/src/clocks/clk_ref_ctrl.rs +++ b/src/clocks/clk_ref_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_REF_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] -pub type SRC_R = crate::FieldReader; #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly Value on reset: 0"] @@ -26,6 +24,8 @@ impl From for u8 { impl crate::FieldSpec for SRC_A { type Ux = u8; } +#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] +pub type SRC_R = crate::FieldReader; impl SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -76,8 +76,6 @@ where self.variant(SRC_A::XOSC_CLKSRC) } } -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -100,6 +98,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -175,16 +175,6 @@ impl W { pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self, 5) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -197,6 +187,7 @@ impl crate::RegisterSpec for CLK_REF_CTRL_SPEC { impl crate::Readable for CLK_REF_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_ref_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_REF_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_ref_div.rs b/src/clocks/clk_ref_div.rs index 77ac5a45c..2cd4bbe79 100644 --- a/src/clocks/clk_ref_div.rs +++ b/src/clocks/clk_ref_div.rs @@ -20,16 +20,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CLK_REF_DIV_SPEC { impl crate::Readable for CLK_REF_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_ref_div::W`](W) writer structure"] impl crate::Writable for CLK_REF_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_rtc_ctrl.rs b/src/clocks/clk_rtc_ctrl.rs index 4d1c12d5a..6adf1f9a7 100644 --- a/src/clocks/clk_rtc_ctrl.rs +++ b/src/clocks/clk_rtc_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_RTC_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -32,6 +30,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -197,16 +197,6 @@ impl W { pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -219,6 +209,7 @@ impl crate::RegisterSpec for CLK_RTC_CTRL_SPEC { impl crate::Readable for CLK_RTC_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_rtc_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_RTC_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_rtc_div.rs b/src/clocks/clk_rtc_div.rs index f8bce1a4f..e79f911f5 100644 --- a/src/clocks/clk_rtc_div.rs +++ b/src/clocks/clk_rtc_div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -57,6 +47,7 @@ impl crate::RegisterSpec for CLK_RTC_DIV_SPEC { impl crate::Readable for CLK_RTC_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_rtc_div::W`](W) writer structure"] impl crate::Writable for CLK_RTC_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_sys_ctrl.rs b/src/clocks/clk_sys_ctrl.rs index a6b8724d7..2a489cfbc 100644 --- a/src/clocks/clk_sys_ctrl.rs +++ b/src/clocks/clk_sys_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_SYS_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] -pub type SRC_R = crate::BitReader; #[doc = "Selects the clock source glitchlessly, can be changed on-the-fly Value on reset: 0"] @@ -20,6 +18,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `SRC` reader - Selects the clock source glitchlessly, can be changed on-the-fly"] +pub type SRC_R = crate::BitReader; impl SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -57,8 +57,6 @@ where self.variant(SRC_A::CLKSRC_CLK_SYS_AUX) } } -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -87,6 +85,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -195,16 +195,6 @@ impl W { pub fn auxsrc(&mut self) -> AUXSRC_W { AUXSRC_W::new(self, 5) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -217,6 +207,7 @@ impl crate::RegisterSpec for CLK_SYS_CTRL_SPEC { impl crate::Readable for CLK_SYS_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_sys_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_SYS_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_sys_div.rs b/src/clocks/clk_sys_div.rs index 7a6df7bed..0e32cc7a1 100644 --- a/src/clocks/clk_sys_div.rs +++ b/src/clocks/clk_sys_div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -57,6 +47,7 @@ impl crate::RegisterSpec for CLK_SYS_DIV_SPEC { impl crate::Readable for CLK_SYS_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_sys_div::W`](W) writer structure"] impl crate::Writable for CLK_SYS_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_sys_resus_ctrl.rs b/src/clocks/clk_sys_resus_ctrl.rs index 52f97ddff..b1551c978 100644 --- a/src/clocks/clk_sys_resus_ctrl.rs +++ b/src/clocks/clk_sys_resus_ctrl.rs @@ -69,16 +69,6 @@ impl W { pub fn clear(&mut self) -> CLEAR_W { CLEAR_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = " @@ -91,6 +81,7 @@ impl crate::RegisterSpec for CLK_SYS_RESUS_CTRL_SPEC { impl crate::Readable for CLK_SYS_RESUS_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_sys_resus_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_SYS_RESUS_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_usb_ctrl.rs b/src/clocks/clk_usb_ctrl.rs index ed2135c2b..b67c9bbb3 100644 --- a/src/clocks/clk_usb_ctrl.rs +++ b/src/clocks/clk_usb_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CLK_USB_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] -pub type AUXSRC_R = crate::FieldReader; #[doc = "Selects the auxiliary clock source, will glitch when switching Value on reset: 0"] @@ -32,6 +30,8 @@ impl From for u8 { impl crate::FieldSpec for AUXSRC_A { type Ux = u8; } +#[doc = "Field `AUXSRC` reader - Selects the auxiliary clock source, will glitch when switching"] +pub type AUXSRC_R = crate::FieldReader; impl AUXSRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -197,16 +197,6 @@ impl W { pub fn nudge(&mut self) -> NUDGE_W { NUDGE_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock control, can be changed on-the-fly (except for auxsrc) @@ -219,6 +209,7 @@ impl crate::RegisterSpec for CLK_USB_CTRL_SPEC { impl crate::Readable for CLK_USB_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_usb_ctrl::W`](W) writer structure"] impl crate::Writable for CLK_USB_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/clk_usb_div.rs b/src/clocks/clk_usb_div.rs index 06a152ada..5fec1d8e0 100644 --- a/src/clocks/clk_usb_div.rs +++ b/src/clocks/clk_usb_div.rs @@ -20,16 +20,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor, can be changed on-the-fly @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CLK_USB_DIV_SPEC { impl crate::Readable for CLK_USB_DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`clk_usb_div::W`](W) writer structure"] impl crate::Writable for CLK_USB_DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/fc0_delay.rs b/src/clocks/fc0_delay.rs index c344f4f17..de0b8cf10 100644 --- a/src/clocks/fc0_delay.rs +++ b/src/clocks/fc0_delay.rs @@ -20,16 +20,6 @@ impl W { pub fn fc0_delay(&mut self) -> FC0_DELAY_W { FC0_DELAY_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period @@ -43,6 +33,7 @@ impl crate::RegisterSpec for FC0_DELAY_SPEC { impl crate::Readable for FC0_DELAY_SPEC {} #[doc = "`write(|w| ..)` method takes [`fc0_delay::W`](W) writer structure"] impl crate::Writable for FC0_DELAY_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/fc0_interval.rs b/src/clocks/fc0_interval.rs index ea7f304c7..596f6a01b 100644 --- a/src/clocks/fc0_interval.rs +++ b/src/clocks/fc0_interval.rs @@ -20,16 +20,6 @@ impl W { pub fn fc0_interval(&mut self) -> FC0_INTERVAL_W { FC0_INTERVAL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us @@ -43,6 +33,7 @@ impl crate::RegisterSpec for FC0_INTERVAL_SPEC { impl crate::Readable for FC0_INTERVAL_SPEC {} #[doc = "`write(|w| ..)` method takes [`fc0_interval::W`](W) writer structure"] impl crate::Writable for FC0_INTERVAL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/fc0_max_khz.rs b/src/clocks/fc0_max_khz.rs index cfd8ca30d..f52c4bf84 100644 --- a/src/clocks/fc0_max_khz.rs +++ b/src/clocks/fc0_max_khz.rs @@ -20,16 +20,6 @@ impl W { pub fn fc0_max_khz(&mut self) -> FC0_MAX_KHZ_W { FC0_MAX_KHZ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags @@ -42,6 +32,7 @@ impl crate::RegisterSpec for FC0_MAX_KHZ_SPEC { impl crate::Readable for FC0_MAX_KHZ_SPEC {} #[doc = "`write(|w| ..)` method takes [`fc0_max_khz::W`](W) writer structure"] impl crate::Writable for FC0_MAX_KHZ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/fc0_min_khz.rs b/src/clocks/fc0_min_khz.rs index a07596c41..93c5c41f6 100644 --- a/src/clocks/fc0_min_khz.rs +++ b/src/clocks/fc0_min_khz.rs @@ -20,16 +20,6 @@ impl W { pub fn fc0_min_khz(&mut self) -> FC0_MIN_KHZ_W { FC0_MIN_KHZ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags @@ -42,6 +32,7 @@ impl crate::RegisterSpec for FC0_MIN_KHZ_SPEC { impl crate::Readable for FC0_MIN_KHZ_SPEC {} #[doc = "`write(|w| ..)` method takes [`fc0_min_khz::W`](W) writer structure"] impl crate::Writable for FC0_MIN_KHZ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/fc0_ref_khz.rs b/src/clocks/fc0_ref_khz.rs index 94e2e1489..74a091f9b 100644 --- a/src/clocks/fc0_ref_khz.rs +++ b/src/clocks/fc0_ref_khz.rs @@ -20,16 +20,6 @@ impl W { pub fn fc0_ref_khz(&mut self) -> FC0_REF_KHZ_W { FC0_REF_KHZ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Reference clock frequency in kHz @@ -42,6 +32,7 @@ impl crate::RegisterSpec for FC0_REF_KHZ_SPEC { impl crate::Readable for FC0_REF_KHZ_SPEC {} #[doc = "`write(|w| ..)` method takes [`fc0_ref_khz::W`](W) writer structure"] impl crate::Writable for FC0_REF_KHZ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/fc0_src.rs b/src/clocks/fc0_src.rs index 7d4cf90b9..bfcf72e23 100644 --- a/src/clocks/fc0_src.rs +++ b/src/clocks/fc0_src.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `FC0_SRC` writer"] pub type W = crate::W; -#[doc = "Field `FC0_SRC` reader - "] -pub type FC0_SRC_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -48,6 +46,8 @@ impl From for u8 { impl crate::FieldSpec for FC0_SRC_A { type Ux = u8; } +#[doc = "Field `FC0_SRC` reader - "] +pub type FC0_SRC_R = crate::FieldReader; impl FC0_SRC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -233,16 +233,6 @@ impl W { pub fn fc0_src(&mut self) -> FC0_SRC_W { FC0_SRC_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count @@ -256,6 +246,7 @@ impl crate::RegisterSpec for FC0_SRC_SPEC { impl crate::Readable for FC0_SRC_SPEC {} #[doc = "`write(|w| ..)` method takes [`fc0_src::W`](W) writer structure"] impl crate::Writable for FC0_SRC_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/inte.rs b/src/clocks/inte.rs index 2564abc60..cf327c382 100644 --- a/src/clocks/inte.rs +++ b/src/clocks/inte.rs @@ -20,16 +20,6 @@ impl W { pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W { CLK_SYS_RESUS_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTE_SPEC { impl crate::Readable for INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/intf.rs b/src/clocks/intf.rs index 03d198365..4737fa057 100644 --- a/src/clocks/intf.rs +++ b/src/clocks/intf.rs @@ -20,16 +20,6 @@ impl W { pub fn clk_sys_resus(&mut self) -> CLK_SYS_RESUS_W { CLK_SYS_RESUS_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTF_SPEC { impl crate::Readable for INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/sleep_en0.rs b/src/clocks/sleep_en0.rs index 584754df4..5104a40f9 100644 --- a/src/clocks/sleep_en0.rs +++ b/src/clocks/sleep_en0.rs @@ -485,16 +485,6 @@ impl W { pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W { CLK_SYS_SRAM3_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "enable clock in sleep mode @@ -507,6 +497,7 @@ impl crate::RegisterSpec for SLEEP_EN0_SPEC { impl crate::Readable for SLEEP_EN0_SPEC {} #[doc = "`write(|w| ..)` method takes [`sleep_en0::W`](W) writer structure"] impl crate::Writable for SLEEP_EN0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/sleep_en1.rs b/src/clocks/sleep_en1.rs index d58a75f83..cd786cf31 100644 --- a/src/clocks/sleep_en1.rs +++ b/src/clocks/sleep_en1.rs @@ -230,16 +230,6 @@ impl W { pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W { CLK_SYS_XOSC_W::new(self, 14) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "enable clock in sleep mode @@ -252,6 +242,7 @@ impl crate::RegisterSpec for SLEEP_EN1_SPEC { impl crate::Readable for SLEEP_EN1_SPEC {} #[doc = "`write(|w| ..)` method takes [`sleep_en1::W`](W) writer structure"] impl crate::Writable for SLEEP_EN1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/wake_en0.rs b/src/clocks/wake_en0.rs index 07977344b..b1c0edb48 100644 --- a/src/clocks/wake_en0.rs +++ b/src/clocks/wake_en0.rs @@ -485,16 +485,6 @@ impl W { pub fn clk_sys_sram3(&mut self) -> CLK_SYS_SRAM3_W { CLK_SYS_SRAM3_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "enable clock in wake mode @@ -507,6 +497,7 @@ impl crate::RegisterSpec for WAKE_EN0_SPEC { impl crate::Readable for WAKE_EN0_SPEC {} #[doc = "`write(|w| ..)` method takes [`wake_en0::W`](W) writer structure"] impl crate::Writable for WAKE_EN0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/clocks/wake_en1.rs b/src/clocks/wake_en1.rs index c959cda42..9e4eca31a 100644 --- a/src/clocks/wake_en1.rs +++ b/src/clocks/wake_en1.rs @@ -230,16 +230,6 @@ impl W { pub fn clk_sys_xosc(&mut self) -> CLK_SYS_XOSC_W { CLK_SYS_XOSC_W::new(self, 14) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "enable clock in wake mode @@ -252,6 +242,7 @@ impl crate::RegisterSpec for WAKE_EN1_SPEC { impl crate::Readable for WAKE_EN1_SPEC {} #[doc = "`write(|w| ..)` method takes [`wake_en1::W`](W) writer structure"] impl crate::Writable for WAKE_EN1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma.rs b/src/dma.rs index 33dd1ae05..388108620 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ch: [CH; 12], _reserved1: [u8; 0x0100], diff --git a/src/dma/ch.rs b/src/dma/ch.rs index bfde2f861..d00408bfd 100644 --- a/src/dma/ch.rs +++ b/src/dma/ch.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG"] pub struct CH { ch_read_addr: CH_READ_ADDR, ch_write_addr: CH_WRITE_ADDR, diff --git a/src/dma/ch/ch_al1_ctrl.rs b/src/dma/ch/ch_al1_ctrl.rs index 5f74343dc..36865c3d9 100644 --- a/src/dma/ch/ch_al1_ctrl.rs +++ b/src/dma/ch/ch_al1_ctrl.rs @@ -16,8 +16,6 @@ pub type HIGH_PRIORITY_R = crate::BitReader; This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. Value on reset: 0"] @@ -40,6 +38,8 @@ impl From for u8 { impl crate::FieldSpec for DATA_SIZE_A { type Ux = u8; } +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -106,10 +106,6 @@ pub type INCR_WRITE_R = crate::BitReader; Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_R = crate::FieldReader; #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. @@ -130,6 +126,10 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -172,10 +172,6 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_R = crate::FieldReader; #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ @@ -284,6 +280,10 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -1047,16 +1047,6 @@ impl W { pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA Channel 0 Control and Status @@ -1069,6 +1059,7 @@ impl crate::RegisterSpec for CH_AL1_CTRL_SPEC { impl crate::Readable for CH_AL1_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al1_ctrl::W`](W) writer structure"] impl crate::Writable for CH_AL1_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; } diff --git a/src/dma/ch/ch_al1_read_addr.rs b/src/dma/ch/ch_al1_read_addr.rs index 7add14275..006c80538 100644 --- a/src/dma/ch/ch_al1_read_addr.rs +++ b/src/dma/ch/ch_al1_read_addr.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 READ_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for CH_AL1_READ_ADDR_SPEC { impl crate::Readable for CH_AL1_READ_ADDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al1_read_addr::W`](W) writer structure"] impl crate::Writable for CH_AL1_READ_ADDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al1_trans_count_trig.rs b/src/dma/ch/ch_al1_trans_count_trig.rs index 4e2143bcd..37ed300d8 100644 --- a/src/dma/ch/ch_al1_trans_count_trig.rs +++ b/src/dma/ch/ch_al1_trans_count_trig.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. @@ -37,6 +26,7 @@ impl crate::RegisterSpec for CH_AL1_TRANS_COUNT_TRIG_SPEC { impl crate::Readable for CH_AL1_TRANS_COUNT_TRIG_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al1_trans_count_trig::W`](W) writer structure"] impl crate::Writable for CH_AL1_TRANS_COUNT_TRIG_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al1_write_addr.rs b/src/dma/ch/ch_al1_write_addr.rs index 911b4f38f..749156fec 100644 --- a/src/dma/ch/ch_al1_write_addr.rs +++ b/src/dma/ch/ch_al1_write_addr.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 WRITE_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al1_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al1_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for CH_AL1_WRITE_ADDR_SPEC { impl crate::Readable for CH_AL1_WRITE_ADDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al1_write_addr::W`](W) writer structure"] impl crate::Writable for CH_AL1_WRITE_ADDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al2_ctrl.rs b/src/dma/ch/ch_al2_ctrl.rs index e27327082..dcf6e4082 100644 --- a/src/dma/ch/ch_al2_ctrl.rs +++ b/src/dma/ch/ch_al2_ctrl.rs @@ -16,8 +16,6 @@ pub type HIGH_PRIORITY_R = crate::BitReader; This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. Value on reset: 0"] @@ -40,6 +38,8 @@ impl From for u8 { impl crate::FieldSpec for DATA_SIZE_A { type Ux = u8; } +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -106,10 +106,6 @@ pub type INCR_WRITE_R = crate::BitReader; Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_R = crate::FieldReader; #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. @@ -130,6 +126,10 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -172,10 +172,6 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_R = crate::FieldReader; #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ @@ -284,6 +280,10 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -1047,16 +1047,6 @@ impl W { pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA Channel 0 Control and Status @@ -1069,6 +1059,7 @@ impl crate::RegisterSpec for CH_AL2_CTRL_SPEC { impl crate::Readable for CH_AL2_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al2_ctrl::W`](W) writer structure"] impl crate::Writable for CH_AL2_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; } diff --git a/src/dma/ch/ch_al2_read_addr.rs b/src/dma/ch/ch_al2_read_addr.rs index 2863bd617..0dd73092b 100644 --- a/src/dma/ch/ch_al2_read_addr.rs +++ b/src/dma/ch/ch_al2_read_addr.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 READ_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_read_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_read_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for CH_AL2_READ_ADDR_SPEC { impl crate::Readable for CH_AL2_READ_ADDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al2_read_addr::W`](W) writer structure"] impl crate::Writable for CH_AL2_READ_ADDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al2_trans_count.rs b/src/dma/ch/ch_al2_trans_count.rs index 419ce3485..2053f2ddb 100644 --- a/src/dma/ch/ch_al2_trans_count.rs +++ b/src/dma/ch/ch_al2_trans_count.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 TRANS_COUNT register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al2_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al2_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for CH_AL2_TRANS_COUNT_SPEC { impl crate::Readable for CH_AL2_TRANS_COUNT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al2_trans_count::W`](W) writer structure"] impl crate::Writable for CH_AL2_TRANS_COUNT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al2_write_addr_trig.rs b/src/dma/ch/ch_al2_write_addr_trig.rs index 0a4633c95..a3b75870c 100644 --- a/src/dma/ch/ch_al2_write_addr_trig.rs +++ b/src/dma/ch/ch_al2_write_addr_trig.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. @@ -37,6 +26,7 @@ impl crate::RegisterSpec for CH_AL2_WRITE_ADDR_TRIG_SPEC { impl crate::Readable for CH_AL2_WRITE_ADDR_TRIG_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al2_write_addr_trig::W`](W) writer structure"] impl crate::Writable for CH_AL2_WRITE_ADDR_TRIG_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al3_ctrl.rs b/src/dma/ch/ch_al3_ctrl.rs index f4c48dcb3..f4ea5fd08 100644 --- a/src/dma/ch/ch_al3_ctrl.rs +++ b/src/dma/ch/ch_al3_ctrl.rs @@ -16,8 +16,6 @@ pub type HIGH_PRIORITY_R = crate::BitReader; This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. Value on reset: 0"] @@ -40,6 +38,8 @@ impl From for u8 { impl crate::FieldSpec for DATA_SIZE_A { type Ux = u8; } +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -106,10 +106,6 @@ pub type INCR_WRITE_R = crate::BitReader; Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_R = crate::FieldReader; #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. @@ -130,6 +126,10 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -172,10 +172,6 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_R = crate::FieldReader; #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ @@ -284,6 +280,10 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -1047,16 +1047,6 @@ impl W { pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA Channel 0 Control and Status @@ -1069,6 +1059,7 @@ impl crate::RegisterSpec for CH_AL3_CTRL_SPEC { impl crate::Readable for CH_AL3_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al3_ctrl::W`](W) writer structure"] impl crate::Writable for CH_AL3_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; } diff --git a/src/dma/ch/ch_al3_read_addr_trig.rs b/src/dma/ch/ch_al3_read_addr_trig.rs index b3fd049d8..ce54935ae 100644 --- a/src/dma/ch/ch_al3_read_addr_trig.rs +++ b/src/dma/ch/ch_al3_read_addr_trig.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. @@ -37,6 +26,7 @@ impl crate::RegisterSpec for CH_AL3_READ_ADDR_TRIG_SPEC { impl crate::Readable for CH_AL3_READ_ADDR_TRIG_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al3_read_addr_trig::W`](W) writer structure"] impl crate::Writable for CH_AL3_READ_ADDR_TRIG_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al3_trans_count.rs b/src/dma/ch/ch_al3_trans_count.rs index c8fc30212..7cef663be 100644 --- a/src/dma/ch/ch_al3_trans_count.rs +++ b/src/dma/ch/ch_al3_trans_count.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 TRANS_COUNT register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_trans_count::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_trans_count::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for CH_AL3_TRANS_COUNT_SPEC { impl crate::Readable for CH_AL3_TRANS_COUNT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al3_trans_count::W`](W) writer structure"] impl crate::Writable for CH_AL3_TRANS_COUNT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_al3_write_addr.rs b/src/dma/ch/ch_al3_write_addr.rs index 149f2c8eb..d69813fe0 100644 --- a/src/dma/ch/ch_al3_write_addr.rs +++ b/src/dma/ch/ch_al3_write_addr.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Alias for channel 0 WRITE_ADDR register You can [`read`](crate::generic::Reg::read) this register and get [`ch_al3_write_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ch_al3_write_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for CH_AL3_WRITE_ADDR_SPEC { impl crate::Readable for CH_AL3_WRITE_ADDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_al3_write_addr::W`](W) writer structure"] impl crate::Writable for CH_AL3_WRITE_ADDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_ctrl_trig.rs b/src/dma/ch/ch_ctrl_trig.rs index 24b32e6d7..af5e735ef 100644 --- a/src/dma/ch/ch_ctrl_trig.rs +++ b/src/dma/ch/ch_ctrl_trig.rs @@ -16,8 +16,6 @@ pub type HIGH_PRIORITY_R = crate::BitReader; This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput."] pub type HIGH_PRIORITY_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] -pub type DATA_SIZE_R = crate::FieldReader; #[doc = "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. Value on reset: 0"] @@ -40,6 +38,8 @@ impl From for u8 { impl crate::FieldSpec for DATA_SIZE_A { type Ux = u8; } +#[doc = "Field `DATA_SIZE` reader - Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer."] +pub type DATA_SIZE_R = crate::FieldReader; impl DATA_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -106,10 +106,6 @@ pub type INCR_WRITE_R = crate::BitReader; Generally this should be disabled for memory-to-peripheral transfers."] pub type INCR_WRITE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] -pub type RING_SIZE_R = crate::FieldReader; #[doc = "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. @@ -130,6 +126,10 @@ impl From for u8 { impl crate::FieldSpec for RING_SIZE_A { type Ux = u8; } +#[doc = "Field `RING_SIZE` reader - Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. + + Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL."] +pub type RING_SIZE_R = crate::FieldReader; impl RING_SIZE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -172,10 +172,6 @@ pub type CHAIN_TO_R = crate::FieldReader; #[doc = "Field `CHAIN_TO` writer - When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour."] pub type CHAIN_TO_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. - The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ"] -pub type TREQ_SEL_R = crate::FieldReader; #[doc = "Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ @@ -284,6 +280,10 @@ impl From for u8 { impl crate::FieldSpec for TREQ_SEL_A { type Ux = u8; } +#[doc = "Field `TREQ_SEL` reader - Select a Transfer Request signal. + The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). + 0x0 to 0x3a -> select DREQ n as TREQ"] +pub type TREQ_SEL_R = crate::FieldReader; impl TREQ_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -1047,16 +1047,6 @@ impl W { pub fn read_error(&mut self) -> READ_ERROR_W { READ_ERROR_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA Channel 0 Control and Status @@ -1069,6 +1059,7 @@ impl crate::RegisterSpec for CH_CTRL_TRIG_SPEC { impl crate::Readable for CH_CTRL_TRIG_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_ctrl_trig::W`](W) writer structure"] impl crate::Writable for CH_CTRL_TRIG_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x6000_0000; } diff --git a/src/dma/ch/ch_read_addr.rs b/src/dma/ch/ch_read_addr.rs index 550721d38..f40b0adec 100644 --- a/src/dma/ch/ch_read_addr.rs +++ b/src/dma/ch/ch_read_addr.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "DMA Channel 0 Read Address pointer This register updates automatically each time a read completes. The current value is the next address to be read by this channel. @@ -36,6 +25,7 @@ impl crate::RegisterSpec for CH_READ_ADDR_SPEC { impl crate::Readable for CH_READ_ADDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_read_addr::W`](W) writer structure"] impl crate::Writable for CH_READ_ADDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_trans_count.rs b/src/dma/ch/ch_trans_count.rs index ecd0c9ef5..0868b3baa 100644 --- a/src/dma/ch/ch_trans_count.rs +++ b/src/dma/ch/ch_trans_count.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "DMA Channel 0 Transfer Count Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). @@ -42,6 +31,7 @@ impl crate::RegisterSpec for CH_TRANS_COUNT_SPEC { impl crate::Readable for CH_TRANS_COUNT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_trans_count::W`](W) writer structure"] impl crate::Writable for CH_TRANS_COUNT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch/ch_write_addr.rs b/src/dma/ch/ch_write_addr.rs index f2d4ee83e..2aef1f437 100644 --- a/src/dma/ch/ch_write_addr.rs +++ b/src/dma/ch/ch_write_addr.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "DMA Channel 0 Write Address pointer This register updates automatically each time a write completes. The current value is the next address to be written by this channel. @@ -36,6 +25,7 @@ impl crate::RegisterSpec for CH_WRITE_ADDR_SPEC { impl crate::Readable for CH_WRITE_ADDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch_write_addr::W`](W) writer structure"] impl crate::Writable for CH_WRITE_ADDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/ch0_dbg_ctdreq.rs b/src/dma/ch0_dbg_ctdreq.rs index f2c5fabb0..94a4c0e31 100644 --- a/src/dma/ch0_dbg_ctdreq.rs +++ b/src/dma/ch0_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch0_dbg_ctdreq(&mut self) -> CH0_DBG_CTDREQ_W { CH0_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH0_DBG_CTDREQ_SPEC { impl crate::Readable for CH0_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch0_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH0_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch10_dbg_ctdreq.rs b/src/dma/ch10_dbg_ctdreq.rs index 4443b9feb..354170fe0 100644 --- a/src/dma/ch10_dbg_ctdreq.rs +++ b/src/dma/ch10_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch10_dbg_ctdreq(&mut self) -> CH10_DBG_CTDREQ_W { CH10_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH10_DBG_CTDREQ_SPEC { impl crate::Readable for CH10_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch10_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH10_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch11_dbg_ctdreq.rs b/src/dma/ch11_dbg_ctdreq.rs index b13c3f3aa..4bc819302 100644 --- a/src/dma/ch11_dbg_ctdreq.rs +++ b/src/dma/ch11_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch11_dbg_ctdreq(&mut self) -> CH11_DBG_CTDREQ_W { CH11_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH11_DBG_CTDREQ_SPEC { impl crate::Readable for CH11_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch11_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH11_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch1_dbg_ctdreq.rs b/src/dma/ch1_dbg_ctdreq.rs index c1ef8c736..4f4482b5f 100644 --- a/src/dma/ch1_dbg_ctdreq.rs +++ b/src/dma/ch1_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch1_dbg_ctdreq(&mut self) -> CH1_DBG_CTDREQ_W { CH1_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH1_DBG_CTDREQ_SPEC { impl crate::Readable for CH1_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch1_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH1_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch2_dbg_ctdreq.rs b/src/dma/ch2_dbg_ctdreq.rs index cf96e2631..8217bf82c 100644 --- a/src/dma/ch2_dbg_ctdreq.rs +++ b/src/dma/ch2_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch2_dbg_ctdreq(&mut self) -> CH2_DBG_CTDREQ_W { CH2_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH2_DBG_CTDREQ_SPEC { impl crate::Readable for CH2_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch2_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH2_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch3_dbg_ctdreq.rs b/src/dma/ch3_dbg_ctdreq.rs index 430c6ab84..3565fef13 100644 --- a/src/dma/ch3_dbg_ctdreq.rs +++ b/src/dma/ch3_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch3_dbg_ctdreq(&mut self) -> CH3_DBG_CTDREQ_W { CH3_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH3_DBG_CTDREQ_SPEC { impl crate::Readable for CH3_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch3_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH3_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch4_dbg_ctdreq.rs b/src/dma/ch4_dbg_ctdreq.rs index c1a94af42..670efba69 100644 --- a/src/dma/ch4_dbg_ctdreq.rs +++ b/src/dma/ch4_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch4_dbg_ctdreq(&mut self) -> CH4_DBG_CTDREQ_W { CH4_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH4_DBG_CTDREQ_SPEC { impl crate::Readable for CH4_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch4_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH4_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch5_dbg_ctdreq.rs b/src/dma/ch5_dbg_ctdreq.rs index 2d10c5526..60c56b0b9 100644 --- a/src/dma/ch5_dbg_ctdreq.rs +++ b/src/dma/ch5_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch5_dbg_ctdreq(&mut self) -> CH5_DBG_CTDREQ_W { CH5_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH5_DBG_CTDREQ_SPEC { impl crate::Readable for CH5_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch5_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH5_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch6_dbg_ctdreq.rs b/src/dma/ch6_dbg_ctdreq.rs index 6ffed5a05..f97bfbd5b 100644 --- a/src/dma/ch6_dbg_ctdreq.rs +++ b/src/dma/ch6_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch6_dbg_ctdreq(&mut self) -> CH6_DBG_CTDREQ_W { CH6_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH6_DBG_CTDREQ_SPEC { impl crate::Readable for CH6_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch6_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH6_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch7_dbg_ctdreq.rs b/src/dma/ch7_dbg_ctdreq.rs index 0ab855dd8..59b87fd7f 100644 --- a/src/dma/ch7_dbg_ctdreq.rs +++ b/src/dma/ch7_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch7_dbg_ctdreq(&mut self) -> CH7_DBG_CTDREQ_W { CH7_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH7_DBG_CTDREQ_SPEC { impl crate::Readable for CH7_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch7_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH7_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch8_dbg_ctdreq.rs b/src/dma/ch8_dbg_ctdreq.rs index 2079b74be..87d191d6c 100644 --- a/src/dma/ch8_dbg_ctdreq.rs +++ b/src/dma/ch8_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch8_dbg_ctdreq(&mut self) -> CH8_DBG_CTDREQ_W { CH8_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH8_DBG_CTDREQ_SPEC { impl crate::Readable for CH8_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch8_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH8_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/ch9_dbg_ctdreq.rs b/src/dma/ch9_dbg_ctdreq.rs index cb1c8aa49..8e1f5a499 100644 --- a/src/dma/ch9_dbg_ctdreq.rs +++ b/src/dma/ch9_dbg_ctdreq.rs @@ -20,16 +20,6 @@ impl W { pub fn ch9_dbg_ctdreq(&mut self) -> CH9_DBG_CTDREQ_W { CH9_DBG_CTDREQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CH9_DBG_CTDREQ_SPEC { impl crate::Readable for CH9_DBG_CTDREQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`ch9_dbg_ctdreq::W`](W) writer structure"] impl crate::Writable for CH9_DBG_CTDREQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f; } diff --git a/src/dma/chan_abort.rs b/src/dma/chan_abort.rs index 7457fdcc8..82c47ba6b 100644 --- a/src/dma/chan_abort.rs +++ b/src/dma/chan_abort.rs @@ -28,16 +28,6 @@ impl W { pub fn chan_abort(&mut self) -> CHAN_ABORT_W { CHAN_ABORT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Abort an in-progress transfer sequence on one or more channels @@ -50,6 +40,7 @@ impl crate::RegisterSpec for CHAN_ABORT_SPEC { impl crate::Readable for CHAN_ABORT_SPEC {} #[doc = "`write(|w| ..)` method takes [`chan_abort::W`](W) writer structure"] impl crate::Writable for CHAN_ABORT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/inte0.rs b/src/dma/inte0.rs index b0a80dab2..0d431a47a 100644 --- a/src/dma/inte0.rs +++ b/src/dma/inte0.rs @@ -20,16 +20,6 @@ impl W { pub fn inte0(&mut self) -> INTE0_W { INTE0_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enables for IRQ 0 @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTE0_SPEC { impl crate::Readable for INTE0_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte0::W`](W) writer structure"] impl crate::Writable for INTE0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/inte1.rs b/src/dma/inte1.rs index 724b8e84b..b294bfcbf 100644 --- a/src/dma/inte1.rs +++ b/src/dma/inte1.rs @@ -20,16 +20,6 @@ impl W { pub fn inte1(&mut self) -> INTE1_W { INTE1_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enables for IRQ 1 @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTE1_SPEC { impl crate::Readable for INTE1_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte1::W`](W) writer structure"] impl crate::Writable for INTE1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/intf0.rs b/src/dma/intf0.rs index 24a93e1f0..2a99c3050 100644 --- a/src/dma/intf0.rs +++ b/src/dma/intf0.rs @@ -20,16 +20,6 @@ impl W { pub fn intf0(&mut self) -> INTF0_W { INTF0_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Force Interrupts @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTF0_SPEC { impl crate::Readable for INTF0_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf0::W`](W) writer structure"] impl crate::Writable for INTF0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/intf1.rs b/src/dma/intf1.rs index b7687f705..d79d3bac4 100644 --- a/src/dma/intf1.rs +++ b/src/dma/intf1.rs @@ -20,16 +20,6 @@ impl W { pub fn intf1(&mut self) -> INTF1_W { INTF1_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Force Interrupts for IRQ 1 @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTF1_SPEC { impl crate::Readable for INTF1_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf1::W`](W) writer structure"] impl crate::Writable for INTF1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/intr.rs b/src/dma/intr.rs index 3bd17a6b6..c84d7c909 100644 --- a/src/dma/intr.rs +++ b/src/dma/intr.rs @@ -44,16 +44,6 @@ impl W { pub fn intr(&mut self) -> INTR_W { INTR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Status (raw) @@ -66,6 +56,7 @@ impl crate::RegisterSpec for INTR_SPEC { impl crate::Readable for INTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; } diff --git a/src/dma/ints0.rs b/src/dma/ints0.rs index 59d5a2889..994a68e80 100644 --- a/src/dma/ints0.rs +++ b/src/dma/ints0.rs @@ -24,16 +24,6 @@ impl W { pub fn ints0(&mut self) -> INTS0_W { INTS0_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Status for IRQ 0 @@ -46,6 +36,7 @@ impl crate::RegisterSpec for INTS0_SPEC { impl crate::Readable for INTS0_SPEC {} #[doc = "`write(|w| ..)` method takes [`ints0::W`](W) writer structure"] impl crate::Writable for INTS0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; } diff --git a/src/dma/ints1.rs b/src/dma/ints1.rs index d61693d4f..78beebea6 100644 --- a/src/dma/ints1.rs +++ b/src/dma/ints1.rs @@ -24,16 +24,6 @@ impl W { pub fn ints1(&mut self) -> INTS1_W { INTS1_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Status (masked) for IRQ 1 @@ -46,6 +36,7 @@ impl crate::RegisterSpec for INTS1_SPEC { impl crate::Readable for INTS1_SPEC {} #[doc = "`write(|w| ..)` method takes [`ints1::W`](W) writer structure"] impl crate::Writable for INTS1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff; } diff --git a/src/dma/multi_chan_trigger.rs b/src/dma/multi_chan_trigger.rs index b099758d5..0eb8b0e67 100644 --- a/src/dma/multi_chan_trigger.rs +++ b/src/dma/multi_chan_trigger.rs @@ -20,16 +20,6 @@ impl W { pub fn multi_chan_trigger(&mut self) -> MULTI_CHAN_TRIGGER_W { MULTI_CHAN_TRIGGER_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Trigger one or more channels simultaneously @@ -42,6 +32,7 @@ impl crate::RegisterSpec for MULTI_CHAN_TRIGGER_SPEC { impl crate::Readable for MULTI_CHAN_TRIGGER_SPEC {} #[doc = "`write(|w| ..)` method takes [`multi_chan_trigger::W`](W) writer structure"] impl crate::Writable for MULTI_CHAN_TRIGGER_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/sniff_ctrl.rs b/src/dma/sniff_ctrl.rs index b60c3e5ec..1e4432c05 100644 --- a/src/dma/sniff_ctrl.rs +++ b/src/dma/sniff_ctrl.rs @@ -10,8 +10,6 @@ pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>; pub type DMACH_R = crate::FieldReader; #[doc = "Field `DMACH` writer - DMA channel for Sniffer to observe"] pub type DMACH_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `CALC` reader - "] -pub type CALC_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -40,6 +38,8 @@ impl From for u8 { impl crate::FieldSpec for CALC_A { type Ux = u8; } +#[doc = "Field `CALC` reader - "] +pub type CALC_R = crate::FieldReader; impl CALC_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -212,16 +212,6 @@ impl W { pub fn out_inv(&mut self) -> OUT_INV_W { OUT_INV_W::new(self, 11) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Sniffer Control @@ -234,6 +224,7 @@ impl crate::RegisterSpec for SNIFF_CTRL_SPEC { impl crate::Readable for SNIFF_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`sniff_ctrl::W`](W) writer structure"] impl crate::Writable for SNIFF_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/sniff_data.rs b/src/dma/sniff_data.rs index 429ad223a..298f49b3a 100644 --- a/src/dma/sniff_data.rs +++ b/src/dma/sniff_data.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. @@ -36,6 +25,7 @@ impl crate::RegisterSpec for SNIFF_DATA_SPEC { impl crate::Readable for SNIFF_DATA_SPEC {} #[doc = "`write(|w| ..)` method takes [`sniff_data::W`](W) writer structure"] impl crate::Writable for SNIFF_DATA_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/timer0.rs b/src/dma/timer0.rs index 3c899cb1d..b0c0d1395 100644 --- a/src/dma/timer0.rs +++ b/src/dma/timer0.rs @@ -35,16 +35,6 @@ impl W { pub fn x(&mut self) -> X_W { X_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. @@ -58,6 +48,7 @@ impl crate::RegisterSpec for TIMER0_SPEC { impl crate::Readable for TIMER0_SPEC {} #[doc = "`write(|w| ..)` method takes [`timer0::W`](W) writer structure"] impl crate::Writable for TIMER0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/timer1.rs b/src/dma/timer1.rs index b201ff024..ddf44a745 100644 --- a/src/dma/timer1.rs +++ b/src/dma/timer1.rs @@ -35,16 +35,6 @@ impl W { pub fn x(&mut self) -> X_W { X_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. @@ -58,6 +48,7 @@ impl crate::RegisterSpec for TIMER1_SPEC { impl crate::Readable for TIMER1_SPEC {} #[doc = "`write(|w| ..)` method takes [`timer1::W`](W) writer structure"] impl crate::Writable for TIMER1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/timer2.rs b/src/dma/timer2.rs index d1c86a929..b23b748cb 100644 --- a/src/dma/timer2.rs +++ b/src/dma/timer2.rs @@ -35,16 +35,6 @@ impl W { pub fn x(&mut self) -> X_W { X_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. @@ -58,6 +48,7 @@ impl crate::RegisterSpec for TIMER2_SPEC { impl crate::Readable for TIMER2_SPEC {} #[doc = "`write(|w| ..)` method takes [`timer2::W`](W) writer structure"] impl crate::Writable for TIMER2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/dma/timer3.rs b/src/dma/timer3.rs index d8b0d8a16..0041ca097 100644 --- a/src/dma/timer3.rs +++ b/src/dma/timer3.rs @@ -35,16 +35,6 @@ impl W { pub fn x(&mut self) -> X_W { X_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. @@ -58,6 +48,7 @@ impl crate::RegisterSpec for TIMER3_SPEC { impl crate::Readable for TIMER3_SPEC {} #[doc = "`write(|w| ..)` method takes [`timer3::W`](W) writer structure"] impl crate::Writable for TIMER3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/generic.rs b/src/generic.rs index 59c8e7474..db0f701ae 100644 --- a/src/generic.rs +++ b/src/generic.rs @@ -60,6 +60,8 @@ pub trait Readable: RegisterSpec {} #[doc = ""] #[doc = " Registers marked with `Readable` can be also be `modify`'ed."] pub trait Writable: RegisterSpec { + #[doc = " Is it safe to write any bits to register"] + type Safety; #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] @@ -262,6 +264,29 @@ where #[doc = ""] #[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] pub type W = raw::W; +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +impl W +where + REG: Writable, +{ + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub fn set(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} #[doc = " Field reader."] #[doc = ""] #[doc = " Result of the `read` methods of fields."] @@ -311,9 +336,9 @@ impl BitReader { self.bit() } } -#[doc(hidden)] +#[doc = " Marker for register/field writers which can take any value of specified width"] pub struct Safe; -#[doc(hidden)] +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] pub struct Unsafe; #[doc = " Write field Proxy with unsafe `bits`"] pub type FieldWriter<'a, REG, const WI: u8, FI = u8> = raw::FieldWriter<'a, REG, WI, FI, Unsafe>; diff --git a/src/i2c0.rs b/src/i2c0.rs index b64464f01..5e09fdf84 100644 --- a/src/i2c0.rs +++ b/src/i2c0.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ic_con: IC_CON, ic_tar: IC_TAR, diff --git a/src/i2c0/ic_ack_general_call.rs b/src/i2c0/ic_ack_general_call.rs index b8d374795..d012db2fe 100644 --- a/src/i2c0/ic_ack_general_call.rs +++ b/src/i2c0/ic_ack_general_call.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `IC_ACK_GENERAL_CALL` writer"] pub type W = crate::W; -#[doc = "Field `ACK_GEN_CALL` reader - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] -pub type ACK_GEN_CALL_R = crate::BitReader; #[doc = "ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). Value on reset: 1"] @@ -20,6 +18,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ACK_GEN_CALL` reader - ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe)."] +pub type ACK_GEN_CALL_R = crate::BitReader; impl ACK_GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -71,16 +71,6 @@ impl W { pub fn ack_gen_call(&mut self) -> ACK_GEN_CALL_W { ACK_GEN_CALL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C ACK General Call Register @@ -97,6 +87,7 @@ impl crate::RegisterSpec for IC_ACK_GENERAL_CALL_SPEC { impl crate::Readable for IC_ACK_GENERAL_CALL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_ack_general_call::W`](W) writer structure"] impl crate::Writable for IC_ACK_GENERAL_CALL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_con.rs b/src/i2c0/ic_con.rs index 71fb8a73e..a210ffffa 100644 --- a/src/i2c0/ic_con.rs +++ b/src/i2c0/ic_con.rs @@ -2,10 +2,6 @@ pub type R = crate::R; #[doc = "Register `IC_CON` writer"] pub type W = crate::W; -#[doc = "Field `MASTER_MODE` reader - This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] -pub type MASTER_MODE_R = crate::BitReader; #[doc = "This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. @@ -24,6 +20,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `MASTER_MODE` reader - This bit controls whether the DW_apb_i2c master is enabled. + + NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'."] +pub type MASTER_MODE_R = crate::BitReader; impl MASTER_MODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -63,18 +63,6 @@ where self.variant(MASTER_MODE_A::ENABLED) } } -#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. - - 1: standard mode (100 kbit/s) - - 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) - - 3: high speed mode (3.4 Mbit/s) - - Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] -pub type SPEED_R = crate::FieldReader; #[doc = "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. @@ -107,6 +95,18 @@ impl From for u8 { impl crate::FieldSpec for SPEED_A { type Ux = u8; } +#[doc = "Field `SPEED` reader - These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. + + This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. + + 1: standard mode (100 kbit/s) + + 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) + + 3: high speed mode (3.4 Mbit/s) + + Note: This field is not applicable when IC_ULTRA_FAST_MODE=1"] +pub type SPEED_R = crate::FieldReader; impl SPEED_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -167,8 +167,6 @@ where self.variant(SPEED_A::HIGH) } } -#[doc = "Field `IC_10BITADDR_SLAVE` reader - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] -pub type IC_10BITADDR_SLAVE_R = crate::BitReader; #[doc = "When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. Value on reset: 0"] @@ -185,6 +183,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `IC_10BITADDR_SLAVE` reader - When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register."] +pub type IC_10BITADDR_SLAVE_R = crate::BitReader; impl IC_10BITADDR_SLAVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -222,8 +222,6 @@ where self.variant(IC_10BITADDR_SLAVE_A::ADDR_10BITS) } } -#[doc = "Field `IC_10BITADDR_MASTER` reader - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] -pub type IC_10BITADDR_MASTER_R = crate::BitReader; #[doc = "Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing Value on reset: 0"] @@ -240,6 +238,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `IC_10BITADDR_MASTER` reader - Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing"] +pub type IC_10BITADDR_MASTER_R = crate::BitReader; impl IC_10BITADDR_MASTER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -277,10 +277,6 @@ where self.variant(IC_10BITADDR_MASTER_A::ADDR_10BITS) } } -#[doc = "Field `IC_RESTART_EN` reader - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. - - Reset value: ENABLED"] -pub type IC_RESTART_EN_R = crate::BitReader; #[doc = "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED @@ -299,6 +295,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `IC_RESTART_EN` reader - Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. + + Reset value: ENABLED"] +pub type IC_RESTART_EN_R = crate::BitReader; impl IC_RESTART_EN_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -338,12 +338,6 @@ where self.variant(IC_RESTART_EN_A::ENABLED) } } -#[doc = "Field `IC_SLAVE_DISABLE` reader - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. - - NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] -pub type IC_SLAVE_DISABLE_R = crate::BitReader; #[doc = "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. @@ -364,6 +358,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `IC_SLAVE_DISABLE` reader - This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. + + If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. + + NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0."] +pub type IC_SLAVE_DISABLE_R = crate::BitReader; impl IC_SLAVE_DISABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -405,10 +405,6 @@ where self.variant(IC_SLAVE_DISABLE_A::SLAVE_DISABLED) } } -#[doc = "Field `STOP_DET_IFADDRESSED` reader - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 - - NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] -pub type STOP_DET_IFADDRESSED_R = crate::BitReader; #[doc = "In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). @@ -427,6 +423,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `STOP_DET_IFADDRESSED` reader - In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 + + NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR)."] +pub type STOP_DET_IFADDRESSED_R = crate::BitReader; impl STOP_DET_IFADDRESSED_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -466,10 +466,6 @@ where self.variant(STOP_DET_IFADDRESSED_A::ENABLED) } } -#[doc = "Field `TX_EMPTY_CTRL` reader - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0."] -pub type TX_EMPTY_CTRL_R = crate::BitReader; #[doc = "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. @@ -488,6 +484,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TX_EMPTY_CTRL` reader - This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. + + Reset value: 0x0."] +pub type TX_EMPTY_CTRL_R = crate::BitReader; impl TX_EMPTY_CTRL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -527,10 +527,6 @@ where self.variant(TX_EMPTY_CTRL_A::ENABLED) } } -#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` reader - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0."] -pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; #[doc = "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. @@ -549,6 +545,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RX_FIFO_FULL_HLD_CTRL` reader - This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. + + Reset value: 0x0."] +pub type RX_FIFO_FULL_HLD_CTRL_R = crate::BitReader; impl RX_FIFO_FULL_HLD_CTRL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -745,16 +745,6 @@ impl W { pub fn rx_fifo_full_hld_ctrl(&mut self) -> RX_FIFO_FULL_HLD_CTRL_W { RX_FIFO_FULL_HLD_CTRL_W::new(self, 9) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE\\[0\\] register being set to 0. Writes at other times have no effect. @@ -770,6 +760,7 @@ impl crate::RegisterSpec for IC_CON_SPEC { impl crate::Readable for IC_CON_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_con::W`](W) writer structure"] impl crate::Writable for IC_CON_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_data_cmd.rs b/src/i2c0/ic_data_cmd.rs index 76902162b..a0cd32bcb 100644 --- a/src/i2c0/ic_data_cmd.rs +++ b/src/i2c0/ic_data_cmd.rs @@ -10,14 +10,6 @@ pub type DAT_R = crate::FieldReader; Reset value: 0x0"] pub type DAT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>; -#[doc = "Field `CMD` reader - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. - - When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. - - Reset value: 0x0"] -pub type CMD_R = crate::BitReader; #[doc = "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. @@ -40,6 +32,14 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `CMD` reader - This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. + + When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. + + When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. + + Reset value: 0x0"] +pub type CMD_R = crate::BitReader; impl CMD_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -83,10 +83,6 @@ where self.variant(CMD_A::READ) } } -#[doc = "Field `STOP` reader - This bit controls whether a STOP is issued after the byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] -pub type STOP_R = crate::BitReader; #[doc = "This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 @@ -105,6 +101,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `STOP` reader - This bit controls whether a STOP is issued after the byte is sent or received. + + - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0"] +pub type STOP_R = crate::BitReader; impl STOP_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -144,14 +144,6 @@ where self.variant(STOP_A::ENABLE) } } -#[doc = "Field `RESTART` reader - This bit controls whether a RESTART is issued before the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. - - Reset value: 0x0"] -pub type RESTART_R = crate::BitReader; #[doc = "This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. @@ -174,6 +166,14 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RESTART` reader - This bit controls whether a RESTART is issued before the byte is sent or received. + + 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. + + Reset value: 0x0"] +pub type RESTART_R = crate::BitReader; impl RESTART_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -217,21 +217,6 @@ where self.variant(RESTART_A::ENABLE) } } -#[doc = "Field `FIRST_DATA_BYTE` reader - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] -(offset 0x10) and then perform the second read \\[15:8\\] -(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). - - 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] -(offset 0x11) if not interested in FIRST_DATA_BYTE status."] -pub type FIRST_DATA_BYTE_R = crate::BitReader; #[doc = "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 @@ -261,6 +246,21 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `FIRST_DATA_BYTE` reader - Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. + + Reset value : 0x0 + + NOTE: In case of APB_DATA_WIDTH=8, + + 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. + + 2. In order to read the 11 bit, the user has to perform the first data byte read \\[7:0\\] +(offset 0x10) and then perform the second read \\[15:8\\] +(offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). + + 3. The 11th bit is an optional read field, user can ignore 2nd byte read \\[15:8\\] +(offset 0x11) if not interested in FIRST_DATA_BYTE status."] +pub type FIRST_DATA_BYTE_R = crate::BitReader; impl FIRST_DATA_BYTE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -378,16 +378,6 @@ impl W { pub fn restart(&mut self) -> RESTART_W { RESTART_W::new(self, 10) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. @@ -404,6 +394,7 @@ impl crate::RegisterSpec for IC_DATA_CMD_SPEC { impl crate::Readable for IC_DATA_CMD_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_data_cmd::W`](W) writer structure"] impl crate::Writable for IC_DATA_CMD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_dma_cr.rs b/src/i2c0/ic_dma_cr.rs index fe533fc32..73ace2dd3 100644 --- a/src/i2c0/ic_dma_cr.rs +++ b/src/i2c0/ic_dma_cr.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `IC_DMA_CR` writer"] pub type W = crate::W; -#[doc = "Field `RDMAE` reader - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] -pub type RDMAE_R = crate::BitReader; #[doc = "Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 Value on reset: 0"] @@ -20,6 +18,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RDMAE` reader - Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0"] +pub type RDMAE_R = crate::BitReader; impl RDMAE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -57,8 +57,6 @@ where self.variant(RDMAE_A::ENABLED) } } -#[doc = "Field `TDMAE` reader - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] -pub type TDMAE_R = crate::BitReader; #[doc = "Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 Value on reset: 0"] @@ -75,6 +73,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TDMAE` reader - Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0"] +pub type TDMAE_R = crate::BitReader; impl TDMAE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -137,16 +137,6 @@ impl W { pub fn tdmae(&mut self) -> TDMAE_W { TDMAE_W::new(self, 1) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA Control Register @@ -161,6 +151,7 @@ impl crate::RegisterSpec for IC_DMA_CR_SPEC { impl crate::Readable for IC_DMA_CR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_dma_cr::W`](W) writer structure"] impl crate::Writable for IC_DMA_CR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_dma_rdlr.rs b/src/i2c0/ic_dma_rdlr.rs index 97a48a832..0acb62409 100644 --- a/src/i2c0/ic_dma_rdlr.rs +++ b/src/i2c0/ic_dma_rdlr.rs @@ -28,16 +28,6 @@ impl W { pub fn dmardl(&mut self) -> DMARDL_W { DMARDL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Receive Data Level Register @@ -50,6 +40,7 @@ impl crate::RegisterSpec for IC_DMA_RDLR_SPEC { impl crate::Readable for IC_DMA_RDLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_dma_rdlr::W`](W) writer structure"] impl crate::Writable for IC_DMA_RDLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_dma_tdlr.rs b/src/i2c0/ic_dma_tdlr.rs index 14ab16169..9afd98445 100644 --- a/src/i2c0/ic_dma_tdlr.rs +++ b/src/i2c0/ic_dma_tdlr.rs @@ -28,16 +28,6 @@ impl W { pub fn dmatdl(&mut self) -> DMATDL_W { DMATDL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA Transmit Data Level Register @@ -50,6 +40,7 @@ impl crate::RegisterSpec for IC_DMA_TDLR_SPEC { impl crate::Readable for IC_DMA_TDLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_dma_tdlr::W`](W) writer structure"] impl crate::Writable for IC_DMA_TDLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_enable.rs b/src/i2c0/ic_enable.rs index 2bf8ecbdc..960e02f5c 100644 --- a/src/i2c0/ic_enable.rs +++ b/src/i2c0/ic_enable.rs @@ -2,14 +2,6 @@ pub type R = crate::R; #[doc = "Register `IC_ENABLE` writer"] pub type W = crate::W; -#[doc = "Field `ENABLE` reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. - - In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' - - Reset value: 0x0"] -pub type ENABLE_R = crate::BitReader; #[doc = "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. @@ -32,6 +24,14 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ENABLE` reader - Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. + + When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. + + In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' + + Reset value: 0x0"] +pub type ENABLE_R = crate::BitReader; impl ENABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -75,12 +75,6 @@ where self.variant(ENABLE_A::ENABLED) } } -#[doc = "Field `ABORT` reader - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. - - For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. - - Reset value: 0x0"] -pub type ABORT_R = crate::BitReader; #[doc = "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. @@ -101,6 +95,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABORT` reader - When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. + + For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. + + Reset value: 0x0"] +pub type ABORT_R = crate::BitReader; impl ABORT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -142,9 +142,6 @@ where self.variant(ABORT_A::ENABLED) } } -#[doc = "Field `TX_CMD_BLOCK` reader - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] -== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] -pub type TX_CMD_BLOCK_R = crate::BitReader; #[doc = "In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT @@ -162,6 +159,9 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TX_CMD_BLOCK` reader - In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS\\[2\\]==1) and Master is in Idle state (IC_STATUS\\[5\\] +== 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT"] +pub type TX_CMD_BLOCK_R = crate::BitReader; impl TX_CMD_BLOCK_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -258,16 +258,6 @@ impl W { pub fn tx_cmd_block(&mut self) -> TX_CMD_BLOCK_W { TX_CMD_BLOCK_W::new(self, 2) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Enable Register @@ -280,6 +270,7 @@ impl crate::RegisterSpec for IC_ENABLE_SPEC { impl crate::Readable for IC_ENABLE_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_enable::W`](W) writer structure"] impl crate::Writable for IC_ENABLE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_enable_status.rs b/src/i2c0/ic_enable_status.rs index 22620f9a7..b431554b3 100644 --- a/src/i2c0/ic_enable_status.rs +++ b/src/i2c0/ic_enable_status.rs @@ -1,9 +1,5 @@ #[doc = "Register `IC_ENABLE_STATUS` reader"] pub type R = crate::R; -#[doc = "Field `IC_EN` reader - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0"] -pub type IC_EN_R = crate::BitReader; #[doc = "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0 @@ -22,6 +18,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `IC_EN` reader - ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). + + Reset value: 0x0"] +pub type IC_EN_R = crate::BitReader; impl IC_EN_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -42,25 +42,6 @@ impl IC_EN_R { *self == IC_EN_A::ENABLED } } -#[doc = "Field `SLV_DISABLED_WHILE_BUSY` reader - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation from a remote master. - - When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit will also be set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0"] -pub type SLV_DISABLED_WHILE_BUSY_R = crate::BitReader; #[doc = "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; @@ -94,6 +75,25 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `SLV_DISABLED_WHILE_BUSY` reader - Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: + + (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; + + OR, + + (b) address and data bytes of the Slave-Receiver operation from a remote master. + + When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit will also be set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0"] +pub type SLV_DISABLED_WHILE_BUSY_R = crate::BitReader; impl SLV_DISABLED_WHILE_BUSY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -114,17 +114,6 @@ impl SLV_DISABLED_WHILE_BUSY_R { *self == SLV_DISABLED_WHILE_BUSY_A::ACTIVE } } -#[doc = "Field `SLV_RX_DATA_LOST` reader - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] -has been set to 0, then this bit is also set to 1. - - When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. - - Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. - - Reset value: 0x0"] -pub type SLV_RX_DATA_LOST_R = crate::BitReader; #[doc = "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] @@ -150,6 +139,17 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `SLV_RX_DATA_LOST` reader - Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. + + Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE\\[0\\] +has been set to 0, then this bit is also set to 1. + + When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. + + Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. + + Reset value: 0x0"] +pub type SLV_RX_DATA_LOST_R = crate::BitReader; impl SLV_RX_DATA_LOST_R { #[doc = "Get enumerated values variant"] #[inline(always)] diff --git a/src/i2c0/ic_fs_scl_hcnt.rs b/src/i2c0/ic_fs_scl_hcnt.rs index 42cbd8770..85d134b2d 100644 --- a/src/i2c0/ic_fs_scl_hcnt.rs +++ b/src/i2c0/ic_fs_scl_hcnt.rs @@ -40,16 +40,6 @@ register being set to 0. Writes at other times have no effect. pub fn ic_fs_scl_hcnt(&mut self) -> IC_FS_SCL_HCNT_W { IC_FS_SCL_HCNT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register @@ -62,6 +52,7 @@ impl crate::RegisterSpec for IC_FS_SCL_HCNT_SPEC { impl crate::Readable for IC_FS_SCL_HCNT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_fs_scl_hcnt::W`](W) writer structure"] impl crate::Writable for IC_FS_SCL_HCNT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_fs_scl_lcnt.rs b/src/i2c0/ic_fs_scl_lcnt.rs index 8d8ad5db3..046f1eb3a 100644 --- a/src/i2c0/ic_fs_scl_lcnt.rs +++ b/src/i2c0/ic_fs_scl_lcnt.rs @@ -48,16 +48,6 @@ register being set to 0. Writes at other times have no effect. pub fn ic_fs_scl_lcnt(&mut self) -> IC_FS_SCL_LCNT_W { IC_FS_SCL_LCNT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register @@ -70,6 +60,7 @@ impl crate::RegisterSpec for IC_FS_SCL_LCNT_SPEC { impl crate::Readable for IC_FS_SCL_LCNT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_fs_scl_lcnt::W`](W) writer structure"] impl crate::Writable for IC_FS_SCL_LCNT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_fs_spklen.rs b/src/i2c0/ic_fs_spklen.rs index 6cde4cc20..59d99b468 100644 --- a/src/i2c0/ic_fs_spklen.rs +++ b/src/i2c0/ic_fs_spklen.rs @@ -24,16 +24,6 @@ register being set to 0. Writes at other times have no effect. The minimum valid pub fn ic_fs_spklen(&mut self) -> IC_FS_SPKLEN_W { IC_FS_SPKLEN_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C SS, FS or FM+ spike suppression limit @@ -48,6 +38,7 @@ impl crate::RegisterSpec for IC_FS_SPKLEN_SPEC { impl crate::Readable for IC_FS_SPKLEN_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_fs_spklen::W`](W) writer structure"] impl crate::Writable for IC_FS_SPKLEN_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_intr_mask.rs b/src/i2c0/ic_intr_mask.rs index 57c2b49fe..f2512f11c 100644 --- a/src/i2c0/ic_intr_mask.rs +++ b/src/i2c0/ic_intr_mask.rs @@ -2,10 +2,6 @@ pub type R = crate::R; #[doc = "Register `IC_INTR_MASK` writer"] pub type W = crate::W; -#[doc = "Field `M_RX_UNDER` reader - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_RX_UNDER_R = crate::BitReader; #[doc = "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -24,6 +20,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_RX_UNDER` reader - This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_RX_UNDER_R = crate::BitReader; impl M_RX_UNDER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -63,10 +63,6 @@ where self.variant(M_RX_UNDER_A::DISABLED) } } -#[doc = "Field `M_RX_OVER` reader - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_RX_OVER_R = crate::BitReader; #[doc = "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -85,6 +81,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_RX_OVER` reader - This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_RX_OVER_R = crate::BitReader; impl M_RX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -124,10 +124,6 @@ where self.variant(M_RX_OVER_A::DISABLED) } } -#[doc = "Field `M_RX_FULL` reader - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_RX_FULL_R = crate::BitReader; #[doc = "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -146,6 +142,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_RX_FULL` reader - This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_RX_FULL_R = crate::BitReader; impl M_RX_FULL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -185,10 +185,6 @@ where self.variant(M_RX_FULL_A::DISABLED) } } -#[doc = "Field `M_TX_OVER` reader - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_TX_OVER_R = crate::BitReader; #[doc = "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -207,6 +203,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_TX_OVER` reader - This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_TX_OVER_R = crate::BitReader; impl M_TX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -246,10 +246,6 @@ where self.variant(M_TX_OVER_A::DISABLED) } } -#[doc = "Field `M_TX_EMPTY` reader - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_TX_EMPTY_R = crate::BitReader; #[doc = "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -268,6 +264,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_TX_EMPTY` reader - This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_TX_EMPTY_R = crate::BitReader; impl M_TX_EMPTY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -307,10 +307,6 @@ where self.variant(M_TX_EMPTY_A::DISABLED) } } -#[doc = "Field `M_RD_REQ` reader - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_RD_REQ_R = crate::BitReader; #[doc = "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -329,6 +325,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_RD_REQ` reader - This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_RD_REQ_R = crate::BitReader; impl M_RD_REQ_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -368,10 +368,6 @@ where self.variant(M_RD_REQ_A::DISABLED) } } -#[doc = "Field `M_TX_ABRT` reader - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_TX_ABRT_R = crate::BitReader; #[doc = "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -390,6 +386,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_TX_ABRT` reader - This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_TX_ABRT_R = crate::BitReader; impl M_TX_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -429,10 +429,6 @@ where self.variant(M_TX_ABRT_A::DISABLED) } } -#[doc = "Field `M_RX_DONE` reader - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_RX_DONE_R = crate::BitReader; #[doc = "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -451,6 +447,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_RX_DONE` reader - This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_RX_DONE_R = crate::BitReader; impl M_RX_DONE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -490,10 +490,6 @@ where self.variant(M_RX_DONE_A::DISABLED) } } -#[doc = "Field `M_ACTIVITY` reader - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] -pub type M_ACTIVITY_R = crate::BitReader; #[doc = "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 @@ -512,6 +508,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_ACTIVITY` reader - This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] +pub type M_ACTIVITY_R = crate::BitReader; impl M_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -551,10 +551,6 @@ where self.variant(M_ACTIVITY_A::DISABLED) } } -#[doc = "Field `M_STOP_DET` reader - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] -pub type M_STOP_DET_R = crate::BitReader; #[doc = "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 @@ -573,6 +569,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_STOP_DET` reader - This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] +pub type M_STOP_DET_R = crate::BitReader; impl M_STOP_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -612,10 +612,6 @@ where self.variant(M_STOP_DET_A::DISABLED) } } -#[doc = "Field `M_START_DET` reader - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] -pub type M_START_DET_R = crate::BitReader; #[doc = "This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 @@ -634,6 +630,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_START_DET` reader - This bit masks the R_START_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] +pub type M_START_DET_R = crate::BitReader; impl M_START_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -673,10 +673,6 @@ where self.variant(M_START_DET_A::DISABLED) } } -#[doc = "Field `M_GEN_CALL` reader - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. - - Reset value: 0x1"] -pub type M_GEN_CALL_R = crate::BitReader; #[doc = "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 @@ -695,6 +691,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_GEN_CALL` reader - This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. + + Reset value: 0x1"] +pub type M_GEN_CALL_R = crate::BitReader; impl M_GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -734,10 +734,6 @@ where self.variant(M_GEN_CALL_A::DISABLED) } } -#[doc = "Field `M_RESTART_DET` reader - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. - - Reset value: 0x0"] -pub type M_RESTART_DET_R = crate::BitReader; #[doc = "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 @@ -756,6 +752,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `M_RESTART_DET` reader - This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. + + Reset value: 0x0"] +pub type M_RESTART_DET_R = crate::BitReader; impl M_RESTART_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -993,16 +993,6 @@ impl W { pub fn m_restart_det(&mut self) -> M_RESTART_DET_W { M_RESTART_DET_W::new(self, 12) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Interrupt Mask Register. @@ -1017,6 +1007,7 @@ impl crate::RegisterSpec for IC_INTR_MASK_SPEC { impl crate::Readable for IC_INTR_MASK_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_intr_mask::W`](W) writer structure"] impl crate::Writable for IC_INTR_MASK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_intr_stat.rs b/src/i2c0/ic_intr_stat.rs index 5a50de183..c8aea206a 100644 --- a/src/i2c0/ic_intr_stat.rs +++ b/src/i2c0/ic_intr_stat.rs @@ -1,9 +1,5 @@ #[doc = "Register `IC_INTR_STAT` reader"] pub type R = crate::R; -#[doc = "Field `R_RX_UNDER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. - - Reset value: 0x0"] -pub type R_RX_UNDER_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0 @@ -22,6 +18,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_RX_UNDER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. + + Reset value: 0x0"] +pub type R_RX_UNDER_R = crate::BitReader; impl R_RX_UNDER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -42,10 +42,6 @@ impl R_RX_UNDER_R { *self == R_RX_UNDER_A::ACTIVE } } -#[doc = "Field `R_RX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. - - Reset value: 0x0"] -pub type R_RX_OVER_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 @@ -64,6 +60,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_RX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. + + Reset value: 0x0"] +pub type R_RX_OVER_R = crate::BitReader; impl R_RX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -84,10 +84,6 @@ impl R_RX_OVER_R { *self == R_RX_OVER_A::ACTIVE } } -#[doc = "Field `R_RX_FULL` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. - - Reset value: 0x0"] -pub type R_RX_FULL_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0 @@ -106,6 +102,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_RX_FULL` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. + + Reset value: 0x0"] +pub type R_RX_FULL_R = crate::BitReader; impl R_RX_FULL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -126,10 +126,6 @@ impl R_RX_FULL_R { *self == R_RX_FULL_A::ACTIVE } } -#[doc = "Field `R_TX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. - - Reset value: 0x0"] -pub type R_TX_OVER_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0 @@ -148,6 +144,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_TX_OVER` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. + + Reset value: 0x0"] +pub type R_TX_OVER_R = crate::BitReader; impl R_TX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -168,10 +168,6 @@ impl R_TX_OVER_R { *self == R_TX_OVER_A::ACTIVE } } -#[doc = "Field `R_TX_EMPTY` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. - - Reset value: 0x0"] -pub type R_TX_EMPTY_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0 @@ -190,6 +186,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_TX_EMPTY` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. + + Reset value: 0x0"] +pub type R_TX_EMPTY_R = crate::BitReader; impl R_TX_EMPTY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -210,10 +210,6 @@ impl R_TX_EMPTY_R { *self == R_TX_EMPTY_A::ACTIVE } } -#[doc = "Field `R_RD_REQ` reader - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. - - Reset value: 0x0"] -pub type R_RD_REQ_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0 @@ -232,6 +228,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_RD_REQ` reader - See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. + + Reset value: 0x0"] +pub type R_RD_REQ_R = crate::BitReader; impl R_RD_REQ_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -252,10 +252,6 @@ impl R_RD_REQ_R { *self == R_RD_REQ_A::ACTIVE } } -#[doc = "Field `R_TX_ABRT` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. - - Reset value: 0x0"] -pub type R_TX_ABRT_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0 @@ -274,6 +270,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_TX_ABRT` reader - See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. + + Reset value: 0x0"] +pub type R_TX_ABRT_R = crate::BitReader; impl R_TX_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -294,10 +294,6 @@ impl R_TX_ABRT_R { *self == R_TX_ABRT_A::ACTIVE } } -#[doc = "Field `R_RX_DONE` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. - - Reset value: 0x0"] -pub type R_RX_DONE_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0 @@ -316,6 +312,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_RX_DONE` reader - See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. + + Reset value: 0x0"] +pub type R_RX_DONE_R = crate::BitReader; impl R_RX_DONE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -336,10 +336,6 @@ impl R_RX_DONE_R { *self == R_RX_DONE_A::ACTIVE } } -#[doc = "Field `R_ACTIVITY` reader - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. - - Reset value: 0x0"] -pub type R_ACTIVITY_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0 @@ -358,6 +354,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_ACTIVITY` reader - See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. + + Reset value: 0x0"] +pub type R_ACTIVITY_R = crate::BitReader; impl R_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -378,10 +378,6 @@ impl R_ACTIVITY_R { *self == R_ACTIVITY_A::ACTIVE } } -#[doc = "Field `R_STOP_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. - - Reset value: 0x0"] -pub type R_STOP_DET_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0 @@ -400,6 +396,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_STOP_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. + + Reset value: 0x0"] +pub type R_STOP_DET_R = crate::BitReader; impl R_STOP_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -420,10 +420,6 @@ impl R_STOP_DET_R { *self == R_STOP_DET_A::ACTIVE } } -#[doc = "Field `R_START_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. - - Reset value: 0x0"] -pub type R_START_DET_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0 @@ -442,6 +438,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_START_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. + + Reset value: 0x0"] +pub type R_START_DET_R = crate::BitReader; impl R_START_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -462,10 +462,6 @@ impl R_START_DET_R { *self == R_START_DET_A::ACTIVE } } -#[doc = "Field `R_GEN_CALL` reader - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. - - Reset value: 0x0"] -pub type R_GEN_CALL_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0 @@ -484,6 +480,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_GEN_CALL` reader - See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. + + Reset value: 0x0"] +pub type R_GEN_CALL_R = crate::BitReader; impl R_GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -504,10 +504,6 @@ impl R_GEN_CALL_R { *self == R_GEN_CALL_A::ACTIVE } } -#[doc = "Field `R_RESTART_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. - - Reset value: 0x0"] -pub type R_RESTART_DET_R = crate::BitReader; #[doc = "See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0 @@ -526,6 +522,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `R_RESTART_DET` reader - See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. + + Reset value: 0x0"] +pub type R_RESTART_DET_R = crate::BitReader; impl R_RESTART_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] diff --git a/src/i2c0/ic_raw_intr_stat.rs b/src/i2c0/ic_raw_intr_stat.rs index 2484fbdd3..527538c31 100644 --- a/src/i2c0/ic_raw_intr_stat.rs +++ b/src/i2c0/ic_raw_intr_stat.rs @@ -1,9 +1,5 @@ #[doc = "Register `IC_RAW_INTR_STAT` reader"] pub type R = crate::R; -#[doc = "Field `RX_UNDER` reader - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0"] -pub type RX_UNDER_R = crate::BitReader; #[doc = "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 @@ -22,6 +18,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RX_UNDER` reader - Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0"] +pub type RX_UNDER_R = crate::BitReader; impl RX_UNDER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -42,12 +42,6 @@ impl RX_UNDER_R { *self == RX_UNDER_A::ACTIVE } } -#[doc = "Field `RX_OVER` reader - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. - - Reset value: 0x0"] -pub type RX_OVER_R = crate::BitReader; #[doc = "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. @@ -68,6 +62,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RX_OVER` reader - Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE\\[0\\]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. + + Reset value: 0x0"] +pub type RX_OVER_R = crate::BitReader; impl RX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -88,10 +88,6 @@ impl RX_OVER_R { *self == RX_OVER_A::ACTIVE } } -#[doc = "Field `RX_FULL` reader - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. - - Reset value: 0x0"] -pub type RX_FULL_R = crate::BitReader; #[doc = "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0 @@ -110,6 +106,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RX_FULL` reader - Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE\\[0\\]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. + + Reset value: 0x0"] +pub type RX_FULL_R = crate::BitReader; impl RX_FULL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -130,10 +130,6 @@ impl RX_FULL_R { *self == RX_FULL_A::ACTIVE } } -#[doc = "Field `TX_OVER` reader - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0"] -pub type TX_OVER_R = crate::BitReader; #[doc = "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 @@ -152,6 +148,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TX_OVER` reader - Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. + + Reset value: 0x0"] +pub type TX_OVER_R = crate::BitReader; impl TX_OVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -172,11 +172,6 @@ impl TX_OVER_R { *self == TX_OVER_A::ACTIVE } } -#[doc = "Field `TX_EMPTY` reader - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] -is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. - - Reset value: 0x0."] -pub type TX_EMPTY_R = crate::BitReader; #[doc = "The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. @@ -196,6 +191,11 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TX_EMPTY` reader - The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE\\[0\\] +is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. + + Reset value: 0x0."] +pub type TX_EMPTY_R = crate::BitReader; impl TX_EMPTY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -216,10 +216,6 @@ impl TX_EMPTY_R { *self == TX_EMPTY_A::ACTIVE } } -#[doc = "Field `RD_REQ` reader - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. - - Reset value: 0x0"] -pub type RD_REQ_R = crate::BitReader; #[doc = "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0 @@ -238,6 +234,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RD_REQ` reader - This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. + + Reset value: 0x0"] +pub type RD_REQ_R = crate::BitReader; impl RD_REQ_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -258,12 +258,6 @@ impl RD_REQ_R { *self == RD_REQ_A::ACTIVE } } -#[doc = "Field `TX_ABRT` reader - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. - - Reset value: 0x0"] -pub type TX_ABRT_R = crate::BitReader; #[doc = "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. @@ -284,6 +278,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TX_ABRT` reader - This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. + + Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. + + Reset value: 0x0"] +pub type TX_ABRT_R = crate::BitReader; impl TX_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -304,10 +304,6 @@ impl TX_ABRT_R { *self == TX_ABRT_A::ACTIVE } } -#[doc = "Field `RX_DONE` reader - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. - - Reset value: 0x0"] -pub type RX_DONE_R = crate::BitReader; #[doc = "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0 @@ -326,6 +322,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RX_DONE` reader - When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. + + Reset value: 0x0"] +pub type RX_DONE_R = crate::BitReader; impl RX_DONE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -346,10 +346,6 @@ impl RX_DONE_R { *self == RX_DONE_A::ACTIVE } } -#[doc = "Field `ACTIVITY` reader - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. - - Reset value: 0x0"] -pub type ACTIVITY_R = crate::BitReader; #[doc = "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0 @@ -368,6 +364,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ACTIVITY` reader - This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. + + Reset value: 0x0"] +pub type ACTIVITY_R = crate::BitReader; impl ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -388,10 +388,6 @@ impl ACTIVITY_R { *self == ACTIVITY_A::ACTIVE } } -#[doc = "Field `STOP_DET` reader - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] -pub type STOP_DET_R = crate::BitReader; #[doc = "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 @@ -410,6 +406,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `STOP_DET` reader - Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + In Slave Mode: - If IC_CON\\[7\\]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON\\[7\\]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON\\[10\\]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON\\[10\\]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0"] +pub type STOP_DET_R = crate::BitReader; impl STOP_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -430,10 +430,6 @@ impl STOP_DET_R { *self == STOP_DET_A::ACTIVE } } -#[doc = "Field `START_DET` reader - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. - - Reset value: 0x0"] -pub type START_DET_R = crate::BitReader; #[doc = "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 @@ -452,6 +448,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `START_DET` reader - Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. + + Reset value: 0x0"] +pub type START_DET_R = crate::BitReader; impl START_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -472,10 +472,6 @@ impl START_DET_R { *self == START_DET_A::ACTIVE } } -#[doc = "Field `GEN_CALL` reader - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. - - Reset value: 0x0"] -pub type GEN_CALL_R = crate::BitReader; #[doc = "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0 @@ -494,6 +490,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `GEN_CALL` reader - Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. + + Reset value: 0x0"] +pub type GEN_CALL_R = crate::BitReader; impl GEN_CALL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -514,12 +514,6 @@ impl GEN_CALL_R { *self == GEN_CALL_A::ACTIVE } } -#[doc = "Field `RESTART_DET` reader - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. - - Reset value: 0x0"] -pub type RESTART_DET_R = crate::BitReader; #[doc = "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. @@ -540,6 +534,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RESTART_DET` reader - Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. + + Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. + + Reset value: 0x0"] +pub type RESTART_DET_R = crate::BitReader; impl RESTART_DET_R { #[doc = "Get enumerated values variant"] #[inline(always)] diff --git a/src/i2c0/ic_rx_tl.rs b/src/i2c0/ic_rx_tl.rs index 9ef5367cc..bc573d9c7 100644 --- a/src/i2c0/ic_rx_tl.rs +++ b/src/i2c0/ic_rx_tl.rs @@ -28,16 +28,6 @@ impl W { pub fn rx_tl(&mut self) -> RX_TL_W { RX_TL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Receive FIFO Threshold Register @@ -50,6 +40,7 @@ impl crate::RegisterSpec for IC_RX_TL_SPEC { impl crate::Readable for IC_RX_TL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_rx_tl::W`](W) writer structure"] impl crate::Writable for IC_RX_TL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_sar.rs b/src/i2c0/ic_sar.rs index 8bbb06631..ea3e58ee4 100644 --- a/src/i2c0/ic_sar.rs +++ b/src/i2c0/ic_sar.rs @@ -44,16 +44,6 @@ register being set to 0. Writes at other times have no effect. pub fn ic_sar(&mut self) -> IC_SAR_W { IC_SAR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Slave Address Register @@ -66,6 +56,7 @@ impl crate::RegisterSpec for IC_SAR_SPEC { impl crate::Readable for IC_SAR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_sar::W`](W) writer structure"] impl crate::Writable for IC_SAR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_sda_hold.rs b/src/i2c0/ic_sda_hold.rs index e8bcff55c..60f8bddc2 100644 --- a/src/i2c0/ic_sda_hold.rs +++ b/src/i2c0/ic_sda_hold.rs @@ -51,16 +51,6 @@ impl W { pub fn ic_sda_rx_hold(&mut self) -> IC_SDA_RX_HOLD_W { IC_SDA_RX_HOLD_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C SDA Hold Time Length Register @@ -85,6 +75,7 @@ impl crate::RegisterSpec for IC_SDA_HOLD_SPEC { impl crate::Readable for IC_SDA_HOLD_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_sda_hold::W`](W) writer structure"] impl crate::Writable for IC_SDA_HOLD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_sda_setup.rs b/src/i2c0/ic_sda_setup.rs index 3f2b0d8ad..d6d02c3ba 100644 --- a/src/i2c0/ic_sda_setup.rs +++ b/src/i2c0/ic_sda_setup.rs @@ -20,16 +20,6 @@ impl W { pub fn sda_setup(&mut self) -> SDA_SETUP_W { SDA_SETUP_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C SDA Setup Register @@ -49,6 +39,7 @@ impl crate::RegisterSpec for IC_SDA_SETUP_SPEC { impl crate::Readable for IC_SDA_SETUP_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_sda_setup::W`](W) writer structure"] impl crate::Writable for IC_SDA_SETUP_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_slv_data_nack_only.rs b/src/i2c0/ic_slv_data_nack_only.rs index a577d1a0d..beb7e06bb 100644 --- a/src/i2c0/ic_slv_data_nack_only.rs +++ b/src/i2c0/ic_slv_data_nack_only.rs @@ -2,10 +2,6 @@ pub type R = crate::R; #[doc = "Register `IC_SLV_DATA_NACK_ONLY` writer"] pub type W = crate::W; -#[doc = "Field `NACK` reader - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] -pub type NACK_R = crate::BitReader; #[doc = "Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 @@ -24,6 +20,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `NACK` reader - Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. + + When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0"] +pub type NACK_R = crate::BitReader; impl NACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -81,16 +81,6 @@ impl W { pub fn nack(&mut self) -> NACK_W { NACK_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Generate Slave Data NACK Register @@ -110,6 +100,7 @@ impl crate::RegisterSpec for IC_SLV_DATA_NACK_ONLY_SPEC { impl crate::Readable for IC_SLV_DATA_NACK_ONLY_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_slv_data_nack_only::W`](W) writer structure"] impl crate::Writable for IC_SLV_DATA_NACK_ONLY_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_ss_scl_hcnt.rs b/src/i2c0/ic_ss_scl_hcnt.rs index 381ada07e..f6272e5c5 100644 --- a/src/i2c0/ic_ss_scl_hcnt.rs +++ b/src/i2c0/ic_ss_scl_hcnt.rs @@ -48,16 +48,6 @@ register being set to 0. Writes at other times have no effect. pub fn ic_ss_scl_hcnt(&mut self) -> IC_SS_SCL_HCNT_W { IC_SS_SCL_HCNT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Standard Speed I2C Clock SCL High Count Register @@ -70,6 +60,7 @@ impl crate::RegisterSpec for IC_SS_SCL_HCNT_SPEC { impl crate::Readable for IC_SS_SCL_HCNT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_ss_scl_hcnt::W`](W) writer structure"] impl crate::Writable for IC_SS_SCL_HCNT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_ss_scl_lcnt.rs b/src/i2c0/ic_ss_scl_lcnt.rs index cc0815a1a..99940d30a 100644 --- a/src/i2c0/ic_ss_scl_lcnt.rs +++ b/src/i2c0/ic_ss_scl_lcnt.rs @@ -40,16 +40,6 @@ register being set to 0. Writes at other times have no effect. pub fn ic_ss_scl_lcnt(&mut self) -> IC_SS_SCL_LCNT_W { IC_SS_SCL_LCNT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Standard Speed I2C Clock SCL Low Count Register @@ -62,6 +52,7 @@ impl crate::RegisterSpec for IC_SS_SCL_LCNT_SPEC { impl crate::Readable for IC_SS_SCL_LCNT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_ss_scl_lcnt::W`](W) writer structure"] impl crate::Writable for IC_SS_SCL_LCNT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_status.rs b/src/i2c0/ic_status.rs index 3ce4fcf41..a449a0b2e 100644 --- a/src/i2c0/ic_status.rs +++ b/src/i2c0/ic_status.rs @@ -1,7 +1,5 @@ #[doc = "Register `IC_STATUS` reader"] pub type R = crate::R; -#[doc = "Field `ACTIVITY` reader - I2C Activity Status. Reset value: 0x0"] -pub type ACTIVITY_R = crate::BitReader; #[doc = "I2C Activity Status. Reset value: 0x0 Value on reset: 0"] @@ -18,6 +16,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ACTIVITY` reader - I2C Activity Status. Reset value: 0x0"] +pub type ACTIVITY_R = crate::BitReader; impl ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -38,8 +38,6 @@ impl ACTIVITY_R { *self == ACTIVITY_A::ACTIVE } } -#[doc = "Field `TFNF` reader - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1"] -pub type TFNF_R = crate::BitReader; #[doc = "Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 Value on reset: 1"] @@ -56,6 +54,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TFNF` reader - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1"] +pub type TFNF_R = crate::BitReader; impl TFNF_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -76,8 +76,6 @@ impl TFNF_R { *self == TFNF_A::NOT_FULL } } -#[doc = "Field `TFE` reader - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1"] -pub type TFE_R = crate::BitReader; #[doc = "Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 Value on reset: 1"] @@ -94,6 +92,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `TFE` reader - Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1"] +pub type TFE_R = crate::BitReader; impl TFE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -114,8 +114,6 @@ impl TFE_R { *self == TFE_A::EMPTY } } -#[doc = "Field `RFNE` reader - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0"] -pub type RFNE_R = crate::BitReader; #[doc = "Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 Value on reset: 0"] @@ -132,6 +130,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RFNE` reader - Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0"] +pub type RFNE_R = crate::BitReader; impl RFNE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -152,8 +152,6 @@ impl RFNE_R { *self == RFNE_A::NOT_EMPTY } } -#[doc = "Field `RFF` reader - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0"] -pub type RFF_R = crate::BitReader; #[doc = "Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 Value on reset: 0"] @@ -170,6 +168,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `RFF` reader - Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0"] +pub type RFF_R = crate::BitReader; impl RFF_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -190,10 +190,6 @@ impl RFF_R { *self == RFF_A::FULL } } -#[doc = "Field `MST_ACTIVITY` reader - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. - - Reset value: 0x0"] -pub type MST_ACTIVITY_R = crate::BitReader; #[doc = "Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0 @@ -212,6 +208,10 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `MST_ACTIVITY` reader - Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS\\[0\\]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. + + Reset value: 0x0"] +pub type MST_ACTIVITY_R = crate::BitReader; impl MST_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -232,8 +232,6 @@ impl MST_ACTIVITY_R { *self == MST_ACTIVITY_A::ACTIVE } } -#[doc = "Field `SLV_ACTIVITY` reader - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0"] -pub type SLV_ACTIVITY_R = crate::BitReader; #[doc = "Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 Value on reset: 0"] @@ -250,6 +248,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `SLV_ACTIVITY` reader - Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0"] +pub type SLV_ACTIVITY_R = crate::BitReader; impl SLV_ACTIVITY_R { #[doc = "Get enumerated values variant"] #[inline(always)] diff --git a/src/i2c0/ic_tar.rs b/src/i2c0/ic_tar.rs index c21f80824..4cf0e1e35 100644 --- a/src/i2c0/ic_tar.rs +++ b/src/i2c0/ic_tar.rs @@ -10,8 +10,6 @@ pub type IC_TAR_R = crate::FieldReader; If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave."] pub type IC_TAR_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; -#[doc = "Field `GC_OR_START` reader - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] -pub type GC_OR_START_R = crate::BitReader; #[doc = "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 Value on reset: 0"] @@ -28,6 +26,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `GC_OR_START` reader - If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0"] +pub type GC_OR_START_R = crate::BitReader; impl GC_OR_START_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -65,8 +65,6 @@ where self.variant(GC_OR_START_A::START_BYTE) } } -#[doc = "Field `SPECIAL` reader - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] -pub type SPECIAL_R = crate::BitReader; #[doc = "This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 Value on reset: 0"] @@ -83,6 +81,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `SPECIAL` reader - This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0"] +pub type SPECIAL_R = crate::BitReader; impl SPECIAL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -160,16 +160,6 @@ impl W { pub fn special(&mut self) -> SPECIAL_W { SPECIAL_W::new(self, 11) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Target Address Register @@ -187,6 +177,7 @@ impl crate::RegisterSpec for IC_TAR_SPEC { impl crate::Readable for IC_TAR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_tar::W`](W) writer structure"] impl crate::Writable for IC_TAR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/i2c0/ic_tx_abrt_source.rs b/src/i2c0/ic_tx_abrt_source.rs index f71830e83..7fbde9336 100644 --- a/src/i2c0/ic_tx_abrt_source.rs +++ b/src/i2c0/ic_tx_abrt_source.rs @@ -1,11 +1,5 @@ #[doc = "Register `IC_TX_ABRT_SOURCE` reader"] pub type R = crate::R; -#[doc = "Field `ABRT_7B_ADDR_NOACK` reader - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] -pub type ABRT_7B_ADDR_NOACK_R = crate::BitReader; #[doc = "This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 @@ -26,6 +20,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_7B_ADDR_NOACK` reader - This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_7B_ADDR_NOACK_R = crate::BitReader; impl ABRT_7B_ADDR_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -46,12 +46,6 @@ impl ABRT_7B_ADDR_NOACK_R { *self == ABRT_7B_ADDR_NOACK_A::ACTIVE } } -#[doc = "Field `ABRT_10ADDR1_NOACK` reader - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] -pub type ABRT_10ADDR1_NOACK_R = crate::BitReader; #[doc = "This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 @@ -72,6 +66,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_10ADDR1_NOACK` reader - This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_10ADDR1_NOACK_R = crate::BitReader; impl ABRT_10ADDR1_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -92,12 +92,6 @@ impl ABRT_10ADDR1_NOACK_R { *self == ABRT_10ADDR1_NOACK_A::ACTIVE } } -#[doc = "Field `ABRT_10ADDR2_NOACK` reader - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] -pub type ABRT_10ADDR2_NOACK_R = crate::BitReader; #[doc = "This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 @@ -118,6 +112,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_10ADDR2_NOACK` reader - This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_10ADDR2_NOACK_R = crate::BitReader; impl ABRT_10ADDR2_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -138,12 +138,6 @@ impl ABRT_10ADDR2_NOACK_R { *self == ABRT_10ADDR2_NOACK_A::ACTIVE } } -#[doc = "Field `ABRT_TXDATA_NOACK` reader - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] -pub type ABRT_TXDATA_NOACK_R = crate::BitReader; #[doc = "This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 @@ -164,6 +158,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_TXDATA_NOACK` reader - This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_TXDATA_NOACK_R = crate::BitReader; impl ABRT_TXDATA_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -184,12 +184,6 @@ impl ABRT_TXDATA_NOACK_R { *self == ABRT_TXDATA_NOACK_A::ABRT_TXDATA_NOACK_GENERATED } } -#[doc = "Field `ABRT_GCALL_NOACK` reader - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] -pub type ABRT_GCALL_NOACK_R = crate::BitReader; #[doc = "This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 @@ -210,6 +204,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_GCALL_NOACK` reader - This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_GCALL_NOACK_R = crate::BitReader; impl ABRT_GCALL_NOACK_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -230,13 +230,6 @@ impl ABRT_GCALL_NOACK_R { *self == ABRT_GCALL_NOACK_A::ABRT_GCALL_NOACK_GENERATED } } -#[doc = "Field `ABRT_GCALL_READ` reader - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] -is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] -pub type ABRT_GCALL_READ_R = crate::BitReader; #[doc = "This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] is set to 1). @@ -258,6 +251,13 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_GCALL_READ` reader - This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD\\[9\\] +is set to 1). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_GCALL_READ_R = crate::BitReader; impl ABRT_GCALL_READ_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -278,12 +278,6 @@ impl ABRT_GCALL_READ_R { *self == ABRT_GCALL_READ_A::ABRT_GCALL_READ_GENERATED } } -#[doc = "Field `ABRT_HS_ACKDET` reader - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] -pub type ABRT_HS_ACKDET_R = crate::BitReader; #[doc = "This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 @@ -304,6 +298,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_HS_ACKDET` reader - This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master"] +pub type ABRT_HS_ACKDET_R = crate::BitReader; impl ABRT_HS_ACKDET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -324,12 +324,6 @@ impl ABRT_HS_ACKDET_R { *self == ABRT_HS_ACKDET_A::ABRT_HS_ACK_GENERATED } } -#[doc = "Field `ABRT_SBYTE_ACKDET` reader - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] -pub type ABRT_SBYTE_ACKDET_R = crate::BitReader; #[doc = "This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 @@ -350,6 +344,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_SBYTE_ACKDET` reader - This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). + + Reset value: 0x0 + + Role of DW_apb_i2c: Master"] +pub type ABRT_SBYTE_ACKDET_R = crate::BitReader; impl ABRT_SBYTE_ACKDET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -370,12 +370,6 @@ impl ABRT_SBYTE_ACKDET_R { *self == ABRT_SBYTE_ACKDET_A::ABRT_SBYTE_ACKDET_GENERATED } } -#[doc = "Field `ABRT_HS_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] -pub type ABRT_HS_NORSTRT_R = crate::BitReader; #[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 @@ -396,6 +390,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_HS_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to use the master to transfer data in High Speed mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_HS_NORSTRT_R = crate::BitReader; impl ABRT_HS_NORSTRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -416,12 +416,6 @@ impl ABRT_HS_NORSTRT_R { *self == ABRT_HS_NORSTRT_A::ABRT_HS_NORSTRT_GENERATED } } -#[doc = "Field `ABRT_SBYTE_NORSTRT` reader - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master"] -pub type ABRT_SBYTE_NORSTRT_R = crate::BitReader; #[doc = "To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. Reset value: 0x0 @@ -442,6 +436,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_SBYTE_NORSTRT` reader - To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON\\[5\\]=1), the SPECIAL bit must be cleared (IC_TAR\\[11\\]), or the GC_OR_START bit must be cleared (IC_TAR\\[10\\]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the user is trying to send a START Byte. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master"] +pub type ABRT_SBYTE_NORSTRT_R = crate::BitReader; impl ABRT_SBYTE_NORSTRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -462,12 +462,6 @@ impl ABRT_SBYTE_NORSTRT_R { *self == ABRT_SBYTE_NORSTRT_A::ABRT_SBYTE_NORSTRT_GENERATED } } -#[doc = "Field `ABRT_10B_RD_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver"] -pub type ABRT_10B_RD_NORSTRT_R = crate::BitReader; #[doc = "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 @@ -488,6 +482,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_10B_RD_NORSTRT` reader - This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON\\[5\\]) =0) and the master sends a read command in 10-bit addressing mode. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Receiver"] +pub type ABRT_10B_RD_NORSTRT_R = crate::BitReader; impl ABRT_10B_RD_NORSTRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -508,12 +508,6 @@ impl ABRT_10B_RD_NORSTRT_R { *self == ABRT_10B_RD_NORSTRT_A::ABRT_10B_RD_GENERATED } } -#[doc = "Field `ABRT_MASTER_DIS` reader - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] -pub type ABRT_MASTER_DIS_R = crate::BitReader; #[doc = "This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 @@ -534,6 +528,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_MASTER_DIS` reader - This field indicates that the User tries to initiate a Master operation with the Master mode disabled. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Master-Receiver"] +pub type ABRT_MASTER_DIS_R = crate::BitReader; impl ABRT_MASTER_DIS_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -554,13 +554,6 @@ impl ABRT_MASTER_DIS_R { *self == ABRT_MASTER_DIS_A::ABRT_MASTER_DIS_GENERATED } } -#[doc = "Field `ARB_LOST` reader - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] -is also set, then the slave transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] -pub type ARB_LOST_R = crate::BitReader; #[doc = "This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] is also set, then the slave transmitter has lost arbitration. @@ -582,6 +575,13 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ARB_LOST` reader - This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE\\[14\\] +is also set, then the slave transmitter has lost arbitration. + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter"] +pub type ARB_LOST_R = crate::BitReader; impl ARB_LOST_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -602,12 +602,6 @@ impl ARB_LOST_R { *self == ARB_LOST_A::ABRT_LOST_GENERATED } } -#[doc = "Field `ABRT_SLVFLUSH_TXFIFO` reader - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] -pub type ABRT_SLVFLUSH_TXFIFO_R = crate::BitReader; #[doc = "This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 @@ -628,6 +622,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_SLVFLUSH_TXFIFO` reader - This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter"] +pub type ABRT_SLVFLUSH_TXFIFO_R = crate::BitReader; impl ABRT_SLVFLUSH_TXFIFO_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -648,13 +648,6 @@ impl ABRT_SLVFLUSH_TXFIFO_R { *self == ABRT_SLVFLUSH_TXFIFO_A::ABRT_SLVFLUSH_TXFIFO_GENERATED } } -#[doc = "Field `ABRT_SLV_ARBLOST` reader - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] -is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] -pub type ABRT_SLV_ARBLOST_R = crate::BitReader; #[doc = "This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. @@ -676,6 +669,13 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_SLV_ARBLOST` reader - This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE\\[12\\] +is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter"] +pub type ABRT_SLV_ARBLOST_R = crate::BitReader; impl ABRT_SLV_ARBLOST_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -696,12 +696,6 @@ impl ABRT_SLV_ARBLOST_R { *self == ABRT_SLV_ARBLOST_A::ABRT_SLV_ARBLOST_GENERATED } } -#[doc = "Field `ABRT_SLVRD_INTX` reader - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter"] -pub type ABRT_SLVRD_INTX_R = crate::BitReader; #[doc = "1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 @@ -722,6 +716,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_SLVRD_INTX` reader - 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. + + Reset value: 0x0 + + Role of DW_apb_i2c: Slave-Transmitter"] +pub type ABRT_SLVRD_INTX_R = crate::BitReader; impl ABRT_SLVRD_INTX_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -742,12 +742,6 @@ impl ABRT_SLVRD_INTX_R { *self == ABRT_SLVRD_INTX_A::ABRT_SLVRD_INTX_GENERATED } } -#[doc = "Field `ABRT_USER_ABRT` reader - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter"] -pub type ABRT_USER_ABRT_R = crate::BitReader; #[doc = "This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) Reset value: 0x0 @@ -768,6 +762,12 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `ABRT_USER_ABRT` reader - This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE\\[1\\]) + + Reset value: 0x0 + + Role of DW_apb_i2c: Master-Transmitter"] +pub type ABRT_USER_ABRT_R = crate::BitReader; impl ABRT_USER_ABRT_R { #[doc = "Get enumerated values variant"] #[inline(always)] diff --git a/src/i2c0/ic_tx_tl.rs b/src/i2c0/ic_tx_tl.rs index 8d39a1a3c..32fa42d7e 100644 --- a/src/i2c0/ic_tx_tl.rs +++ b/src/i2c0/ic_tx_tl.rs @@ -28,16 +28,6 @@ impl W { pub fn tx_tl(&mut self) -> TX_TL_W { TX_TL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "I2C Transmit FIFO Threshold Register @@ -50,6 +40,7 @@ impl crate::RegisterSpec for IC_TX_TL_SPEC { impl crate::Readable for IC_TX_TL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ic_tx_tl::W`](W) writer structure"] impl crate::Writable for IC_TX_TL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_bank0.rs b/src/io_bank0.rs index 6cc1dacc2..728289fcf 100644 --- a/src/io_bank0.rs +++ b/src/io_bank0.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { gpio: [GPIO; 30], intr: [INTR; 4], diff --git a/src/io_bank0/dormant_wake_inte.rs b/src/io_bank0/dormant_wake_inte.rs index c420dcd08..2375a5ef8 100644 --- a/src/io_bank0/dormant_wake_inte.rs +++ b/src/io_bank0/dormant_wake_inte.rs @@ -485,16 +485,6 @@ impl W { pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable for dormant_wake @@ -507,6 +497,7 @@ impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC { impl crate::Readable for DORMANT_WAKE_INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`dormant_wake_inte::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_bank0/dormant_wake_intf.rs b/src/io_bank0/dormant_wake_intf.rs index d1f1b8c8d..9099fcaa9 100644 --- a/src/io_bank0/dormant_wake_intf.rs +++ b/src/io_bank0/dormant_wake_intf.rs @@ -485,16 +485,6 @@ impl W { pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force for dormant_wake @@ -507,6 +497,7 @@ impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC { impl crate::Readable for DORMANT_WAKE_INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`dormant_wake_intf::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_bank0/gpio.rs b/src/io_bank0/gpio.rs index 1f1024da5..77023bc7d 100644 --- a/src/io_bank0/gpio.rs +++ b/src/io_bank0/gpio.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL"] pub struct GPIO { gpio_status: GPIO_STATUS, gpio_ctrl: GPIO_CTRL, diff --git a/src/io_bank0/gpio/gpio_ctrl.rs b/src/io_bank0/gpio/gpio_ctrl.rs index 9714e9e4f..f0b9aee22 100644 --- a/src/io_bank0/gpio/gpio_ctrl.rs +++ b/src/io_bank0/gpio/gpio_ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `GPIO_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] -pub type FUNCSEL_R = crate::FieldReader; #[doc = "0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. Value on reset: 31"] @@ -42,6 +40,8 @@ impl From for u8 { impl crate::FieldSpec for FUNCSEL_A { type Ux = u8; } +#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins."] +pub type FUNCSEL_R = crate::FieldReader; impl FUNCSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -180,8 +180,6 @@ where self.variant(FUNCSEL_A::NULL) } } -#[doc = "Field `OUTOVER` reader - "] -pub type OUTOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -206,6 +204,8 @@ impl From for u8 { impl crate::FieldSpec for OUTOVER_A { type Ux = u8; } +#[doc = "Field `OUTOVER` reader - "] +pub type OUTOVER_R = crate::FieldReader; impl OUTOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -267,8 +267,6 @@ where self.variant(OUTOVER_A::HIGH) } } -#[doc = "Field `OEOVER` reader - "] -pub type OEOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -293,6 +291,8 @@ impl From for u8 { impl crate::FieldSpec for OEOVER_A { type Ux = u8; } +#[doc = "Field `OEOVER` reader - "] +pub type OEOVER_R = crate::FieldReader; impl OEOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -354,8 +354,6 @@ where self.variant(OEOVER_A::ENABLE) } } -#[doc = "Field `INOVER` reader - "] -pub type INOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -380,6 +378,8 @@ impl From for u8 { impl crate::FieldSpec for INOVER_A { type Ux = u8; } +#[doc = "Field `INOVER` reader - "] +pub type INOVER_R = crate::FieldReader; impl INOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -441,8 +441,6 @@ where self.variant(INOVER_A::HIGH) } } -#[doc = "Field `IRQOVER` reader - "] -pub type IRQOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -467,6 +465,8 @@ impl From for u8 { impl crate::FieldSpec for IRQOVER_A { type Ux = u8; } +#[doc = "Field `IRQOVER` reader - "] +pub type IRQOVER_R = crate::FieldReader; impl IRQOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -586,16 +586,6 @@ impl W { pub fn irqover(&mut self) -> IRQOVER_W { IRQOVER_W::new(self, 28) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO control including function select and overrides. @@ -608,6 +598,7 @@ impl crate::RegisterSpec for GPIO_CTRL_SPEC { impl crate::Readable for GPIO_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_ctrl::W`](W) writer structure"] impl crate::Writable for GPIO_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_bank0/intr.rs b/src/io_bank0/intr.rs index 5527ca094..4cae9a89f 100644 --- a/src/io_bank0/intr.rs +++ b/src/io_bank0/intr.rs @@ -357,16 +357,6 @@ impl W { pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Raw Interrupts @@ -379,6 +369,7 @@ impl crate::RegisterSpec for INTR_SPEC { impl crate::Readable for INTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xcccc_cccc; } diff --git a/src/io_bank0/proc0_inte.rs b/src/io_bank0/proc0_inte.rs index a74d9019d..931d527da 100644 --- a/src/io_bank0/proc0_inte.rs +++ b/src/io_bank0/proc0_inte.rs @@ -485,16 +485,6 @@ impl W { pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable for proc0 @@ -507,6 +497,7 @@ impl crate::RegisterSpec for PROC0_INTE_SPEC { impl crate::Readable for PROC0_INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc0_inte::W`](W) writer structure"] impl crate::Writable for PROC0_INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_bank0/proc0_intf.rs b/src/io_bank0/proc0_intf.rs index 045f38686..a676b4300 100644 --- a/src/io_bank0/proc0_intf.rs +++ b/src/io_bank0/proc0_intf.rs @@ -485,16 +485,6 @@ impl W { pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force for proc0 @@ -507,6 +497,7 @@ impl crate::RegisterSpec for PROC0_INTF_SPEC { impl crate::Readable for PROC0_INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc0_intf::W`](W) writer structure"] impl crate::Writable for PROC0_INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_bank0/proc1_inte.rs b/src/io_bank0/proc1_inte.rs index 51a230847..d92cb269f 100644 --- a/src/io_bank0/proc1_inte.rs +++ b/src/io_bank0/proc1_inte.rs @@ -485,16 +485,6 @@ impl W { pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable for proc1 @@ -507,6 +497,7 @@ impl crate::RegisterSpec for PROC1_INTE_SPEC { impl crate::Readable for PROC1_INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc1_inte::W`](W) writer structure"] impl crate::Writable for PROC1_INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_bank0/proc1_intf.rs b/src/io_bank0/proc1_intf.rs index 3aa1dec9d..9085b9c12 100644 --- a/src/io_bank0/proc1_intf.rs +++ b/src/io_bank0/proc1_intf.rs @@ -485,16 +485,6 @@ impl W { pub fn gpio7_edge_high(&mut self) -> GPIO7_EDGE_HIGH_W { GPIO7_EDGE_HIGH_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force for proc1 @@ -507,6 +497,7 @@ impl crate::RegisterSpec for PROC1_INTF_SPEC { impl crate::Readable for PROC1_INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc1_intf::W`](W) writer structure"] impl crate::Writable for PROC1_INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_qspi.rs b/src/io_qspi.rs index a96bd1005..aeaf4ad26 100644 --- a/src/io_qspi.rs +++ b/src/io_qspi.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { gpio_qspi: [GPIO_QSPI; 6], intr: INTR, diff --git a/src/io_qspi/dormant_wake_inte.rs b/src/io_qspi/dormant_wake_inte.rs index 5dd33a2ac..491c009cb 100644 --- a/src/io_qspi/dormant_wake_inte.rs +++ b/src/io_qspi/dormant_wake_inte.rs @@ -379,16 +379,6 @@ impl W { pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable for dormant_wake @@ -401,6 +391,7 @@ impl crate::RegisterSpec for DORMANT_WAKE_INTE_SPEC { impl crate::Readable for DORMANT_WAKE_INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`dormant_wake_inte::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_qspi/dormant_wake_intf.rs b/src/io_qspi/dormant_wake_intf.rs index 98da69ef8..91e15fc0e 100644 --- a/src/io_qspi/dormant_wake_intf.rs +++ b/src/io_qspi/dormant_wake_intf.rs @@ -379,16 +379,6 @@ impl W { pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force for dormant_wake @@ -401,6 +391,7 @@ impl crate::RegisterSpec for DORMANT_WAKE_INTF_SPEC { impl crate::Readable for DORMANT_WAKE_INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`dormant_wake_intf::W`](W) writer structure"] impl crate::Writable for DORMANT_WAKE_INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_qspi/gpio_qspi.rs b/src/io_qspi/gpio_qspi.rs index 2c839319d..8b60a9ad1 100644 --- a/src/io_qspi/gpio_qspi.rs +++ b/src/io_qspi/gpio_qspi.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL"] pub struct GPIO_QSPI { gpio_status: GPIO_STATUS, gpio_ctrl: GPIO_CTRL, diff --git a/src/io_qspi/gpio_qspi/gpio_ctrl.rs b/src/io_qspi/gpio_qspi/gpio_ctrl.rs index 440d23829..c91a7f94c 100644 --- a/src/io_qspi/gpio_qspi/gpio_ctrl.rs +++ b/src/io_qspi/gpio_qspi/gpio_ctrl.rs @@ -2,9 +2,6 @@ pub type R = crate::R; #[doc = "Register `GPIO_CTRL` writer"] pub type W = crate::W; -#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table - 31 == NULL"] -pub type FUNCSEL_R = crate::FieldReader; #[doc = "0-31 -> selects pin function according to the gpio table 31 == NULL @@ -28,6 +25,9 @@ impl From for u8 { impl crate::FieldSpec for FUNCSEL_A { type Ux = u8; } +#[doc = "Field `FUNCSEL` reader - 0-31 -> selects pin function according to the gpio table + 31 == NULL"] +pub type FUNCSEL_R = crate::FieldReader; impl FUNCSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -79,8 +79,6 @@ where self.variant(FUNCSEL_A::NULL) } } -#[doc = "Field `OUTOVER` reader - "] -pub type OUTOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -105,6 +103,8 @@ impl From for u8 { impl crate::FieldSpec for OUTOVER_A { type Ux = u8; } +#[doc = "Field `OUTOVER` reader - "] +pub type OUTOVER_R = crate::FieldReader; impl OUTOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -166,8 +166,6 @@ where self.variant(OUTOVER_A::HIGH) } } -#[doc = "Field `OEOVER` reader - "] -pub type OEOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -192,6 +190,8 @@ impl From for u8 { impl crate::FieldSpec for OEOVER_A { type Ux = u8; } +#[doc = "Field `OEOVER` reader - "] +pub type OEOVER_R = crate::FieldReader; impl OEOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -253,8 +253,6 @@ where self.variant(OEOVER_A::ENABLE) } } -#[doc = "Field `INOVER` reader - "] -pub type INOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -279,6 +277,8 @@ impl From for u8 { impl crate::FieldSpec for INOVER_A { type Ux = u8; } +#[doc = "Field `INOVER` reader - "] +pub type INOVER_R = crate::FieldReader; impl INOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -340,8 +340,6 @@ where self.variant(INOVER_A::HIGH) } } -#[doc = "Field `IRQOVER` reader - "] -pub type IRQOVER_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -366,6 +364,8 @@ impl From for u8 { impl crate::FieldSpec for IRQOVER_A { type Ux = u8; } +#[doc = "Field `IRQOVER` reader - "] +pub type IRQOVER_R = crate::FieldReader; impl IRQOVER_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -487,16 +487,6 @@ impl W { pub fn irqover(&mut self) -> IRQOVER_W { IRQOVER_W::new(self, 28) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO control including function select and overrides. @@ -509,6 +499,7 @@ impl crate::RegisterSpec for GPIO_CTRL_SPEC { impl crate::Readable for GPIO_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_ctrl::W`](W) writer structure"] impl crate::Writable for GPIO_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_qspi/intr.rs b/src/io_qspi/intr.rs index 00e27b039..9329d4c32 100644 --- a/src/io_qspi/intr.rs +++ b/src/io_qspi/intr.rs @@ -269,16 +269,6 @@ impl W { pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Raw Interrupts @@ -291,6 +281,7 @@ impl crate::RegisterSpec for INTR_SPEC { impl crate::Readable for INTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00cc_cccc; } diff --git a/src/io_qspi/proc0_inte.rs b/src/io_qspi/proc0_inte.rs index cecc63018..8d194d6c0 100644 --- a/src/io_qspi/proc0_inte.rs +++ b/src/io_qspi/proc0_inte.rs @@ -365,16 +365,6 @@ impl W { pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable for proc0 @@ -387,6 +377,7 @@ impl crate::RegisterSpec for PROC0_INTE_SPEC { impl crate::Readable for PROC0_INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc0_inte::W`](W) writer structure"] impl crate::Writable for PROC0_INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_qspi/proc0_intf.rs b/src/io_qspi/proc0_intf.rs index 74ce8df2f..7c3d6b1a4 100644 --- a/src/io_qspi/proc0_intf.rs +++ b/src/io_qspi/proc0_intf.rs @@ -365,16 +365,6 @@ impl W { pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force for proc0 @@ -387,6 +377,7 @@ impl crate::RegisterSpec for PROC0_INTF_SPEC { impl crate::Readable for PROC0_INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc0_intf::W`](W) writer structure"] impl crate::Writable for PROC0_INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_qspi/proc1_inte.rs b/src/io_qspi/proc1_inte.rs index 8fa5f8c6f..923279580 100644 --- a/src/io_qspi/proc1_inte.rs +++ b/src/io_qspi/proc1_inte.rs @@ -365,16 +365,6 @@ impl W { pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable for proc1 @@ -387,6 +377,7 @@ impl crate::RegisterSpec for PROC1_INTE_SPEC { impl crate::Readable for PROC1_INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc1_inte::W`](W) writer structure"] impl crate::Writable for PROC1_INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/io_qspi/proc1_intf.rs b/src/io_qspi/proc1_intf.rs index 46ce34255..a845d3315 100644 --- a/src/io_qspi/proc1_intf.rs +++ b/src/io_qspi/proc1_intf.rs @@ -365,16 +365,6 @@ impl W { pub fn gpio_qspi_sd3_edge_high(&mut self) -> GPIO_QSPI_SD3_EDGE_HIGH_W { GPIO_QSPI_SD3_EDGE_HIGH_W::new(self, 23) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force for proc1 @@ -387,6 +377,7 @@ impl crate::RegisterSpec for PROC1_INTF_SPEC { impl crate::Readable for PROC1_INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc1_intf::W`](W) writer structure"] impl crate::Writable for PROC1_INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/lib.rs b/src/lib.rs index 2fe3f28ca..094585a0a 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,11 +1,11 @@ -#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.31.5 ( )) +#![doc = "Peripheral access API for RP2040 microcontrollers (generated using svd2rust v0.32.0 ( )) You can find an overview of the generated API [here]. API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`. -[here]: https://docs.rs/svd2rust/0.31.5/svd2rust/#peripheral-api +[here]: https://docs.rs/svd2rust/0.32.0/svd2rust/#peripheral-api [next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased [repository]: https://github.com/rust-embedded/svd2rust"] #![allow(non_camel_case_types)] diff --git a/src/pads_bank0.rs b/src/pads_bank0.rs index 136ed46e8..fdbed2a54 100644 --- a/src/pads_bank0.rs +++ b/src/pads_bank0.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { voltage_select: VOLTAGE_SELECT, gpio: [GPIO; 30], diff --git a/src/pads_bank0/gpio.rs b/src/pads_bank0/gpio.rs index eabdcc71c..98bfa5b24 100644 --- a/src/pads_bank0/gpio.rs +++ b/src/pads_bank0/gpio.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for GPIO_SPEC { impl crate::Readable for GPIO_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio::W`](W) writer structure"] impl crate::Writable for GPIO_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_bank0/swclk.rs b/src/pads_bank0/swclk.rs index 4c7a60cbe..7b909ce86 100644 --- a/src/pads_bank0/swclk.rs +++ b/src/pads_bank0/swclk.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for SWCLK_SPEC { impl crate::Readable for SWCLK_SPEC {} #[doc = "`write(|w| ..)` method takes [`swclk::W`](W) writer structure"] impl crate::Writable for SWCLK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_bank0/swd.rs b/src/pads_bank0/swd.rs index a96bda399..4df05995e 100644 --- a/src/pads_bank0/swd.rs +++ b/src/pads_bank0/swd.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for SWD_SPEC { impl crate::Readable for SWD_SPEC {} #[doc = "`write(|w| ..)` method takes [`swd::W`](W) writer structure"] impl crate::Writable for SWD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_bank0/voltage_select.rs b/src/pads_bank0/voltage_select.rs index 8b30209d3..e1ca5ea9a 100644 --- a/src/pads_bank0/voltage_select.rs +++ b/src/pads_bank0/voltage_select.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `VOLTAGE_SELECT` writer"] pub type W = crate::W; -#[doc = "Field `VOLTAGE_SELECT` reader - "] -pub type VOLTAGE_SELECT_R = crate::BitReader; #[doc = " Value on reset: 0"] @@ -20,6 +18,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `VOLTAGE_SELECT` reader - "] +pub type VOLTAGE_SELECT_R = crate::BitReader; impl VOLTAGE_SELECT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -71,16 +71,6 @@ impl W { pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W { VOLTAGE_SELECT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Voltage select. Per bank control @@ -93,6 +83,7 @@ impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC { impl crate::Readable for VOLTAGE_SELECT_SPEC {} #[doc = "`write(|w| ..)` method takes [`voltage_select::W`](W) writer structure"] impl crate::Writable for VOLTAGE_SELECT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_qspi.rs b/src/pads_qspi.rs index 22d8703d7..27cf3bde9 100644 --- a/src/pads_qspi.rs +++ b/src/pads_qspi.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { voltage_select: VOLTAGE_SELECT, gpio_qspi_sclk: GPIO_QSPI_SCLK, diff --git a/src/pads_qspi/gpio_qspi_sclk.rs b/src/pads_qspi/gpio_qspi_sclk.rs index fe2e8d70d..96d9229fc 100644 --- a/src/pads_qspi/gpio_qspi_sclk.rs +++ b/src/pads_qspi/gpio_qspi_sclk.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for GPIO_QSPI_SCLK_SPEC { impl crate::Readable for GPIO_QSPI_SCLK_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_qspi_sclk::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SCLK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd0.rs b/src/pads_qspi/gpio_qspi_sd0.rs index a45379c2d..cd34d33d7 100644 --- a/src/pads_qspi/gpio_qspi_sd0.rs +++ b/src/pads_qspi/gpio_qspi_sd0.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for GPIO_QSPI_SD0_SPEC { impl crate::Readable for GPIO_QSPI_SD0_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd0::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd1.rs b/src/pads_qspi/gpio_qspi_sd1.rs index 2fbfbae82..073b9f561 100644 --- a/src/pads_qspi/gpio_qspi_sd1.rs +++ b/src/pads_qspi/gpio_qspi_sd1.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for GPIO_QSPI_SD1_SPEC { impl crate::Readable for GPIO_QSPI_SD1_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd1::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd2.rs b/src/pads_qspi/gpio_qspi_sd2.rs index 485583a9f..738b7ef2b 100644 --- a/src/pads_qspi/gpio_qspi_sd2.rs +++ b/src/pads_qspi/gpio_qspi_sd2.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for GPIO_QSPI_SD2_SPEC { impl crate::Readable for GPIO_QSPI_SD2_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd2::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_qspi/gpio_qspi_sd3.rs b/src/pads_qspi/gpio_qspi_sd3.rs index d76da8bd3..da18ad2c0 100644 --- a/src/pads_qspi/gpio_qspi_sd3.rs +++ b/src/pads_qspi/gpio_qspi_sd3.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for GPIO_QSPI_SD3_SPEC { impl crate::Readable for GPIO_QSPI_SD3_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_qspi_sd3::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SD3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_qspi/gpio_qspi_ss.rs b/src/pads_qspi/gpio_qspi_ss.rs index 3204bc1c0..de88f61b0 100644 --- a/src/pads_qspi/gpio_qspi_ss.rs +++ b/src/pads_qspi/gpio_qspi_ss.rs @@ -18,8 +18,6 @@ pub type PDE_W<'a, REG> = crate::BitWriter<'a, REG>; pub type PUE_R = crate::BitReader; #[doc = "Field `PUE` writer - Pull up enable"] pub type PUE_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DRIVE` reader - Drive strength."] -pub type DRIVE_R = crate::FieldReader; #[doc = "Drive strength. Value on reset: 1"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DRIVE_A { type Ux = u8; } +#[doc = "Field `DRIVE` reader - Drive strength."] +pub type DRIVE_R = crate::FieldReader; impl DRIVE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -193,16 +193,6 @@ impl W { pub fn od(&mut self) -> OD_W { OD_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Pad control register @@ -215,6 +205,7 @@ impl crate::RegisterSpec for GPIO_QSPI_SS_SPEC { impl crate::Readable for GPIO_QSPI_SS_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_qspi_ss::W`](W) writer structure"] impl crate::Writable for GPIO_QSPI_SS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pads_qspi/voltage_select.rs b/src/pads_qspi/voltage_select.rs index 8b30209d3..e1ca5ea9a 100644 --- a/src/pads_qspi/voltage_select.rs +++ b/src/pads_qspi/voltage_select.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `VOLTAGE_SELECT` writer"] pub type W = crate::W; -#[doc = "Field `VOLTAGE_SELECT` reader - "] -pub type VOLTAGE_SELECT_R = crate::BitReader; #[doc = " Value on reset: 0"] @@ -20,6 +18,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `VOLTAGE_SELECT` reader - "] +pub type VOLTAGE_SELECT_R = crate::BitReader; impl VOLTAGE_SELECT_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -71,16 +71,6 @@ impl W { pub fn voltage_select(&mut self) -> VOLTAGE_SELECT_W { VOLTAGE_SELECT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Voltage select. Per bank control @@ -93,6 +83,7 @@ impl crate::RegisterSpec for VOLTAGE_SELECT_SPEC { impl crate::Readable for VOLTAGE_SELECT_SPEC {} #[doc = "`write(|w| ..)` method takes [`voltage_select::W`](W) writer structure"] impl crate::Writable for VOLTAGE_SELECT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0.rs b/src/pio0.rs index 1ac7d1d83..d13478492 100644 --- a/src/pio0.rs +++ b/src/pio0.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ctrl: CTRL, fstat: FSTAT, diff --git a/src/pio0/ctrl.rs b/src/pio0/ctrl.rs index 400969125..a3638640d 100644 --- a/src/pio0/ctrl.rs +++ b/src/pio0/ctrl.rs @@ -82,16 +82,6 @@ impl W { pub fn clkdiv_restart(&mut self) -> CLKDIV_RESTART_W { CLKDIV_RESTART_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "PIO control register @@ -104,6 +94,7 @@ impl crate::RegisterSpec for CTRL_SPEC { impl crate::Readable for CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/fdebug.rs b/src/pio0/fdebug.rs index 3c07bfb47..fd533d10f 100644 --- a/src/pio0/fdebug.rs +++ b/src/pio0/fdebug.rs @@ -65,16 +65,6 @@ impl W { pub fn txstall(&mut self) -> TXSTALL_W { TXSTALL_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "FIFO debug register @@ -87,6 +77,7 @@ impl crate::RegisterSpec for FDEBUG_SPEC { impl crate::Readable for FDEBUG_SPEC {} #[doc = "`write(|w| ..)` method takes [`fdebug::W`](W) writer structure"] impl crate::Writable for FDEBUG_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f0f_0f0f; } diff --git a/src/pio0/input_sync_bypass.rs b/src/pio0/input_sync_bypass.rs index 85792cc1c..0b355db58 100644 --- a/src/pio0/input_sync_bypass.rs +++ b/src/pio0/input_sync_bypass.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed @@ -38,6 +27,7 @@ impl crate::RegisterSpec for INPUT_SYNC_BYPASS_SPEC { impl crate::Readable for INPUT_SYNC_BYPASS_SPEC {} #[doc = "`write(|w| ..)` method takes [`input_sync_bypass::W`](W) writer structure"] impl crate::Writable for INPUT_SYNC_BYPASS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/instr_mem.rs b/src/pio0/instr_mem.rs index 9ff617ba9..1b69c4ef9 100644 --- a/src/pio0/instr_mem.rs +++ b/src/pio0/instr_mem.rs @@ -9,16 +9,6 @@ impl W { pub fn instr_mem0(&mut self) -> INSTR_MEM0_W { INSTR_MEM0_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Write-only access to instruction memory location %s @@ -29,6 +19,7 @@ impl crate::RegisterSpec for INSTR_MEM_SPEC { } #[doc = "`write(|w| ..)` method takes [`instr_mem::W`](W) writer structure"] impl crate::Writable for INSTR_MEM_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/irq.rs b/src/pio0/irq.rs index ee808dd41..587f8f05e 100644 --- a/src/pio0/irq.rs +++ b/src/pio0/irq.rs @@ -20,16 +20,6 @@ impl W { pub fn irq(&mut self) -> IRQ_W { IRQ_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. @@ -44,6 +34,7 @@ impl crate::RegisterSpec for IRQ_SPEC { impl crate::Readable for IRQ_SPEC {} #[doc = "`write(|w| ..)` method takes [`irq::W`](W) writer structure"] impl crate::Writable for IRQ_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; } diff --git a/src/pio0/irq_force.rs b/src/pio0/irq_force.rs index 392ec0979..46e8b95fd 100644 --- a/src/pio0/irq_force.rs +++ b/src/pio0/irq_force.rs @@ -9,16 +9,6 @@ impl W { pub fn irq_force(&mut self) -> IRQ_FORCE_W { IRQ_FORCE_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. @@ -29,6 +19,7 @@ impl crate::RegisterSpec for IRQ_FORCE_SPEC { } #[doc = "`write(|w| ..)` method takes [`irq_force::W`](W) writer structure"] impl crate::Writable for IRQ_FORCE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/sm.rs b/src/pio0/sm.rs index e3559b8d4..05686cd36 100644 --- a/src/pio0/sm.rs +++ b/src/pio0/sm.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL"] pub struct SM { sm_clkdiv: SM_CLKDIV, sm_execctrl: SM_EXECCTRL, diff --git a/src/pio0/sm/sm_clkdiv.rs b/src/pio0/sm/sm_clkdiv.rs index 283e68b59..e65fbf594 100644 --- a/src/pio0/sm/sm_clkdiv.rs +++ b/src/pio0/sm/sm_clkdiv.rs @@ -39,16 +39,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) @@ -62,6 +52,7 @@ impl crate::RegisterSpec for SM_CLKDIV_SPEC { impl crate::Readable for SM_CLKDIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`sm_clkdiv::W`](W) writer structure"] impl crate::Writable for SM_CLKDIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/sm/sm_execctrl.rs b/src/pio0/sm/sm_execctrl.rs index a207589d5..419ecc091 100644 --- a/src/pio0/sm/sm_execctrl.rs +++ b/src/pio0/sm/sm_execctrl.rs @@ -6,8 +6,6 @@ pub type W = crate::W; pub type STATUS_N_R = crate::FieldReader; #[doc = "Field `STATUS_N` writer - Comparison level for the MOV x, STATUS instruction"] pub type STATUS_N_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `STATUS_SEL` reader - Comparison used for the MOV x, STATUS instruction."] -pub type STATUS_SEL_R = crate::BitReader; #[doc = "Comparison used for the MOV x, STATUS instruction. Value on reset: 0"] @@ -24,6 +22,8 @@ impl From for bool { variant as u8 != 0 } } +#[doc = "Field `STATUS_SEL` reader - Comparison used for the MOV x, STATUS instruction."] +pub type STATUS_SEL_R = crate::BitReader; impl STATUS_SEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -229,16 +229,6 @@ impl W { pub fn side_en(&mut self) -> SIDE_EN_W { SIDE_EN_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Execution/behavioural settings for state machine 0 @@ -251,6 +241,7 @@ impl crate::RegisterSpec for SM_EXECCTRL_SPEC { impl crate::Readable for SM_EXECCTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`sm_execctrl::W`](W) writer structure"] impl crate::Writable for SM_EXECCTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/sm/sm_instr.rs b/src/pio0/sm/sm_instr.rs index 51df7566b..795552995 100644 --- a/src/pio0/sm/sm_instr.rs +++ b/src/pio0/sm/sm_instr.rs @@ -20,16 +20,6 @@ impl W { pub fn sm0_instr(&mut self) -> SM0_INSTR_W { SM0_INSTR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. @@ -43,6 +33,7 @@ impl crate::RegisterSpec for SM_INSTR_SPEC { impl crate::Readable for SM_INSTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`sm_instr::W`](W) writer structure"] impl crate::Writable for SM_INSTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/sm/sm_pinctrl.rs b/src/pio0/sm/sm_pinctrl.rs index fb59426a7..29072b12d 100644 --- a/src/pio0/sm/sm_pinctrl.rs +++ b/src/pio0/sm/sm_pinctrl.rs @@ -110,16 +110,6 @@ impl W { pub fn sideset_count(&mut self) -> SIDESET_COUNT_W { SIDESET_COUNT_W::new(self, 29) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "State machine pin control @@ -132,6 +122,7 @@ impl crate::RegisterSpec for SM_PINCTRL_SPEC { impl crate::Readable for SM_PINCTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`sm_pinctrl::W`](W) writer structure"] impl crate::Writable for SM_PINCTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/sm/sm_shiftctrl.rs b/src/pio0/sm/sm_shiftctrl.rs index bba59114a..bcb7872b2 100644 --- a/src/pio0/sm/sm_shiftctrl.rs +++ b/src/pio0/sm/sm_shiftctrl.rs @@ -149,16 +149,6 @@ impl W { pub fn fjoin_rx(&mut self) -> FJOIN_RX_W { FJOIN_RX_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control behaviour of the input/output shift registers for state machine 0 @@ -171,6 +161,7 @@ impl crate::RegisterSpec for SM_SHIFTCTRL_SPEC { impl crate::Readable for SM_SHIFTCTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`sm_shiftctrl::W`](W) writer structure"] impl crate::Writable for SM_SHIFTCTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/sm_irq.rs b/src/pio0/sm_irq.rs index d894a7e37..b059f6698 100644 --- a/src/pio0/sm_irq.rs +++ b/src/pio0/sm_irq.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS"] pub struct SM_IRQ { irq_inte: IRQ_INTE, irq_intf: IRQ_INTF, diff --git a/src/pio0/sm_irq/irq_inte.rs b/src/pio0/sm_irq/irq_inte.rs index c5f950c1a..9ea0a5af4 100644 --- a/src/pio0/sm_irq/irq_inte.rs +++ b/src/pio0/sm_irq/irq_inte.rs @@ -185,16 +185,6 @@ impl W { pub fn sm3(&mut self) -> SM3_W { SM3_W::new(self, 11) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable for irq0 @@ -207,6 +197,7 @@ impl crate::RegisterSpec for IRQ_INTE_SPEC { impl crate::Readable for IRQ_INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`irq_inte::W`](W) writer structure"] impl crate::Writable for IRQ_INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/sm_irq/irq_intf.rs b/src/pio0/sm_irq/irq_intf.rs index 20c9e60a6..b6a056989 100644 --- a/src/pio0/sm_irq/irq_intf.rs +++ b/src/pio0/sm_irq/irq_intf.rs @@ -185,16 +185,6 @@ impl W { pub fn sm3(&mut self) -> SM3_W { SM3_W::new(self, 11) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force for irq0 @@ -207,6 +197,7 @@ impl crate::RegisterSpec for IRQ_INTF_SPEC { impl crate::Readable for IRQ_INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`irq_intf::W`](W) writer structure"] impl crate::Writable for IRQ_INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pio0/txf.rs b/src/pio0/txf.rs index bcd2adc5b..45803a49c 100644 --- a/src/pio0/txf.rs +++ b/src/pio0/txf.rs @@ -5,18 +5,7 @@ impl core::fmt::Debug for crate::generic::Reg { write!(f, "(not readable)") } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txf::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -26,6 +15,7 @@ impl crate::RegisterSpec for TXF_SPEC { } #[doc = "`write(|w| ..)` method takes [`txf::W`](W) writer structure"] impl crate::Writable for TXF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pll_sys.rs b/src/pll_sys.rs index 5fbcf49dc..e0c16b1ec 100644 --- a/src/pll_sys.rs +++ b/src/pll_sys.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { cs: CS, pwr: PWR, diff --git a/src/pll_sys/cs.rs b/src/pll_sys/cs.rs index 35a0de0f5..a24311e4a 100644 --- a/src/pll_sys/cs.rs +++ b/src/pll_sys/cs.rs @@ -50,16 +50,6 @@ impl W { pub fn bypass(&mut self) -> BYPASS_W { BYPASS_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control and Status GENERAL CONSTRAINTS: @@ -76,6 +66,7 @@ impl crate::RegisterSpec for CS_SPEC { impl crate::Readable for CS_SPEC {} #[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"] impl crate::Writable for CS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pll_sys/fbdiv_int.rs b/src/pll_sys/fbdiv_int.rs index 36dfdd0d7..8295a2c89 100644 --- a/src/pll_sys/fbdiv_int.rs +++ b/src/pll_sys/fbdiv_int.rs @@ -20,16 +20,6 @@ impl W { pub fn fbdiv_int(&mut self) -> FBDIV_INT_W { FBDIV_INT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Feedback divisor (note: this PLL does not support fractional division) @@ -43,6 +33,7 @@ impl crate::RegisterSpec for FBDIV_INT_SPEC { impl crate::Readable for FBDIV_INT_SPEC {} #[doc = "`write(|w| ..)` method takes [`fbdiv_int::W`](W) writer structure"] impl crate::Writable for FBDIV_INT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pll_sys/prim.rs b/src/pll_sys/prim.rs index 288ab6f85..893d1d041 100644 --- a/src/pll_sys/prim.rs +++ b/src/pll_sys/prim.rs @@ -35,16 +35,6 @@ impl W { pub fn postdiv1(&mut self) -> POSTDIV1_W { POSTDIV1_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) @@ -59,6 +49,7 @@ impl crate::RegisterSpec for PRIM_SPEC { impl crate::Readable for PRIM_SPEC {} #[doc = "`write(|w| ..)` method takes [`prim::W`](W) writer structure"] impl crate::Writable for PRIM_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pll_sys/pwr.rs b/src/pll_sys/pwr.rs index 084199c7f..de28e0723 100644 --- a/src/pll_sys/pwr.rs +++ b/src/pll_sys/pwr.rs @@ -81,16 +81,6 @@ impl W { pub fn vcopd(&mut self) -> VCOPD_W { VCOPD_W::new(self, 5) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Controls the PLL power modes. @@ -103,6 +93,7 @@ impl crate::RegisterSpec for PWR_SPEC { impl crate::Readable for PWR_SPEC {} #[doc = "`write(|w| ..)` method takes [`pwr::W`](W) writer structure"] impl crate::Writable for PWR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb.rs b/src/ppb.rs index bb6ce50e3..e8dee8f35 100644 --- a/src/ppb.rs +++ b/src/ppb.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { _reserved0: [u8; 0xe010], syst_csr: SYST_CSR, diff --git a/src/ppb/aircr.rs b/src/ppb/aircr.rs index 6800fa8bd..6421fe7b0 100644 --- a/src/ppb/aircr.rs +++ b/src/ppb/aircr.rs @@ -67,16 +67,6 @@ impl W { pub fn vectkey(&mut self) -> VECTKEY_W { VECTKEY_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. @@ -89,6 +79,7 @@ impl crate::RegisterSpec for AIRCR_SPEC { impl crate::Readable for AIRCR_SPEC {} #[doc = "`write(|w| ..)` method takes [`aircr::W`](W) writer structure"] impl crate::Writable for AIRCR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/icsr.rs b/src/ppb/icsr.rs index b9a70d2fb..962b96baa 100644 --- a/src/ppb/icsr.rs +++ b/src/ppb/icsr.rs @@ -232,16 +232,6 @@ impl W { pub fn nmipendset(&mut self) -> NMIPENDSET_W { NMIPENDSET_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. @@ -254,6 +244,7 @@ impl crate::RegisterSpec for ICSR_SPEC { impl crate::Readable for ICSR_SPEC {} #[doc = "`write(|w| ..)` method takes [`icsr::W`](W) writer structure"] impl crate::Writable for ICSR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/mpu_ctrl.rs b/src/ppb/mpu_ctrl.rs index 912e7ef91..cf7f7d414 100644 --- a/src/ppb/mpu_ctrl.rs +++ b/src/ppb/mpu_ctrl.rs @@ -86,16 +86,6 @@ impl W { pub fn privdefena(&mut self) -> PRIVDEFENA_W { PRIVDEFENA_W::new(self, 2) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. @@ -108,6 +98,7 @@ impl crate::RegisterSpec for MPU_CTRL_SPEC { impl crate::Readable for MPU_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`mpu_ctrl::W`](W) writer structure"] impl crate::Writable for MPU_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/mpu_rasr.rs b/src/ppb/mpu_rasr.rs index 807b73510..0147611b6 100644 --- a/src/ppb/mpu_rasr.rs +++ b/src/ppb/mpu_rasr.rs @@ -93,16 +93,6 @@ impl W { pub fn attrs(&mut self) -> ATTRS_W { ATTRS_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. @@ -115,6 +105,7 @@ impl crate::RegisterSpec for MPU_RASR_SPEC { impl crate::Readable for MPU_RASR_SPEC {} #[doc = "`write(|w| ..)` method takes [`mpu_rasr::W`](W) writer structure"] impl crate::Writable for MPU_RASR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/mpu_rbar.rs b/src/ppb/mpu_rbar.rs index ae2c57acb..b59f5b3ac 100644 --- a/src/ppb/mpu_rbar.rs +++ b/src/ppb/mpu_rbar.rs @@ -86,16 +86,6 @@ of MPU_RNR."] pub fn addr(&mut self) -> ADDR_W { ADDR_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. @@ -108,6 +98,7 @@ impl crate::RegisterSpec for MPU_RBAR_SPEC { impl crate::Readable for MPU_RBAR_SPEC {} #[doc = "`write(|w| ..)` method takes [`mpu_rbar::W`](W) writer structure"] impl crate::Writable for MPU_RBAR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/mpu_rnr.rs b/src/ppb/mpu_rnr.rs index d47cd5152..d1e57574f 100644 --- a/src/ppb/mpu_rnr.rs +++ b/src/ppb/mpu_rnr.rs @@ -24,16 +24,6 @@ impl W { pub fn region(&mut self) -> REGION_W { REGION_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. @@ -46,6 +36,7 @@ impl crate::RegisterSpec for MPU_RNR_SPEC { impl crate::Readable for MPU_RNR_SPEC {} #[doc = "`write(|w| ..)` method takes [`mpu_rnr::W`](W) writer structure"] impl crate::Writable for MPU_RNR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_icer.rs b/src/ppb/nvic_icer.rs index 398541ccb..492c9a4f2 100644 --- a/src/ppb/nvic_icer.rs +++ b/src/ppb/nvic_icer.rs @@ -44,16 +44,6 @@ impl W { pub fn clrena(&mut self) -> CLRENA_W { CLRENA_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. @@ -66,6 +56,7 @@ impl crate::RegisterSpec for NVIC_ICER_SPEC { impl crate::Readable for NVIC_ICER_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_icer::W`](W) writer structure"] impl crate::Writable for NVIC_ICER_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_icpr.rs b/src/ppb/nvic_icpr.rs index 03ae0837e..d1266559f 100644 --- a/src/ppb/nvic_icpr.rs +++ b/src/ppb/nvic_icpr.rs @@ -44,16 +44,6 @@ impl W { pub fn clrpend(&mut self) -> CLRPEND_W { CLRPEND_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. @@ -66,6 +56,7 @@ impl crate::RegisterSpec for NVIC_ICPR_SPEC { impl crate::Readable for NVIC_ICPR_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_icpr::W`](W) writer structure"] impl crate::Writable for NVIC_ICPR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr0.rs b/src/ppb/nvic_ipr0.rs index 4a358982e..829f9209c 100644 --- a/src/ppb/nvic_ipr0.rs +++ b/src/ppb/nvic_ipr0.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_3(&mut self) -> IP_3_W { IP_3_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. @@ -89,6 +79,7 @@ impl crate::RegisterSpec for NVIC_IPR0_SPEC { impl crate::Readable for NVIC_IPR0_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr0::W`](W) writer structure"] impl crate::Writable for NVIC_IPR0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr1.rs b/src/ppb/nvic_ipr1.rs index d8e522a11..0dd33bc6c 100644 --- a/src/ppb/nvic_ipr1.rs +++ b/src/ppb/nvic_ipr1.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_7(&mut self) -> IP_7_W { IP_7_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for NVIC_IPR1_SPEC { impl crate::Readable for NVIC_IPR1_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr1::W`](W) writer structure"] impl crate::Writable for NVIC_IPR1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr2.rs b/src/ppb/nvic_ipr2.rs index 779ddcc85..6e7e90f7f 100644 --- a/src/ppb/nvic_ipr2.rs +++ b/src/ppb/nvic_ipr2.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_11(&mut self) -> IP_11_W { IP_11_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for NVIC_IPR2_SPEC { impl crate::Readable for NVIC_IPR2_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr2::W`](W) writer structure"] impl crate::Writable for NVIC_IPR2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr3.rs b/src/ppb/nvic_ipr3.rs index eb44f05c4..dc0f6aa80 100644 --- a/src/ppb/nvic_ipr3.rs +++ b/src/ppb/nvic_ipr3.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_15(&mut self) -> IP_15_W { IP_15_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for NVIC_IPR3_SPEC { impl crate::Readable for NVIC_IPR3_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr3::W`](W) writer structure"] impl crate::Writable for NVIC_IPR3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr4.rs b/src/ppb/nvic_ipr4.rs index b6cfaa5ee..3dd6d0193 100644 --- a/src/ppb/nvic_ipr4.rs +++ b/src/ppb/nvic_ipr4.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_19(&mut self) -> IP_19_W { IP_19_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for NVIC_IPR4_SPEC { impl crate::Readable for NVIC_IPR4_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr4::W`](W) writer structure"] impl crate::Writable for NVIC_IPR4_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr5.rs b/src/ppb/nvic_ipr5.rs index 99497277a..381f61c8d 100644 --- a/src/ppb/nvic_ipr5.rs +++ b/src/ppb/nvic_ipr5.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_23(&mut self) -> IP_23_W { IP_23_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for NVIC_IPR5_SPEC { impl crate::Readable for NVIC_IPR5_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr5::W`](W) writer structure"] impl crate::Writable for NVIC_IPR5_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr6.rs b/src/ppb/nvic_ipr6.rs index fa92583fe..dc6e71849 100644 --- a/src/ppb/nvic_ipr6.rs +++ b/src/ppb/nvic_ipr6.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_27(&mut self) -> IP_27_W { IP_27_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for NVIC_IPR6_SPEC { impl crate::Readable for NVIC_IPR6_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr6::W`](W) writer structure"] impl crate::Writable for NVIC_IPR6_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ipr7.rs b/src/ppb/nvic_ipr7.rs index cc32b8d75..6a8735518 100644 --- a/src/ppb/nvic_ipr7.rs +++ b/src/ppb/nvic_ipr7.rs @@ -65,16 +65,6 @@ impl W { pub fn ip_31(&mut self) -> IP_31_W { IP_31_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for NVIC_IPR7_SPEC { impl crate::Readable for NVIC_IPR7_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ipr7::W`](W) writer structure"] impl crate::Writable for NVIC_IPR7_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_iser.rs b/src/ppb/nvic_iser.rs index 27bd51ea8..314c4d7f3 100644 --- a/src/ppb/nvic_iser.rs +++ b/src/ppb/nvic_iser.rs @@ -44,16 +44,6 @@ impl W { pub fn setena(&mut self) -> SETENA_W { SETENA_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. @@ -67,6 +57,7 @@ impl crate::RegisterSpec for NVIC_ISER_SPEC { impl crate::Readable for NVIC_ISER_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_iser::W`](W) writer structure"] impl crate::Writable for NVIC_ISER_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/nvic_ispr.rs b/src/ppb/nvic_ispr.rs index 79ba0ad02..e3462d616 100644 --- a/src/ppb/nvic_ispr.rs +++ b/src/ppb/nvic_ispr.rs @@ -56,16 +56,6 @@ impl W { pub fn setpend(&mut self) -> SETPEND_W { SETPEND_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. @@ -78,6 +68,7 @@ impl crate::RegisterSpec for NVIC_ISPR_SPEC { impl crate::Readable for NVIC_ISPR_SPEC {} #[doc = "`write(|w| ..)` method takes [`nvic_ispr::W`](W) writer structure"] impl crate::Writable for NVIC_ISPR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/scr.rs b/src/ppb/scr.rs index 9c6ddc363..e21e417a4 100644 --- a/src/ppb/scr.rs +++ b/src/ppb/scr.rs @@ -90,16 +90,6 @@ impl W { pub fn sevonpend(&mut self) -> SEVONPEND_W { SEVONPEND_W::new(self, 4) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. @@ -112,6 +102,7 @@ impl crate::RegisterSpec for SCR_SPEC { impl crate::Readable for SCR_SPEC {} #[doc = "`write(|w| ..)` method takes [`scr::W`](W) writer structure"] impl crate::Writable for SCR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/shcsr.rs b/src/ppb/shcsr.rs index 2c3530bc1..c3f2a47cf 100644 --- a/src/ppb/shcsr.rs +++ b/src/ppb/shcsr.rs @@ -20,16 +20,6 @@ impl W { pub fn svcallpended(&mut self) -> SVCALLPENDED_W { SVCALLPENDED_W::new(self, 15) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the System Handler Control and State Register to determine or clear the pending status of SVCall. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for SHCSR_SPEC { impl crate::Readable for SHCSR_SPEC {} #[doc = "`write(|w| ..)` method takes [`shcsr::W`](W) writer structure"] impl crate::Writable for SHCSR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/shpr2.rs b/src/ppb/shpr2.rs index 418e0a620..f3a64b296 100644 --- a/src/ppb/shpr2.rs +++ b/src/ppb/shpr2.rs @@ -20,16 +20,6 @@ impl W { pub fn pri_11(&mut self) -> PRI_11_W { PRI_11_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for SHPR2_SPEC { impl crate::Readable for SHPR2_SPEC {} #[doc = "`write(|w| ..)` method takes [`shpr2::W`](W) writer structure"] impl crate::Writable for SHPR2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/shpr3.rs b/src/ppb/shpr3.rs index c2f691322..cb51288d4 100644 --- a/src/ppb/shpr3.rs +++ b/src/ppb/shpr3.rs @@ -35,16 +35,6 @@ impl W { pub fn pri_15(&mut self) -> PRI_15_W { PRI_15_W::new(self, 30) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. @@ -57,6 +47,7 @@ impl crate::RegisterSpec for SHPR3_SPEC { impl crate::Readable for SHPR3_SPEC {} #[doc = "`write(|w| ..)` method takes [`shpr3::W`](W) writer structure"] impl crate::Writable for SHPR3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/syst_csr.rs b/src/ppb/syst_csr.rs index 8273f2c8c..40c993501 100644 --- a/src/ppb/syst_csr.rs +++ b/src/ppb/syst_csr.rs @@ -85,16 +85,6 @@ impl W { pub fn clksource(&mut self) -> CLKSOURCE_W { CLKSOURCE_W::new(self, 2) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the SysTick Control and Status Register to enable the SysTick features. @@ -107,6 +97,7 @@ impl crate::RegisterSpec for SYST_CSR_SPEC { impl crate::Readable for SYST_CSR_SPEC {} #[doc = "`write(|w| ..)` method takes [`syst_csr::W`](W) writer structure"] impl crate::Writable for SYST_CSR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/syst_cvr.rs b/src/ppb/syst_cvr.rs index 00f6434e1..8d9bca983 100644 --- a/src/ppb/syst_cvr.rs +++ b/src/ppb/syst_cvr.rs @@ -20,16 +20,6 @@ impl W { pub fn current(&mut self) -> CURRENT_W { CURRENT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for SYST_CVR_SPEC { impl crate::Readable for SYST_CVR_SPEC {} #[doc = "`write(|w| ..)` method takes [`syst_cvr::W`](W) writer structure"] impl crate::Writable for SYST_CVR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/syst_rvr.rs b/src/ppb/syst_rvr.rs index 65de7037f..4e8f0451e 100644 --- a/src/ppb/syst_rvr.rs +++ b/src/ppb/syst_rvr.rs @@ -20,16 +20,6 @@ impl W { pub fn reload(&mut self) -> RELOAD_W { RELOAD_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. @@ -43,6 +33,7 @@ impl crate::RegisterSpec for SYST_RVR_SPEC { impl crate::Readable for SYST_RVR_SPEC {} #[doc = "`write(|w| ..)` method takes [`syst_rvr::W`](W) writer structure"] impl crate::Writable for SYST_RVR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/ppb/vtor.rs b/src/ppb/vtor.rs index 7ccab12c3..bf4d3877e 100644 --- a/src/ppb/vtor.rs +++ b/src/ppb/vtor.rs @@ -24,16 +24,6 @@ of the indicate the vector table offset address."] pub fn tbloff(&mut self) -> TBLOFF_W { TBLOFF_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "The VTOR holds the vector table offset address. @@ -46,6 +36,7 @@ impl crate::RegisterSpec for VTOR_SPEC { impl crate::Readable for VTOR_SPEC {} #[doc = "`write(|w| ..)` method takes [`vtor::W`](W) writer structure"] impl crate::Writable for VTOR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/psm.rs b/src/psm.rs index feb6cf005..c31b8c163 100644 --- a/src/psm.rs +++ b/src/psm.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { frce_on: FRCE_ON, frce_off: FRCE_OFF, diff --git a/src/psm/frce_off.rs b/src/psm/frce_off.rs index 46f7d027f..762808564 100644 --- a/src/psm/frce_off.rs +++ b/src/psm/frce_off.rs @@ -260,16 +260,6 @@ impl W { pub fn proc1(&mut self) -> PROC1_W { PROC1_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Force into reset (i.e. power it off) @@ -282,6 +272,7 @@ impl crate::RegisterSpec for FRCE_OFF_SPEC { impl crate::Readable for FRCE_OFF_SPEC {} #[doc = "`write(|w| ..)` method takes [`frce_off::W`](W) writer structure"] impl crate::Writable for FRCE_OFF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/psm/frce_on.rs b/src/psm/frce_on.rs index af11db00f..b13ba24ae 100644 --- a/src/psm/frce_on.rs +++ b/src/psm/frce_on.rs @@ -260,16 +260,6 @@ impl W { pub fn proc1(&mut self) -> PROC1_W { PROC1_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Force block out of reset (i.e. power it on) @@ -282,6 +272,7 @@ impl crate::RegisterSpec for FRCE_ON_SPEC { impl crate::Readable for FRCE_ON_SPEC {} #[doc = "`write(|w| ..)` method takes [`frce_on::W`](W) writer structure"] impl crate::Writable for FRCE_ON_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/psm/wdsel.rs b/src/psm/wdsel.rs index c439e284f..9a5c5d30a 100644 --- a/src/psm/wdsel.rs +++ b/src/psm/wdsel.rs @@ -260,16 +260,6 @@ impl W { pub fn proc1(&mut self) -> PROC1_W { PROC1_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Set to 1 if this peripheral should be reset when the watchdog fires. @@ -282,6 +272,7 @@ impl crate::RegisterSpec for WDSEL_SPEC { impl crate::Readable for WDSEL_SPEC {} #[doc = "`write(|w| ..)` method takes [`wdsel::W`](W) writer structure"] impl crate::Writable for WDSEL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm.rs b/src/pwm.rs index a9dedd880..cfe10ce1c 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ch: [CH; 8], en: EN, diff --git a/src/pwm/ch.rs b/src/pwm/ch.rs index 0e58dd567..e5b3a229b 100644 --- a/src/pwm/ch.rs +++ b/src/pwm/ch.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP"] pub struct CH { csr: CSR, div: DIV, diff --git a/src/pwm/ch/cc.rs b/src/pwm/ch/cc.rs index 8a1fd4c6f..2e5f9c4c5 100644 --- a/src/pwm/ch/cc.rs +++ b/src/pwm/ch/cc.rs @@ -35,16 +35,6 @@ impl W { pub fn b(&mut self) -> B_W { B_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Counter compare values @@ -57,6 +47,7 @@ impl crate::RegisterSpec for CC_SPEC { impl crate::Readable for CC_SPEC {} #[doc = "`write(|w| ..)` method takes [`cc::W`](W) writer structure"] impl crate::Writable for CC_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/ch/csr.rs b/src/pwm/ch/csr.rs index c939127fd..991645642 100644 --- a/src/pwm/ch/csr.rs +++ b/src/pwm/ch/csr.rs @@ -18,8 +18,6 @@ pub type A_INV_W<'a, REG> = crate::BitWriter<'a, REG>; pub type B_INV_R = crate::BitReader; #[doc = "Field `B_INV` writer - Invert output B"] pub type B_INV_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DIVMODE` reader - "] -pub type DIVMODE_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for DIVMODE_A { type Ux = u8; } +#[doc = "Field `DIVMODE` reader - "] +pub type DIVMODE_R = crate::FieldReader; impl DIVMODE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -205,16 +205,6 @@ impl W { pub fn ph_adv(&mut self) -> PH_ADV_W { PH_ADV_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control and status register @@ -227,6 +217,7 @@ impl crate::RegisterSpec for CSR_SPEC { impl crate::Readable for CSR_SPEC {} #[doc = "`write(|w| ..)` method takes [`csr::W`](W) writer structure"] impl crate::Writable for CSR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/ch/ctr.rs b/src/pwm/ch/ctr.rs index d4ac1b80f..b16809b46 100644 --- a/src/pwm/ch/ctr.rs +++ b/src/pwm/ch/ctr.rs @@ -20,16 +20,6 @@ impl W { pub fn ctr(&mut self) -> CTR_W { CTR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Direct access to the PWM counter @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CTR_SPEC { impl crate::Readable for CTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"] impl crate::Writable for CTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/ch/div.rs b/src/pwm/ch/div.rs index c7866c80f..6c0ea55e2 100644 --- a/src/pwm/ch/div.rs +++ b/src/pwm/ch/div.rs @@ -35,16 +35,6 @@ impl W { pub fn int(&mut self) -> INT_W { INT_W::new(self, 4) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. @@ -59,6 +49,7 @@ impl crate::RegisterSpec for DIV_SPEC { impl crate::Readable for DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/ch/top.rs b/src/pwm/ch/top.rs index 111686578..6cd87eb82 100644 --- a/src/pwm/ch/top.rs +++ b/src/pwm/ch/top.rs @@ -20,16 +20,6 @@ impl W { pub fn top(&mut self) -> TOP_W { TOP_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Counter wrap value @@ -42,6 +32,7 @@ impl crate::RegisterSpec for TOP_SPEC { impl crate::Readable for TOP_SPEC {} #[doc = "`write(|w| ..)` method takes [`top::W`](W) writer structure"] impl crate::Writable for TOP_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/en.rs b/src/pwm/en.rs index 264093dfb..1e28b4742 100644 --- a/src/pwm/en.rs +++ b/src/pwm/en.rs @@ -125,16 +125,6 @@ impl W { pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled @@ -151,6 +141,7 @@ impl crate::RegisterSpec for EN_SPEC { impl crate::Readable for EN_SPEC {} #[doc = "`write(|w| ..)` method takes [`en::W`](W) writer structure"] impl crate::Writable for EN_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/inte.rs b/src/pwm/inte.rs index 7ac8d7079..6da30341b 100644 --- a/src/pwm/inte.rs +++ b/src/pwm/inte.rs @@ -125,16 +125,6 @@ impl W { pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable @@ -147,6 +137,7 @@ impl crate::RegisterSpec for INTE_SPEC { impl crate::Readable for INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/intf.rs b/src/pwm/intf.rs index 985854594..d4da1df39 100644 --- a/src/pwm/intf.rs +++ b/src/pwm/intf.rs @@ -125,16 +125,6 @@ impl W { pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force @@ -147,6 +137,7 @@ impl crate::RegisterSpec for INTF_SPEC { impl crate::Readable for INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/pwm/intr.rs b/src/pwm/intr.rs index 2097df5f9..0f14da7e1 100644 --- a/src/pwm/intr.rs +++ b/src/pwm/intr.rs @@ -125,16 +125,6 @@ impl W { pub fn ch7(&mut self) -> CH7_W { CH7_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Raw Interrupts @@ -147,6 +137,7 @@ impl crate::RegisterSpec for INTR_SPEC { impl crate::Readable for INTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff; } diff --git a/src/resets.rs b/src/resets.rs index 1d5883f54..01d9db6d4 100644 --- a/src/resets.rs +++ b/src/resets.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { reset: RESET, wdsel: WDSEL, diff --git a/src/resets/reset.rs b/src/resets/reset.rs index 58397796f..7920fb593 100644 --- a/src/resets/reset.rs +++ b/src/resets/reset.rs @@ -380,16 +380,6 @@ impl W { pub fn usbctrl(&mut self) -> USBCTRL_W { USBCTRL_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. @@ -402,6 +392,7 @@ impl crate::RegisterSpec for RESET_SPEC { impl crate::Readable for RESET_SPEC {} #[doc = "`write(|w| ..)` method takes [`reset::W`](W) writer structure"] impl crate::Writable for RESET_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/resets/wdsel.rs b/src/resets/wdsel.rs index 8d2798a4e..325379277 100644 --- a/src/resets/wdsel.rs +++ b/src/resets/wdsel.rs @@ -380,16 +380,6 @@ impl W { pub fn usbctrl(&mut self) -> USBCTRL_W { USBCTRL_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. @@ -402,6 +392,7 @@ impl crate::RegisterSpec for WDSEL_SPEC { impl crate::Readable for WDSEL_SPEC {} #[doc = "`write(|w| ..)` method takes [`wdsel::W`](W) writer structure"] impl crate::Writable for WDSEL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rosc.rs b/src/rosc.rs index 5c9bb99d9..35c81fc3e 100644 --- a/src/rosc.rs +++ b/src/rosc.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ctrl: CTRL, freqa: FREQA, diff --git a/src/rosc/ctrl.rs b/src/rosc/ctrl.rs index 8b7b8cf87..66bbef5e0 100644 --- a/src/rosc/ctrl.rs +++ b/src/rosc/ctrl.rs @@ -2,15 +2,6 @@ pub type R = crate::R; #[doc = "Register `CTRL` writer"] pub type W = crate::W; -#[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 0 to 5 - HIGH uses stages 0 to 3 - TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications - The clock output will not glitch when changing the range up one step at a time - The clock output will glitch when changing the range down - Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] -pub type FREQ_RANGE_R = crate::FieldReader; #[doc = "Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 0 to 5 @@ -42,6 +33,15 @@ impl From for u16 { impl crate::FieldSpec for FREQ_RANGE_A { type Ux = u16; } +#[doc = "Field `FREQ_RANGE` reader - Controls the number of delay stages in the ROSC ring + LOW uses stages 0 to 7 + MEDIUM uses stages 0 to 5 + HIGH uses stages 0 to 3 + TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications + The clock output will not glitch when changing the range up one step at a time + The clock output will glitch when changing the range down + Note: the values here are gray coded which is why HIGH comes before TOOHIGH"] +pub type FREQ_RANGE_R = crate::FieldReader; impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -110,10 +110,6 @@ where self.variant(FREQ_RANGE_A::TOOHIGH) } } -#[doc = "Field `ENABLE` reader - On power-up this field is initialised to ENABLE - The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] -pub type ENABLE_R = crate::FieldReader; #[doc = "On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. @@ -136,6 +132,10 @@ impl From for u16 { impl crate::FieldSpec for ENABLE_A { type Ux = u16; } +#[doc = "Field `ENABLE` reader - On power-up this field is initialised to ENABLE + The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +pub type ENABLE_R = crate::FieldReader; impl ENABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -220,16 +220,6 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 12) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Ring Oscillator control @@ -242,6 +232,7 @@ impl crate::RegisterSpec for CTRL_SPEC { impl crate::Readable for CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rosc/div.rs b/src/rosc/div.rs index f42b6bf84..d79cf2155 100644 --- a/src/rosc/div.rs +++ b/src/rosc/div.rs @@ -2,12 +2,6 @@ pub type R = crate::R; #[doc = "Register `DIV` writer"] pub type W = crate::W; -#[doc = "Field `DIV` reader - set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=31 - this register resets to div=16"] -pub type DIV_R = crate::FieldReader; #[doc = "set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div @@ -30,6 +24,12 @@ impl From for u16 { impl crate::FieldSpec for DIV_A { type Ux = u16; } +#[doc = "Field `DIV` reader - set to 0xaa0 + div where + div = 0 divides by 32 + div = 1-31 divides by div + any other value sets div=31 + this register resets to div=16"] +pub type DIV_R = crate::FieldReader; impl DIV_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -84,16 +84,6 @@ impl W { pub fn div(&mut self) -> DIV_W { DIV_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Controls the output divider @@ -106,6 +96,7 @@ impl crate::RegisterSpec for DIV_SPEC { impl crate::Readable for DIV_SPEC {} #[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"] impl crate::Writable for DIV_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rosc/dormant.rs b/src/rosc/dormant.rs index 88e9ed386..1697d4d00 100644 --- a/src/rosc/dormant.rs +++ b/src/rosc/dormant.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Ring Oscillator pause control This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE @@ -39,6 +28,7 @@ impl crate::RegisterSpec for DORMANT_SPEC { impl crate::Readable for DORMANT_SPEC {} #[doc = "`write(|w| ..)` method takes [`dormant::W`](W) writer structure"] impl crate::Writable for DORMANT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rosc/freqa.rs b/src/rosc/freqa.rs index c8d0f36c6..d7c9b6476 100644 --- a/src/rosc/freqa.rs +++ b/src/rosc/freqa.rs @@ -18,9 +18,6 @@ pub type DS2_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; pub type DS3_R = crate::FieldReader; #[doc = "Field `DS3` writer - Stage 3 drive strength"] pub type DS3_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] -pub type PASSWD_R = crate::FieldReader; #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 @@ -40,6 +37,9 @@ impl From for u16 { impl crate::FieldSpec for PASSWD_A { type Ux = u16; } +#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0"] +pub type PASSWD_R = crate::FieldReader; impl PASSWD_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -129,16 +129,6 @@ impl W { pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set @@ -157,6 +147,7 @@ impl crate::RegisterSpec for FREQA_SPEC { impl crate::Readable for FREQA_SPEC {} #[doc = "`write(|w| ..)` method takes [`freqa::W`](W) writer structure"] impl crate::Writable for FREQA_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rosc/freqb.rs b/src/rosc/freqb.rs index 7251c1836..c87b40ad0 100644 --- a/src/rosc/freqb.rs +++ b/src/rosc/freqb.rs @@ -18,9 +18,6 @@ pub type DS6_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; pub type DS7_R = crate::FieldReader; #[doc = "Field `DS7` writer - Stage 7 drive strength"] pub type DS7_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths to 0"] -pub type PASSWD_R = crate::FieldReader; #[doc = "Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 @@ -40,6 +37,9 @@ impl From for u16 { impl crate::FieldSpec for PASSWD_A { type Ux = u16; } +#[doc = "Field `PASSWD` reader - Set to 0x9696 to apply the settings + Any other value in this field will set all drive strengths to 0"] +pub type PASSWD_R = crate::FieldReader; impl PASSWD_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -129,16 +129,6 @@ impl W { pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "For a detailed description see freqa register @@ -151,6 +141,7 @@ impl crate::RegisterSpec for FREQB_SPEC { impl crate::Readable for FREQB_SPEC {} #[doc = "`write(|w| ..)` method takes [`freqb::W`](W) writer structure"] impl crate::Writable for FREQB_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rosc/phase.rs b/src/rosc/phase.rs index dc32ed81e..7275ec351 100644 --- a/src/rosc/phase.rs +++ b/src/rosc/phase.rs @@ -85,16 +85,6 @@ impl W { pub fn passwd(&mut self) -> PASSWD_W { PASSWD_W::new(self, 4) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Controls the phase shifted output @@ -107,6 +97,7 @@ impl crate::RegisterSpec for PHASE_SPEC { impl crate::Readable for PHASE_SPEC {} #[doc = "`write(|w| ..)` method takes [`phase::W`](W) writer structure"] impl crate::Writable for PHASE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc.rs b/src/rtc.rs index 283aa8027..3cac0834b 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { clkdiv_m1: CLKDIV_M1, setup_0: SETUP_0, diff --git a/src/rtc/clkdiv_m1.rs b/src/rtc/clkdiv_m1.rs index a94ae6142..0ba545123 100644 --- a/src/rtc/clkdiv_m1.rs +++ b/src/rtc/clkdiv_m1.rs @@ -20,16 +20,6 @@ impl W { pub fn clkdiv_m1(&mut self) -> CLKDIV_M1_W { CLKDIV_M1_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CLKDIV_M1_SPEC { impl crate::Readable for CLKDIV_M1_SPEC {} #[doc = "`write(|w| ..)` method takes [`clkdiv_m1::W`](W) writer structure"] impl crate::Writable for CLKDIV_M1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc/ctrl.rs b/src/rtc/ctrl.rs index 4439cc0e8..c4a46dc86 100644 --- a/src/rtc/ctrl.rs +++ b/src/rtc/ctrl.rs @@ -61,16 +61,6 @@ impl W { pub fn force_notleapyear(&mut self) -> FORCE_NOTLEAPYEAR_W { FORCE_NOTLEAPYEAR_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "RTC Control and status @@ -83,6 +73,7 @@ impl crate::RegisterSpec for CTRL_SPEC { impl crate::Readable for CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc/inte.rs b/src/rtc/inte.rs index 2716e2f7e..c280da2d3 100644 --- a/src/rtc/inte.rs +++ b/src/rtc/inte.rs @@ -20,16 +20,6 @@ impl W { pub fn rtc(&mut self) -> RTC_W { RTC_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTE_SPEC { impl crate::Readable for INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc/intf.rs b/src/rtc/intf.rs index 7ecc14dec..014bdf87c 100644 --- a/src/rtc/intf.rs +++ b/src/rtc/intf.rs @@ -20,16 +20,6 @@ impl W { pub fn rtc(&mut self) -> RTC_W { RTC_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INTF_SPEC { impl crate::Readable for INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc/irq_setup_0.rs b/src/rtc/irq_setup_0.rs index cc59dc56b..b1791574c 100644 --- a/src/rtc/irq_setup_0.rs +++ b/src/rtc/irq_setup_0.rs @@ -117,16 +117,6 @@ impl W { pub fn match_ena(&mut self) -> MATCH_ENA_W { MATCH_ENA_W::new(self, 28) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt setup register 0 @@ -139,6 +129,7 @@ impl crate::RegisterSpec for IRQ_SETUP_0_SPEC { impl crate::Readable for IRQ_SETUP_0_SPEC {} #[doc = "`write(|w| ..)` method takes [`irq_setup_0::W`](W) writer structure"] impl crate::Writable for IRQ_SETUP_0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc/irq_setup_1.rs b/src/rtc/irq_setup_1.rs index 8175e033c..4525a710a 100644 --- a/src/rtc/irq_setup_1.rs +++ b/src/rtc/irq_setup_1.rs @@ -125,16 +125,6 @@ impl W { pub fn dotw_ena(&mut self) -> DOTW_ENA_W { DOTW_ENA_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt setup register 1 @@ -147,6 +137,7 @@ impl crate::RegisterSpec for IRQ_SETUP_1_SPEC { impl crate::Readable for IRQ_SETUP_1_SPEC {} #[doc = "`write(|w| ..)` method takes [`irq_setup_1::W`](W) writer structure"] impl crate::Writable for IRQ_SETUP_1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc/setup_0.rs b/src/rtc/setup_0.rs index bd5c96a17..1bd9864d0 100644 --- a/src/rtc/setup_0.rs +++ b/src/rtc/setup_0.rs @@ -50,16 +50,6 @@ impl W { pub fn year(&mut self) -> YEAR_W { YEAR_W::new(self, 12) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "RTC setup register 0 @@ -72,6 +62,7 @@ impl crate::RegisterSpec for SETUP_0_SPEC { impl crate::Readable for SETUP_0_SPEC {} #[doc = "`write(|w| ..)` method takes [`setup_0::W`](W) writer structure"] impl crate::Writable for SETUP_0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/rtc/setup_1.rs b/src/rtc/setup_1.rs index 977c8cb0a..05b1bdff6 100644 --- a/src/rtc/setup_1.rs +++ b/src/rtc/setup_1.rs @@ -65,16 +65,6 @@ impl W { pub fn dotw(&mut self) -> DOTW_W { DOTW_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "RTC setup register 1 @@ -87,6 +77,7 @@ impl crate::RegisterSpec for SETUP_1_SPEC { impl crate::Readable for SETUP_1_SPEC {} #[doc = "`write(|w| ..)` method takes [`setup_1::W`](W) writer structure"] impl crate::Writable for SETUP_1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio.rs b/src/sio.rs index 54b7c25b5..2b5353da9 100644 --- a/src/sio.rs +++ b/src/sio.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { cpuid: CPUID, gpio_in: GPIO_IN, diff --git a/src/sio/div_quotient.rs b/src/sio/div_quotient.rs index d84d448bd..d16a6cda5 100644 --- a/src/sio/div_quotient.rs +++ b/src/sio/div_quotient.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. @@ -41,6 +30,7 @@ impl crate::RegisterSpec for DIV_QUOTIENT_SPEC { impl crate::Readable for DIV_QUOTIENT_SPEC {} #[doc = "`write(|w| ..)` method takes [`div_quotient::W`](W) writer structure"] impl crate::Writable for DIV_QUOTIENT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/div_remainder.rs b/src/sio/div_remainder.rs index e8dff470c..12e963907 100644 --- a/src/sio/div_remainder.rs +++ b/src/sio/div_remainder.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. @@ -39,6 +28,7 @@ impl crate::RegisterSpec for DIV_REMAINDER_SPEC { impl crate::Readable for DIV_REMAINDER_SPEC {} #[doc = "`write(|w| ..)` method takes [`div_remainder::W`](W) writer structure"] impl crate::Writable for DIV_REMAINDER_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/div_sdividend.rs b/src/sio/div_sdividend.rs index 44506a40d..f94dfeefd 100644 --- a/src/sio/div_sdividend.rs +++ b/src/sio/div_sdividend.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. @@ -36,6 +25,7 @@ impl crate::RegisterSpec for DIV_SDIVIDEND_SPEC { impl crate::Readable for DIV_SDIVIDEND_SPEC {} #[doc = "`write(|w| ..)` method takes [`div_sdividend::W`](W) writer structure"] impl crate::Writable for DIV_SDIVIDEND_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/div_sdivisor.rs b/src/sio/div_sdivisor.rs index 30ab8a41b..b6a93d79d 100644 --- a/src/sio/div_sdivisor.rs +++ b/src/sio/div_sdivisor.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned. @@ -36,6 +25,7 @@ impl crate::RegisterSpec for DIV_SDIVISOR_SPEC { impl crate::Readable for DIV_SDIVISOR_SPEC {} #[doc = "`write(|w| ..)` method takes [`div_sdivisor::W`](W) writer structure"] impl crate::Writable for DIV_SDIVISOR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/div_udividend.rs b/src/sio/div_udividend.rs index 2e2fe09a9..7dce964b5 100644 --- a/src/sio/div_udividend.rs +++ b/src/sio/div_udividend.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. @@ -39,6 +28,7 @@ impl crate::RegisterSpec for DIV_UDIVIDEND_SPEC { impl crate::Readable for DIV_UDIVIDEND_SPEC {} #[doc = "`write(|w| ..)` method takes [`div_udividend::W`](W) writer structure"] impl crate::Writable for DIV_UDIVIDEND_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/div_udivisor.rs b/src/sio/div_udivisor.rs index 97ec75d53..835a5d191 100644 --- a/src/sio/div_udivisor.rs +++ b/src/sio/div_udivisor.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. @@ -39,6 +28,7 @@ impl crate::RegisterSpec for DIV_UDIVISOR_SPEC { impl crate::Readable for DIV_UDIVISOR_SPEC {} #[doc = "`write(|w| ..)` method takes [`div_udivisor::W`](W) writer structure"] impl crate::Writable for DIV_UDIVISOR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/fifo_st.rs b/src/sio/fifo_st.rs index d1c19e49e..4429b09fd 100644 --- a/src/sio/fifo_st.rs +++ b/src/sio/fifo_st.rs @@ -49,16 +49,6 @@ impl W { pub fn roe(&mut self) -> ROE_W { ROE_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. @@ -75,6 +65,7 @@ impl crate::RegisterSpec for FIFO_ST_SPEC { impl crate::Readable for FIFO_ST_SPEC {} #[doc = "`write(|w| ..)` method takes [`fifo_st::W`](W) writer structure"] impl crate::Writable for FIFO_ST_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c; } diff --git a/src/sio/fifo_wr.rs b/src/sio/fifo_wr.rs index 137871a60..b36d923d6 100644 --- a/src/sio/fifo_wr.rs +++ b/src/sio/fifo_wr.rs @@ -5,18 +5,7 @@ impl core::fmt::Debug for crate::generic::Reg { write!(f, "(not readable)") } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Write access to this core's TX FIFO You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -26,6 +15,7 @@ impl crate::RegisterSpec for FIFO_WR_SPEC { } #[doc = "`write(|w| ..)` method takes [`fifo_wr::W`](W) writer structure"] impl crate::Writable for FIFO_WR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_oe.rs b/src/sio/gpio_hi_oe.rs index 7857d4959..d5dfa20da 100644 --- a/src/sio/gpio_hi_oe.rs +++ b/src/sio/gpio_hi_oe.rs @@ -36,16 +36,6 @@ impl W { pub fn gpio_hi_oe(&mut self) -> GPIO_HI_OE_W { GPIO_HI_OE_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output enable @@ -58,6 +48,7 @@ impl crate::RegisterSpec for GPIO_HI_OE_SPEC { impl crate::Readable for GPIO_HI_OE_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_oe::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_oe_clr.rs b/src/sio/gpio_hi_oe_clr.rs index 6e5400015..748742b54 100644 --- a/src/sio/gpio_hi_oe_clr.rs +++ b/src/sio/gpio_hi_oe_clr.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_hi_oe_clr(&mut self) -> GPIO_HI_OE_CLR_W { GPIO_HI_OE_CLR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output enable clear @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_HI_OE_CLR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_clr::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_CLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_oe_set.rs b/src/sio/gpio_hi_oe_set.rs index 034f78f19..094595426 100644 --- a/src/sio/gpio_hi_oe_set.rs +++ b/src/sio/gpio_hi_oe_set.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_hi_oe_set(&mut self) -> GPIO_HI_OE_SET_W { GPIO_HI_OE_SET_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output enable set @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_HI_OE_SET_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_set::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_SET_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_oe_xor.rs b/src/sio/gpio_hi_oe_xor.rs index e20da21d0..76a630857 100644 --- a/src/sio/gpio_hi_oe_xor.rs +++ b/src/sio/gpio_hi_oe_xor.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_hi_oe_xor(&mut self) -> GPIO_HI_OE_XOR_W { GPIO_HI_OE_XOR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output enable XOR @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_HI_OE_XOR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_hi_oe_xor::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OE_XOR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_out.rs b/src/sio/gpio_hi_out.rs index 8bdebed42..4bbc32ede 100644 --- a/src/sio/gpio_hi_out.rs +++ b/src/sio/gpio_hi_out.rs @@ -36,16 +36,6 @@ impl W { pub fn gpio_hi_out(&mut self) -> GPIO_HI_OUT_W { GPIO_HI_OUT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output value @@ -58,6 +48,7 @@ impl crate::RegisterSpec for GPIO_HI_OUT_SPEC { impl crate::Readable for GPIO_HI_OUT_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_hi_out::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_out_clr.rs b/src/sio/gpio_hi_out_clr.rs index 3167aaaff..83f98f24f 100644 --- a/src/sio/gpio_hi_out_clr.rs +++ b/src/sio/gpio_hi_out_clr.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_hi_out_clr(&mut self) -> GPIO_HI_OUT_CLR_W { GPIO_HI_OUT_CLR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output value clear @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_HI_OUT_CLR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_hi_out_clr::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_CLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_out_set.rs b/src/sio/gpio_hi_out_set.rs index a198f0367..f9b7d8e8d 100644 --- a/src/sio/gpio_hi_out_set.rs +++ b/src/sio/gpio_hi_out_set.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_hi_out_set(&mut self) -> GPIO_HI_OUT_SET_W { GPIO_HI_OUT_SET_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output value set @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_HI_OUT_SET_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_hi_out_set::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_SET_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_hi_out_xor.rs b/src/sio/gpio_hi_out_xor.rs index 44f13a264..791a410bd 100644 --- a/src/sio/gpio_hi_out_xor.rs +++ b/src/sio/gpio_hi_out_xor.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_hi_out_xor(&mut self) -> GPIO_HI_OUT_XOR_W { GPIO_HI_OUT_XOR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "QSPI output value XOR @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_HI_OUT_XOR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_hi_out_xor::W`](W) writer structure"] impl crate::Writable for GPIO_HI_OUT_XOR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_oe.rs b/src/sio/gpio_oe.rs index 7d66464e3..0856f430d 100644 --- a/src/sio/gpio_oe.rs +++ b/src/sio/gpio_oe.rs @@ -36,16 +36,6 @@ impl W { pub fn gpio_oe(&mut self) -> GPIO_OE_W { GPIO_OE_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output enable @@ -58,6 +48,7 @@ impl crate::RegisterSpec for GPIO_OE_SPEC { impl crate::Readable for GPIO_OE_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_oe::W`](W) writer structure"] impl crate::Writable for GPIO_OE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_oe_clr.rs b/src/sio/gpio_oe_clr.rs index ce2eb8bac..9fe86e678 100644 --- a/src/sio/gpio_oe_clr.rs +++ b/src/sio/gpio_oe_clr.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_oe_clr(&mut self) -> GPIO_OE_CLR_W { GPIO_OE_CLR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output enable clear @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_OE_CLR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_oe_clr::W`](W) writer structure"] impl crate::Writable for GPIO_OE_CLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_oe_set.rs b/src/sio/gpio_oe_set.rs index 5953c9116..f2adb3c2f 100644 --- a/src/sio/gpio_oe_set.rs +++ b/src/sio/gpio_oe_set.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_oe_set(&mut self) -> GPIO_OE_SET_W { GPIO_OE_SET_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output enable set @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_OE_SET_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_oe_set::W`](W) writer structure"] impl crate::Writable for GPIO_OE_SET_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_oe_xor.rs b/src/sio/gpio_oe_xor.rs index 30494a1f9..c45870cf6 100644 --- a/src/sio/gpio_oe_xor.rs +++ b/src/sio/gpio_oe_xor.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_oe_xor(&mut self) -> GPIO_OE_XOR_W { GPIO_OE_XOR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output enable XOR @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_OE_XOR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_oe_xor::W`](W) writer structure"] impl crate::Writable for GPIO_OE_XOR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_out.rs b/src/sio/gpio_out.rs index cec8379e9..77b14ae53 100644 --- a/src/sio/gpio_out.rs +++ b/src/sio/gpio_out.rs @@ -36,16 +36,6 @@ impl W { pub fn gpio_out(&mut self) -> GPIO_OUT_W { GPIO_OUT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output value @@ -58,6 +48,7 @@ impl crate::RegisterSpec for GPIO_OUT_SPEC { impl crate::Readable for GPIO_OUT_SPEC {} #[doc = "`write(|w| ..)` method takes [`gpio_out::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_out_clr.rs b/src/sio/gpio_out_clr.rs index 942992fa4..d854fc1a0 100644 --- a/src/sio/gpio_out_clr.rs +++ b/src/sio/gpio_out_clr.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_out_clr(&mut self) -> GPIO_OUT_CLR_W { GPIO_OUT_CLR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output value clear @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_OUT_CLR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_out_clr::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_CLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_out_set.rs b/src/sio/gpio_out_set.rs index dd29b7807..11b64976f 100644 --- a/src/sio/gpio_out_set.rs +++ b/src/sio/gpio_out_set.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_out_set(&mut self) -> GPIO_OUT_SET_W { GPIO_OUT_SET_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output value set @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_OUT_SET_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_out_set::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_SET_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/gpio_out_xor.rs b/src/sio/gpio_out_xor.rs index 0004711be..1e51f0029 100644 --- a/src/sio/gpio_out_xor.rs +++ b/src/sio/gpio_out_xor.rs @@ -9,16 +9,6 @@ impl W { pub fn gpio_out_xor(&mut self) -> GPIO_OUT_XOR_W { GPIO_OUT_XOR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "GPIO output value XOR @@ -29,6 +19,7 @@ impl crate::RegisterSpec for GPIO_OUT_XOR_SPEC { } #[doc = "`write(|w| ..)` method takes [`gpio_out_xor::W`](W) writer structure"] impl crate::Writable for GPIO_OUT_XOR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_accum0.rs b/src/sio/interp0_accum0.rs index 4a8d01566..ed7c47463 100644 --- a/src/sio/interp0_accum0.rs +++ b/src/sio/interp0_accum0.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to accumulator 0 You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP0_ACCUM0_SPEC { impl crate::Readable for INTERP0_ACCUM0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_accum0::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_accum0_add.rs b/src/sio/interp0_accum0_add.rs index cdfab107b..1addd12d8 100644 --- a/src/sio/interp0_accum0_add.rs +++ b/src/sio/interp0_accum0_add.rs @@ -20,16 +20,6 @@ impl W { pub fn interp0_accum0_add(&mut self) -> INTERP0_ACCUM0_ADD_W { INTERP0_ACCUM0_ADD_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). @@ -43,6 +33,7 @@ impl crate::RegisterSpec for INTERP0_ACCUM0_ADD_SPEC { impl crate::Readable for INTERP0_ACCUM0_ADD_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_accum0_add::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM0_ADD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_accum1.rs b/src/sio/interp0_accum1.rs index 3efc8830d..787d98c73 100644 --- a/src/sio/interp0_accum1.rs +++ b/src/sio/interp0_accum1.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to accumulator 1 You can [`read`](crate::generic::Reg::read) this register and get [`interp0_accum1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP0_ACCUM1_SPEC { impl crate::Readable for INTERP0_ACCUM1_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_accum1::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_accum1_add.rs b/src/sio/interp0_accum1_add.rs index 4deed624f..86ec6c6f5 100644 --- a/src/sio/interp0_accum1_add.rs +++ b/src/sio/interp0_accum1_add.rs @@ -20,16 +20,6 @@ impl W { pub fn interp0_accum1_add(&mut self) -> INTERP0_ACCUM1_ADD_W { INTERP0_ACCUM1_ADD_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). @@ -43,6 +33,7 @@ impl crate::RegisterSpec for INTERP0_ACCUM1_ADD_SPEC { impl crate::Readable for INTERP0_ACCUM1_ADD_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_accum1_add::W`](W) writer structure"] impl crate::Writable for INTERP0_ACCUM1_ADD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_base0.rs b/src/sio/interp0_base0.rs index 6f2514f9b..adb318c1d 100644 --- a/src/sio/interp0_base0.rs +++ b/src/sio/interp0_base0.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to BASE0 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP0_BASE0_SPEC { impl crate::Readable for INTERP0_BASE0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_base0::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_base1.rs b/src/sio/interp0_base1.rs index 33382997d..d22741585 100644 --- a/src/sio/interp0_base1.rs +++ b/src/sio/interp0_base1.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to BASE1 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP0_BASE1_SPEC { impl crate::Readable for INTERP0_BASE1_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_base1::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_base2.rs b/src/sio/interp0_base2.rs index d8c32973d..93931169f 100644 --- a/src/sio/interp0_base2.rs +++ b/src/sio/interp0_base2.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to BASE2 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp0_base2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp0_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP0_BASE2_SPEC { impl crate::Readable for INTERP0_BASE2_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_base2::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_base_1and0.rs b/src/sio/interp0_base_1and0.rs index 78e10e134..8f705a5da 100644 --- a/src/sio/interp0_base_1and0.rs +++ b/src/sio/interp0_base_1and0.rs @@ -5,18 +5,7 @@ impl core::fmt::Debug for crate::generic::Reg { write!(f, "(not readable)") } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. @@ -27,6 +16,7 @@ impl crate::RegisterSpec for INTERP0_BASE_1AND0_SPEC { } #[doc = "`write(|w| ..)` method takes [`interp0_base_1and0::W`](W) writer structure"] impl crate::Writable for INTERP0_BASE_1AND0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_ctrl_lane0.rs b/src/sio/interp0_ctrl_lane0.rs index aadb01109..e5d70135f 100644 --- a/src/sio/interp0_ctrl_lane0.rs +++ b/src/sio/interp0_ctrl_lane0.rs @@ -205,16 +205,6 @@ impl W { pub fn blend(&mut self) -> BLEND_W { BLEND_W::new(self, 21) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control register for lane 0 @@ -227,6 +217,7 @@ impl crate::RegisterSpec for INTERP0_CTRL_LANE0_SPEC { impl crate::Readable for INTERP0_CTRL_LANE0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane0::W`](W) writer structure"] impl crate::Writable for INTERP0_CTRL_LANE0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp0_ctrl_lane1.rs b/src/sio/interp0_ctrl_lane1.rs index dc55c9fb8..3f27fbab6 100644 --- a/src/sio/interp0_ctrl_lane1.rs +++ b/src/sio/interp0_ctrl_lane1.rs @@ -145,16 +145,6 @@ impl W { pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self, 19) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control register for lane 1 @@ -167,6 +157,7 @@ impl crate::RegisterSpec for INTERP0_CTRL_LANE1_SPEC { impl crate::Readable for INTERP0_CTRL_LANE1_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp0_ctrl_lane1::W`](W) writer structure"] impl crate::Writable for INTERP0_CTRL_LANE1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_accum0.rs b/src/sio/interp1_accum0.rs index f7ca0c157..fb71f4bbc 100644 --- a/src/sio/interp1_accum0.rs +++ b/src/sio/interp1_accum0.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to accumulator 0 You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP1_ACCUM0_SPEC { impl crate::Readable for INTERP1_ACCUM0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_accum0::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_accum0_add.rs b/src/sio/interp1_accum0_add.rs index 7986ef24d..98b58b1a9 100644 --- a/src/sio/interp1_accum0_add.rs +++ b/src/sio/interp1_accum0_add.rs @@ -20,16 +20,6 @@ impl W { pub fn interp1_accum0_add(&mut self) -> INTERP1_ACCUM0_ADD_W { INTERP1_ACCUM0_ADD_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). @@ -43,6 +33,7 @@ impl crate::RegisterSpec for INTERP1_ACCUM0_ADD_SPEC { impl crate::Readable for INTERP1_ACCUM0_ADD_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_accum0_add::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM0_ADD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_accum1.rs b/src/sio/interp1_accum1.rs index 3d3d57e02..cb4174a1c 100644 --- a/src/sio/interp1_accum1.rs +++ b/src/sio/interp1_accum1.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to accumulator 1 You can [`read`](crate::generic::Reg::read) this register and get [`interp1_accum1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_accum1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP1_ACCUM1_SPEC { impl crate::Readable for INTERP1_ACCUM1_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_accum1::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_accum1_add.rs b/src/sio/interp1_accum1_add.rs index f247ff515..7d4194fb6 100644 --- a/src/sio/interp1_accum1_add.rs +++ b/src/sio/interp1_accum1_add.rs @@ -20,16 +20,6 @@ impl W { pub fn interp1_accum1_add(&mut self) -> INTERP1_ACCUM1_ADD_W { INTERP1_ACCUM1_ADD_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). @@ -43,6 +33,7 @@ impl crate::RegisterSpec for INTERP1_ACCUM1_ADD_SPEC { impl crate::Readable for INTERP1_ACCUM1_ADD_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_accum1_add::W`](W) writer structure"] impl crate::Writable for INTERP1_ACCUM1_ADD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_base0.rs b/src/sio/interp1_base0.rs index 435d24a2c..91dc452e4 100644 --- a/src/sio/interp1_base0.rs +++ b/src/sio/interp1_base0.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to BASE0 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP1_BASE0_SPEC { impl crate::Readable for INTERP1_BASE0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_base0::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_base1.rs b/src/sio/interp1_base1.rs index 5c3fbf190..35c0e3e46 100644 --- a/src/sio/interp1_base1.rs +++ b/src/sio/interp1_base1.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to BASE1 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP1_BASE1_SPEC { impl crate::Readable for INTERP1_BASE1_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_base1::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_base2.rs b/src/sio/interp1_base2.rs index a34394125..38a7dc662 100644 --- a/src/sio/interp1_base2.rs +++ b/src/sio/interp1_base2.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Read/write access to BASE2 register. You can [`read`](crate::generic::Reg::read) this register and get [`interp1_base2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interp1_base2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for INTERP1_BASE2_SPEC { impl crate::Readable for INTERP1_BASE2_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_base2::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_base_1and0.rs b/src/sio/interp1_base_1and0.rs index 3319acf62..962e327e2 100644 --- a/src/sio/interp1_base_1and0.rs +++ b/src/sio/interp1_base_1and0.rs @@ -5,18 +5,7 @@ impl core::fmt::Debug for crate::generic::Reg { write!(f, "(not readable)") } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. @@ -27,6 +16,7 @@ impl crate::RegisterSpec for INTERP1_BASE_1AND0_SPEC { } #[doc = "`write(|w| ..)` method takes [`interp1_base_1and0::W`](W) writer structure"] impl crate::Writable for INTERP1_BASE_1AND0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_ctrl_lane0.rs b/src/sio/interp1_ctrl_lane0.rs index 6ccdc728e..f43f516e4 100644 --- a/src/sio/interp1_ctrl_lane0.rs +++ b/src/sio/interp1_ctrl_lane0.rs @@ -193,16 +193,6 @@ impl W { pub fn clamp(&mut self) -> CLAMP_W { CLAMP_W::new(self, 22) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control register for lane 0 @@ -215,6 +205,7 @@ impl crate::RegisterSpec for INTERP1_CTRL_LANE0_SPEC { impl crate::Readable for INTERP1_CTRL_LANE0_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_ctrl_lane0::W`](W) writer structure"] impl crate::Writable for INTERP1_CTRL_LANE0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/interp1_ctrl_lane1.rs b/src/sio/interp1_ctrl_lane1.rs index 9717d8ab1..288187fb8 100644 --- a/src/sio/interp1_ctrl_lane1.rs +++ b/src/sio/interp1_ctrl_lane1.rs @@ -145,16 +145,6 @@ impl W { pub fn force_msb(&mut self) -> FORCE_MSB_W { FORCE_MSB_W::new(self, 19) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control register for lane 1 @@ -167,6 +157,7 @@ impl crate::RegisterSpec for INTERP1_CTRL_LANE1_SPEC { impl crate::Readable for INTERP1_CTRL_LANE1_SPEC {} #[doc = "`write(|w| ..)` method takes [`interp1_ctrl_lane1::W`](W) writer structure"] impl crate::Writable for INTERP1_CTRL_LANE1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sio/spinlock.rs b/src/sio/spinlock.rs index 7cc2e13d7..f1d37fb24 100644 --- a/src/sio/spinlock.rs +++ b/src/sio/spinlock.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -41,6 +30,7 @@ impl crate::RegisterSpec for SPINLOCK_SPEC { impl crate::Readable for SPINLOCK_SPEC {} #[doc = "`write(|w| ..)` method takes [`spinlock::W`](W) writer structure"] impl crate::Writable for SPINLOCK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/spi0.rs b/src/spi0.rs index 34d1aa38b..50c0c5629 100644 --- a/src/spi0.rs +++ b/src/spi0.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { sspcr0: SSPCR0, sspcr1: SSPCR1, diff --git a/src/spi0/sspcpsr.rs b/src/spi0/sspcpsr.rs index cf374e389..faf3ebf27 100644 --- a/src/spi0/sspcpsr.rs +++ b/src/spi0/sspcpsr.rs @@ -20,16 +20,6 @@ impl W { pub fn cpsdvsr(&mut self) -> CPSDVSR_W { CPSDVSR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Clock prescale register, SSPCPSR on page 3-8 @@ -42,6 +32,7 @@ impl crate::RegisterSpec for SSPCPSR_SPEC { impl crate::Readable for SSPCPSR_SPEC {} #[doc = "`write(|w| ..)` method takes [`sspcpsr::W`](W) writer structure"] impl crate::Writable for SSPCPSR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/spi0/sspcr0.rs b/src/spi0/sspcr0.rs index 41028ddab..62df85ffd 100644 --- a/src/spi0/sspcr0.rs +++ b/src/spi0/sspcr0.rs @@ -6,8 +6,6 @@ pub type W = crate::W; pub type DSS_R = crate::FieldReader; #[doc = "Field `DSS` writer - Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data."] pub type DSS_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `FRF` reader - Frame format."] -pub type FRF_R = crate::FieldReader; #[doc = "Frame format. Value on reset: 0"] @@ -30,6 +28,8 @@ impl From for u8 { impl crate::FieldSpec for FRF_A { type Ux = u8; } +#[doc = "Field `FRF` reader - Frame format."] +pub type FRF_R = crate::FieldReader; impl FRF_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -150,16 +150,6 @@ impl W { pub fn scr(&mut self) -> SCR_W { SCR_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control register 0, SSPCR0 on page 3-4 @@ -172,6 +162,7 @@ impl crate::RegisterSpec for SSPCR0_SPEC { impl crate::Readable for SSPCR0_SPEC {} #[doc = "`write(|w| ..)` method takes [`sspcr0::W`](W) writer structure"] impl crate::Writable for SSPCR0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/spi0/sspcr1.rs b/src/spi0/sspcr1.rs index 25159ea4b..1d0f306b8 100644 --- a/src/spi0/sspcr1.rs +++ b/src/spi0/sspcr1.rs @@ -65,16 +65,6 @@ impl W { pub fn sod(&mut self) -> SOD_W { SOD_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control register 1, SSPCR1 on page 3-5 @@ -87,6 +77,7 @@ impl crate::RegisterSpec for SSPCR1_SPEC { impl crate::Readable for SSPCR1_SPEC {} #[doc = "`write(|w| ..)` method takes [`sspcr1::W`](W) writer structure"] impl crate::Writable for SSPCR1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/spi0/sspdmacr.rs b/src/spi0/sspdmacr.rs index 57cf721da..713ed08e8 100644 --- a/src/spi0/sspdmacr.rs +++ b/src/spi0/sspdmacr.rs @@ -35,16 +35,6 @@ impl W { pub fn txdmae(&mut self) -> TXDMAE_W { TXDMAE_W::new(self, 1) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA control register, SSPDMACR on page 3-12 @@ -57,6 +47,7 @@ impl crate::RegisterSpec for SSPDMACR_SPEC { impl crate::Readable for SSPDMACR_SPEC {} #[doc = "`write(|w| ..)` method takes [`sspdmacr::W`](W) writer structure"] impl crate::Writable for SSPDMACR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/spi0/sspdr.rs b/src/spi0/sspdr.rs index f3b7bf277..c438c31c6 100644 --- a/src/spi0/sspdr.rs +++ b/src/spi0/sspdr.rs @@ -20,16 +20,6 @@ impl W { pub fn data(&mut self) -> DATA_W { DATA_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Data register, SSPDR on page 3-6 @@ -42,6 +32,7 @@ impl crate::RegisterSpec for SSPDR_SPEC { impl crate::Readable for SSPDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`sspdr::W`](W) writer structure"] impl crate::Writable for SSPDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/spi0/sspicr.rs b/src/spi0/sspicr.rs index eff178e33..1f25518a8 100644 --- a/src/spi0/sspicr.rs +++ b/src/spi0/sspicr.rs @@ -35,16 +35,6 @@ impl W { pub fn rtic(&mut self) -> RTIC_W { RTIC_W::new(self, 1) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt clear register, SSPICR on page 3-11 @@ -57,6 +47,7 @@ impl crate::RegisterSpec for SSPICR_SPEC { impl crate::Readable for SSPICR_SPEC {} #[doc = "`write(|w| ..)` method takes [`sspicr::W`](W) writer structure"] impl crate::Writable for SSPICR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x03; } diff --git a/src/spi0/sspimsc.rs b/src/spi0/sspimsc.rs index 5da3d95f4..24c8f2d25 100644 --- a/src/spi0/sspimsc.rs +++ b/src/spi0/sspimsc.rs @@ -65,16 +65,6 @@ impl W { pub fn txim(&mut self) -> TXIM_W { TXIM_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt mask set or clear register, SSPIMSC on page 3-9 @@ -87,6 +77,7 @@ impl crate::RegisterSpec for SSPIMSC_SPEC { impl crate::Readable for SSPIMSC_SPEC {} #[doc = "`write(|w| ..)` method takes [`sspimsc::W`](W) writer structure"] impl crate::Writable for SSPIMSC_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/syscfg.rs b/src/syscfg.rs index d7e059593..06df3a0b0 100644 --- a/src/syscfg.rs +++ b/src/syscfg.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { proc0_nmi_mask: PROC0_NMI_MASK, proc1_nmi_mask: PROC1_NMI_MASK, diff --git a/src/syscfg/dbgforce.rs b/src/syscfg/dbgforce.rs index 57f1d23c8..5610506df 100644 --- a/src/syscfg/dbgforce.rs +++ b/src/syscfg/dbgforce.rs @@ -109,16 +109,6 @@ impl W { pub fn proc1_attach(&mut self) -> PROC1_ATTACH_W { PROC1_ATTACH_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Directly control the SWD debug port of either processor @@ -131,6 +121,7 @@ impl crate::RegisterSpec for DBGFORCE_SPEC { impl crate::Readable for DBGFORCE_SPEC {} #[doc = "`write(|w| ..)` method takes [`dbgforce::W`](W) writer structure"] impl crate::Writable for DBGFORCE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/syscfg/mempowerdown.rs b/src/syscfg/mempowerdown.rs index 91decf54a..255cb702f 100644 --- a/src/syscfg/mempowerdown.rs +++ b/src/syscfg/mempowerdown.rs @@ -125,16 +125,6 @@ impl W { pub fn rom(&mut self) -> ROM_W { ROM_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control power downs to memories. Set high to power down memories. Use with extreme caution @@ -148,6 +138,7 @@ impl crate::RegisterSpec for MEMPOWERDOWN_SPEC { impl crate::Readable for MEMPOWERDOWN_SPEC {} #[doc = "`write(|w| ..)` method takes [`mempowerdown::W`](W) writer structure"] impl crate::Writable for MEMPOWERDOWN_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/syscfg/proc0_nmi_mask.rs b/src/syscfg/proc0_nmi_mask.rs index 34d524f12..76d02c5ae 100644 --- a/src/syscfg/proc0_nmi_mask.rs +++ b/src/syscfg/proc0_nmi_mask.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Processor core 0 NMI source mask Set a bit high to enable NMI from that IRQ @@ -36,6 +25,7 @@ impl crate::RegisterSpec for PROC0_NMI_MASK_SPEC { impl crate::Readable for PROC0_NMI_MASK_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc0_nmi_mask::W`](W) writer structure"] impl crate::Writable for PROC0_NMI_MASK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/syscfg/proc1_nmi_mask.rs b/src/syscfg/proc1_nmi_mask.rs index 58cee8741..ca0b40bec 100644 --- a/src/syscfg/proc1_nmi_mask.rs +++ b/src/syscfg/proc1_nmi_mask.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ @@ -36,6 +25,7 @@ impl crate::RegisterSpec for PROC1_NMI_MASK_SPEC { impl crate::Readable for PROC1_NMI_MASK_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc1_nmi_mask::W`](W) writer structure"] impl crate::Writable for PROC1_NMI_MASK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/syscfg/proc_config.rs b/src/syscfg/proc_config.rs index d1bf72f1a..6358aff53 100644 --- a/src/syscfg/proc_config.rs +++ b/src/syscfg/proc_config.rs @@ -65,16 +65,6 @@ impl W { pub fn proc1_dap_instid(&mut self) -> PROC1_DAP_INSTID_W { PROC1_DAP_INSTID_W::new(self, 28) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Configuration for processors @@ -87,6 +77,7 @@ impl crate::RegisterSpec for PROC_CONFIG_SPEC { impl crate::Readable for PROC_CONFIG_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc_config::W`](W) writer structure"] impl crate::Writable for PROC_CONFIG_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/syscfg/proc_in_sync_bypass.rs b/src/syscfg/proc_in_sync_bypass.rs index 727cba8a1..52db7ddc6 100644 --- a/src/syscfg/proc_in_sync_bypass.rs +++ b/src/syscfg/proc_in_sync_bypass.rs @@ -20,16 +20,6 @@ impl W { pub fn proc_in_sync_bypass(&mut self) -> PROC_IN_SYNC_BYPASS_W { PROC_IN_SYNC_BYPASS_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -46,6 +36,7 @@ impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_SPEC { impl crate::Readable for PROC_IN_SYNC_BYPASS_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc_in_sync_bypass::W`](W) writer structure"] impl crate::Writable for PROC_IN_SYNC_BYPASS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/syscfg/proc_in_sync_bypass_hi.rs b/src/syscfg/proc_in_sync_bypass_hi.rs index 735083852..28e7a8072 100644 --- a/src/syscfg/proc_in_sync_bypass_hi.rs +++ b/src/syscfg/proc_in_sync_bypass_hi.rs @@ -22,16 +22,6 @@ impl W { ) -> PROC_IN_SYNC_BYPASS_HI_W { PROC_IN_SYNC_BYPASS_HI_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -48,6 +38,7 @@ impl crate::RegisterSpec for PROC_IN_SYNC_BYPASS_HI_SPEC { impl crate::Readable for PROC_IN_SYNC_BYPASS_HI_SPEC {} #[doc = "`write(|w| ..)` method takes [`proc_in_sync_bypass_hi::W`](W) writer structure"] impl crate::Writable for PROC_IN_SYNC_BYPASS_HI_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/sysinfo.rs b/src/sysinfo.rs index 3cba3722a..6396a522d 100644 --- a/src/sysinfo.rs +++ b/src/sysinfo.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { chip_id: CHIP_ID, platform: PLATFORM, diff --git a/src/tbman.rs b/src/tbman.rs index c5896b837..85ad7fd3e 100644 --- a/src/tbman.rs +++ b/src/tbman.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { platform: PLATFORM, } diff --git a/src/timer.rs b/src/timer.rs index 5dae46913..e61a6f28b 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { timehw: TIMEHW, timelw: TIMELW, diff --git a/src/timer/alarm0.rs b/src/timer/alarm0.rs index 2f8cc3085..f1e81b6ed 100644 --- a/src/timer/alarm0.rs +++ b/src/timer/alarm0.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can @@ -38,6 +27,7 @@ impl crate::RegisterSpec for ALARM0_SPEC { impl crate::Readable for ALARM0_SPEC {} #[doc = "`write(|w| ..)` method takes [`alarm0::W`](W) writer structure"] impl crate::Writable for ALARM0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/alarm1.rs b/src/timer/alarm1.rs index 937447ecc..777798520 100644 --- a/src/timer/alarm1.rs +++ b/src/timer/alarm1.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can @@ -38,6 +27,7 @@ impl crate::RegisterSpec for ALARM1_SPEC { impl crate::Readable for ALARM1_SPEC {} #[doc = "`write(|w| ..)` method takes [`alarm1::W`](W) writer structure"] impl crate::Writable for ALARM1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/alarm2.rs b/src/timer/alarm2.rs index 94b6a120c..fc9df4b3b 100644 --- a/src/timer/alarm2.rs +++ b/src/timer/alarm2.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can @@ -38,6 +27,7 @@ impl crate::RegisterSpec for ALARM2_SPEC { impl crate::Readable for ALARM2_SPEC {} #[doc = "`write(|w| ..)` method takes [`alarm2::W`](W) writer structure"] impl crate::Writable for ALARM2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/alarm3.rs b/src/timer/alarm3.rs index d844f89bb..1cfb87e31 100644 --- a/src/timer/alarm3.rs +++ b/src/timer/alarm3.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can @@ -38,6 +27,7 @@ impl crate::RegisterSpec for ALARM3_SPEC { impl crate::Readable for ALARM3_SPEC {} #[doc = "`write(|w| ..)` method takes [`alarm3::W`](W) writer structure"] impl crate::Writable for ALARM3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/armed.rs b/src/timer/armed.rs index e36807ee5..b904725f3 100644 --- a/src/timer/armed.rs +++ b/src/timer/armed.rs @@ -20,16 +20,6 @@ impl W { pub fn armed(&mut self) -> ARMED_W { ARMED_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. @@ -45,6 +35,7 @@ impl crate::RegisterSpec for ARMED_SPEC { impl crate::Readable for ARMED_SPEC {} #[doc = "`write(|w| ..)` method takes [`armed::W`](W) writer structure"] impl crate::Writable for ARMED_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; } diff --git a/src/timer/dbgpause.rs b/src/timer/dbgpause.rs index b22bbf768..d13345ae0 100644 --- a/src/timer/dbgpause.rs +++ b/src/timer/dbgpause.rs @@ -35,16 +35,6 @@ impl W { pub fn dbg1(&mut self) -> DBG1_W { DBG1_W::new(self, 2) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Set bits high to enable pause when the corresponding debug ports are active @@ -57,6 +47,7 @@ impl crate::RegisterSpec for DBGPAUSE_SPEC { impl crate::Readable for DBGPAUSE_SPEC {} #[doc = "`write(|w| ..)` method takes [`dbgpause::W`](W) writer structure"] impl crate::Writable for DBGPAUSE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/inte.rs b/src/timer/inte.rs index a06834b9c..585e887fb 100644 --- a/src/timer/inte.rs +++ b/src/timer/inte.rs @@ -65,16 +65,6 @@ impl W { pub fn alarm_3(&mut self) -> ALARM_3_W { ALARM_3_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable @@ -87,6 +77,7 @@ impl crate::RegisterSpec for INTE_SPEC { impl crate::Readable for INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/intf.rs b/src/timer/intf.rs index d37ddd954..6f93aeaf9 100644 --- a/src/timer/intf.rs +++ b/src/timer/intf.rs @@ -65,16 +65,6 @@ impl W { pub fn alarm_3(&mut self) -> ALARM_3_W { ALARM_3_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force @@ -87,6 +77,7 @@ impl crate::RegisterSpec for INTF_SPEC { impl crate::Readable for INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/intr.rs b/src/timer/intr.rs index 607b3c452..571158973 100644 --- a/src/timer/intr.rs +++ b/src/timer/intr.rs @@ -65,16 +65,6 @@ impl W { pub fn alarm_3(&mut self) -> ALARM_3_W { ALARM_3_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Raw Interrupts @@ -87,6 +77,7 @@ impl crate::RegisterSpec for INTR_SPEC { impl crate::Readable for INTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"] impl crate::Writable for INTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; } diff --git a/src/timer/pause.rs b/src/timer/pause.rs index bb7a2191a..754e0f3d9 100644 --- a/src/timer/pause.rs +++ b/src/timer/pause.rs @@ -20,16 +20,6 @@ impl W { pub fn pause(&mut self) -> PAUSE_W { PAUSE_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Set high to pause the timer @@ -42,6 +32,7 @@ impl crate::RegisterSpec for PAUSE_SPEC { impl crate::Readable for PAUSE_SPEC {} #[doc = "`write(|w| ..)` method takes [`pause::W`](W) writer structure"] impl crate::Writable for PAUSE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/timehw.rs b/src/timer/timehw.rs index 8675c104b..86dfb59ab 100644 --- a/src/timer/timehw.rs +++ b/src/timer/timehw.rs @@ -5,18 +5,7 @@ impl core::fmt::Debug for crate::generic::Reg { write!(f, "(not readable)") } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Write to bits 63:32 of time always write timelw before timehw @@ -27,6 +16,7 @@ impl crate::RegisterSpec for TIMEHW_SPEC { } #[doc = "`write(|w| ..)` method takes [`timehw::W`](W) writer structure"] impl crate::Writable for TIMEHW_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/timer/timelw.rs b/src/timer/timelw.rs index 98a6f8f8a..0ef1b5cb6 100644 --- a/src/timer/timelw.rs +++ b/src/timer/timelw.rs @@ -5,18 +5,7 @@ impl core::fmt::Debug for crate::generic::Reg { write!(f, "(not readable)") } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Write to bits 31:0 of time writes do not get copied to time until timehw is written @@ -27,6 +16,7 @@ impl crate::RegisterSpec for TIMELW_SPEC { } #[doc = "`write(|w| ..)` method takes [`timelw::W`](W) writer structure"] impl crate::Writable for TIMELW_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0.rs b/src/uart0.rs index f5be2b3d1..fd19a9339 100644 --- a/src/uart0.rs +++ b/src/uart0.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { uartdr: UARTDR, uartrsr: UARTRSR, diff --git a/src/uart0/uartcr.rs b/src/uart0/uartcr.rs index cb0117b8c..dae084b70 100644 --- a/src/uart0/uartcr.rs +++ b/src/uart0/uartcr.rs @@ -185,16 +185,6 @@ impl W { pub fn ctsen(&mut self) -> CTSEN_W { CTSEN_W::new(self, 15) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control Register, UARTCR @@ -207,6 +197,7 @@ impl crate::RegisterSpec for UARTCR_SPEC { impl crate::Readable for UARTCR_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartcr::W`](W) writer structure"] impl crate::Writable for UARTCR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartdmacr.rs b/src/uart0/uartdmacr.rs index d3103453f..b9507f10d 100644 --- a/src/uart0/uartdmacr.rs +++ b/src/uart0/uartdmacr.rs @@ -50,16 +50,6 @@ impl W { pub fn dmaonerr(&mut self) -> DMAONERR_W { DMAONERR_W::new(self, 2) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA Control Register, UARTDMACR @@ -72,6 +62,7 @@ impl crate::RegisterSpec for UARTDMACR_SPEC { impl crate::Readable for UARTDMACR_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartdmacr::W`](W) writer structure"] impl crate::Writable for UARTDMACR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartdr.rs b/src/uart0/uartdr.rs index 24f8f95eb..536a5856a 100644 --- a/src/uart0/uartdr.rs +++ b/src/uart0/uartdr.rs @@ -48,16 +48,6 @@ impl W { pub fn data(&mut self) -> DATA_W { DATA_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Data Register, UARTDR @@ -70,6 +60,7 @@ impl crate::RegisterSpec for UARTDR_SPEC { impl crate::Readable for UARTDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartdr::W`](W) writer structure"] impl crate::Writable for UARTDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartfbrd.rs b/src/uart0/uartfbrd.rs index 8bc1b224f..b3ff61846 100644 --- a/src/uart0/uartfbrd.rs +++ b/src/uart0/uartfbrd.rs @@ -20,16 +20,6 @@ impl W { pub fn baud_divfrac(&mut self) -> BAUD_DIVFRAC_W { BAUD_DIVFRAC_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Fractional Baud Rate Register, UARTFBRD @@ -42,6 +32,7 @@ impl crate::RegisterSpec for UARTFBRD_SPEC { impl crate::Readable for UARTFBRD_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartfbrd::W`](W) writer structure"] impl crate::Writable for UARTFBRD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartibrd.rs b/src/uart0/uartibrd.rs index e5f490d35..737df2372 100644 --- a/src/uart0/uartibrd.rs +++ b/src/uart0/uartibrd.rs @@ -20,16 +20,6 @@ impl W { pub fn baud_divint(&mut self) -> BAUD_DIVINT_W { BAUD_DIVINT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Integer Baud Rate Register, UARTIBRD @@ -42,6 +32,7 @@ impl crate::RegisterSpec for UARTIBRD_SPEC { impl crate::Readable for UARTIBRD_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartibrd::W`](W) writer structure"] impl crate::Writable for UARTIBRD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uarticr.rs b/src/uart0/uarticr.rs index 691d94e14..4102b4406 100644 --- a/src/uart0/uarticr.rs +++ b/src/uart0/uarticr.rs @@ -170,16 +170,6 @@ impl W { pub fn oeic(&mut self) -> OEIC_W { OEIC_W::new(self, 10) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Clear Register, UARTICR @@ -192,6 +182,7 @@ impl crate::RegisterSpec for UARTICR_SPEC { impl crate::Readable for UARTICR_SPEC {} #[doc = "`write(|w| ..)` method takes [`uarticr::W`](W) writer structure"] impl crate::Writable for UARTICR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07ff; } diff --git a/src/uart0/uartifls.rs b/src/uart0/uartifls.rs index e38d8e965..beb565e1e 100644 --- a/src/uart0/uartifls.rs +++ b/src/uart0/uartifls.rs @@ -35,16 +35,6 @@ impl W { pub fn rxiflsel(&mut self) -> RXIFLSEL_W { RXIFLSEL_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt FIFO Level Select Register, UARTIFLS @@ -57,6 +47,7 @@ impl crate::RegisterSpec for UARTIFLS_SPEC { impl crate::Readable for UARTIFLS_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartifls::W`](W) writer structure"] impl crate::Writable for UARTIFLS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartilpr.rs b/src/uart0/uartilpr.rs index c7eb5dff7..e8568c88b 100644 --- a/src/uart0/uartilpr.rs +++ b/src/uart0/uartilpr.rs @@ -20,16 +20,6 @@ impl W { pub fn ilpdvsr(&mut self) -> ILPDVSR_W { ILPDVSR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "IrDA Low-Power Counter Register, UARTILPR @@ -42,6 +32,7 @@ impl crate::RegisterSpec for UARTILPR_SPEC { impl crate::Readable for UARTILPR_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartilpr::W`](W) writer structure"] impl crate::Writable for UARTILPR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartimsc.rs b/src/uart0/uartimsc.rs index 47a30f5d3..e34234078 100644 --- a/src/uart0/uartimsc.rs +++ b/src/uart0/uartimsc.rs @@ -170,16 +170,6 @@ impl W { pub fn oeim(&mut self) -> OEIM_W { OEIM_W::new(self, 10) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Mask Set/Clear Register, UARTIMSC @@ -192,6 +182,7 @@ impl crate::RegisterSpec for UARTIMSC_SPEC { impl crate::Readable for UARTIMSC_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartimsc::W`](W) writer structure"] impl crate::Writable for UARTIMSC_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartlcr_h.rs b/src/uart0/uartlcr_h.rs index 866449e7f..f06de8392 100644 --- a/src/uart0/uartlcr_h.rs +++ b/src/uart0/uartlcr_h.rs @@ -110,16 +110,6 @@ impl W { pub fn sps(&mut self) -> SPS_W { SPS_W::new(self, 7) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Line Control Register, UARTLCR_H @@ -132,6 +122,7 @@ impl crate::RegisterSpec for UARTLCR_H_SPEC { impl crate::Readable for UARTLCR_H_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartlcr_h::W`](W) writer structure"] impl crate::Writable for UARTLCR_H_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/uart0/uartrsr.rs b/src/uart0/uartrsr.rs index faabb74b6..cf629b0cb 100644 --- a/src/uart0/uartrsr.rs +++ b/src/uart0/uartrsr.rs @@ -65,16 +65,6 @@ impl W { pub fn oe(&mut self) -> OE_W { OE_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Receive Status Register/Error Clear Register, UARTRSR/UARTECR @@ -87,6 +77,7 @@ impl crate::RegisterSpec for UARTRSR_SPEC { impl crate::Readable for UARTRSR_SPEC {} #[doc = "`write(|w| ..)` method takes [`uartrsr::W`](W) writer structure"] impl crate::Writable for UARTRSR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f; } diff --git a/src/usbctrl_dpram.rs b/src/usbctrl_dpram.rs index 9f73aad1e..d0daf7a2a 100644 --- a/src/usbctrl_dpram.rs +++ b/src/usbctrl_dpram.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { setup_packet_low: SETUP_PACKET_LOW, setup_packet_high: SETUP_PACKET_HIGH, diff --git a/src/usbctrl_dpram/ep_buffer_control.rs b/src/usbctrl_dpram/ep_buffer_control.rs index c8aedb640..c977f2907 100644 --- a/src/usbctrl_dpram/ep_buffer_control.rs +++ b/src/usbctrl_dpram/ep_buffer_control.rs @@ -38,9 +38,6 @@ pub type LENGTH_1_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; pub type AVAILABLE_1_R = crate::BitReader; #[doc = "Field `AVAILABLE_1` writer - Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back."] pub type AVAILABLE_1_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. - For a non Isochronous endpoint the offset is always 64 bytes."] -pub type DOUBLE_BUFFER_ISO_OFFSET_R = crate::FieldReader; #[doc = "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. @@ -66,6 +63,9 @@ impl From for u8 { impl crate::FieldSpec for DOUBLE_BUFFER_ISO_OFFSET_A { type Ux = u8; } +#[doc = "Field `DOUBLE_BUFFER_ISO_OFFSET` reader - The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. + For a non Isochronous endpoint the offset is always 64 bytes."] +pub type DOUBLE_BUFFER_ISO_OFFSET_R = crate::FieldReader; impl DOUBLE_BUFFER_ISO_OFFSET_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -291,16 +291,6 @@ impl W { pub fn full_1(&mut self) -> FULL_1_W { FULL_1_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "- @@ -313,6 +303,7 @@ impl crate::RegisterSpec for EP_BUFFER_CONTROL_SPEC { impl crate::Readable for EP_BUFFER_CONTROL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ep_buffer_control::W`](W) writer structure"] impl crate::Writable for EP_BUFFER_CONTROL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_dpram/ep_control.rs b/src/usbctrl_dpram/ep_control.rs index 3e2c84d6f..ffaae0931 100644 --- a/src/usbctrl_dpram/ep_control.rs +++ b/src/usbctrl_dpram/ep_control.rs @@ -18,8 +18,6 @@ pub type HOST_POLL_INTERVAL_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; pub type INTERRUPT_ON_STALL_R = crate::BitReader; #[doc = "Field `INTERRUPT_ON_STALL` writer - Trigger an interrupt if a STALL is sent. Intended for debug only."] pub type INTERRUPT_ON_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ENDPOINT_TYPE` reader - "] -pub type ENDPOINT_TYPE_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for ENDPOINT_TYPE_A { type Ux = u8; } +#[doc = "Field `ENDPOINT_TYPE` reader - "] +pub type ENDPOINT_TYPE_R = crate::FieldReader; impl ENDPOINT_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -223,16 +223,6 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "- @@ -245,6 +235,7 @@ impl crate::RegisterSpec for EP_CONTROL_SPEC { impl crate::Readable for EP_CONTROL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ep_control::W`](W) writer structure"] impl crate::Writable for EP_CONTROL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_dpram/epx_control.rs b/src/usbctrl_dpram/epx_control.rs index 2a2bfb25f..f045155f7 100644 --- a/src/usbctrl_dpram/epx_control.rs +++ b/src/usbctrl_dpram/epx_control.rs @@ -14,8 +14,6 @@ pub type INTERRUPT_ON_NAK_W<'a, REG> = crate::BitWriter<'a, REG>; pub type INTERRUPT_ON_STALL_R = crate::BitReader; #[doc = "Field `INTERRUPT_ON_STALL` writer - Trigger an interrupt if a STALL is sent. Intended for debug only."] pub type INTERRUPT_ON_STALL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `ENDPOINT_TYPE` reader - "] -pub type ENDPOINT_TYPE_R = crate::FieldReader; #[doc = " Value on reset: 0"] @@ -40,6 +38,8 @@ impl From for u8 { impl crate::FieldSpec for ENDPOINT_TYPE_A { type Ux = u8; } +#[doc = "Field `ENDPOINT_TYPE` reader - "] +pub type ENDPOINT_TYPE_R = crate::FieldReader; impl ENDPOINT_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -208,16 +208,6 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "EPx Control (Host-mode only!) @@ -230,6 +220,7 @@ impl crate::RegisterSpec for EPX_CONTROL_SPEC { impl crate::Readable for EPX_CONTROL_SPEC {} #[doc = "`write(|w| ..)` method takes [`epx_control::W`](W) writer structure"] impl crate::Writable for EPX_CONTROL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_dpram/setup_packet_high.rs b/src/usbctrl_dpram/setup_packet_high.rs index 12b68f0cf..277833734 100644 --- a/src/usbctrl_dpram/setup_packet_high.rs +++ b/src/usbctrl_dpram/setup_packet_high.rs @@ -35,16 +35,6 @@ impl W { pub fn wlength(&mut self) -> WLENGTH_W { WLENGTH_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bytes 4-7 of the setup packet from the host. @@ -57,6 +47,7 @@ impl crate::RegisterSpec for SETUP_PACKET_HIGH_SPEC { impl crate::Readable for SETUP_PACKET_HIGH_SPEC {} #[doc = "`write(|w| ..)` method takes [`setup_packet_high::W`](W) writer structure"] impl crate::Writable for SETUP_PACKET_HIGH_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_dpram/setup_packet_low.rs b/src/usbctrl_dpram/setup_packet_low.rs index 7c6ece453..feac492d8 100644 --- a/src/usbctrl_dpram/setup_packet_low.rs +++ b/src/usbctrl_dpram/setup_packet_low.rs @@ -50,16 +50,6 @@ impl W { pub fn wvalue(&mut self) -> WVALUE_W { WVALUE_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Bytes 0-3 of the SETUP packet from the host. @@ -72,6 +62,7 @@ impl crate::RegisterSpec for SETUP_PACKET_LOW_SPEC { impl crate::Readable for SETUP_PACKET_LOW_SPEC {} #[doc = "`write(|w| ..)` method takes [`setup_packet_low::W`](W) writer structure"] impl crate::Writable for SETUP_PACKET_LOW_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs.rs b/src/usbctrl_regs.rs index 565c92e93..621027c35 100644 --- a/src/usbctrl_regs.rs +++ b/src/usbctrl_regs.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { addr_endp: ADDR_ENDP, host_addr_endp: [HOST_ADDR_ENDP; 15], diff --git a/src/usbctrl_regs/addr_endp.rs b/src/usbctrl_regs/addr_endp.rs index 3b6e3a30e..e69f85ebb 100644 --- a/src/usbctrl_regs/addr_endp.rs +++ b/src/usbctrl_regs/addr_endp.rs @@ -35,16 +35,6 @@ impl W { pub fn endpoint(&mut self) -> ENDPOINT_W { ENDPOINT_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Device address and endpoint control @@ -57,6 +47,7 @@ impl crate::RegisterSpec for ADDR_ENDP_SPEC { impl crate::Readable for ADDR_ENDP_SPEC {} #[doc = "`write(|w| ..)` method takes [`addr_endp::W`](W) writer structure"] impl crate::Writable for ADDR_ENDP_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/buff_status.rs b/src/usbctrl_regs/buff_status.rs index 256be55f3..5a7a8f5b3 100644 --- a/src/usbctrl_regs/buff_status.rs +++ b/src/usbctrl_regs/buff_status.rs @@ -485,16 +485,6 @@ impl W { pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. @@ -507,6 +497,7 @@ impl crate::RegisterSpec for BUFF_STATUS_SPEC { impl crate::Readable for BUFF_STATUS_SPEC {} #[doc = "`write(|w| ..)` method takes [`buff_status::W`](W) writer structure"] impl crate::Writable for BUFF_STATUS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; } diff --git a/src/usbctrl_regs/ep_abort.rs b/src/usbctrl_regs/ep_abort.rs index ab1f404e7..597ae38ad 100644 --- a/src/usbctrl_regs/ep_abort.rs +++ b/src/usbctrl_regs/ep_abort.rs @@ -485,16 +485,6 @@ impl W { pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. @@ -507,6 +497,7 @@ impl crate::RegisterSpec for EP_ABORT_SPEC { impl crate::Readable for EP_ABORT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ep_abort::W`](W) writer structure"] impl crate::Writable for EP_ABORT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/ep_abort_done.rs b/src/usbctrl_regs/ep_abort_done.rs index b1a675a0f..730066382 100644 --- a/src/usbctrl_regs/ep_abort_done.rs +++ b/src/usbctrl_regs/ep_abort_done.rs @@ -485,16 +485,6 @@ impl W { pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. @@ -507,6 +497,7 @@ impl crate::RegisterSpec for EP_ABORT_DONE_SPEC { impl crate::Readable for EP_ABORT_DONE_SPEC {} #[doc = "`write(|w| ..)` method takes [`ep_abort_done::W`](W) writer structure"] impl crate::Writable for EP_ABORT_DONE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; } diff --git a/src/usbctrl_regs/ep_stall_arm.rs b/src/usbctrl_regs/ep_stall_arm.rs index 2bacd6d00..07f33ae92 100644 --- a/src/usbctrl_regs/ep_stall_arm.rs +++ b/src/usbctrl_regs/ep_stall_arm.rs @@ -35,16 +35,6 @@ impl W { pub fn ep0_out(&mut self) -> EP0_OUT_W { EP0_OUT_W::new(self, 1) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. @@ -57,6 +47,7 @@ impl crate::RegisterSpec for EP_STALL_ARM_SPEC { impl crate::Readable for EP_STALL_ARM_SPEC {} #[doc = "`write(|w| ..)` method takes [`ep_stall_arm::W`](W) writer structure"] impl crate::Writable for EP_STALL_ARM_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/ep_status_stall_nak.rs b/src/usbctrl_regs/ep_status_stall_nak.rs index c878fb632..6458a1cf6 100644 --- a/src/usbctrl_regs/ep_status_stall_nak.rs +++ b/src/usbctrl_regs/ep_status_stall_nak.rs @@ -485,16 +485,6 @@ impl W { pub fn ep15_out(&mut self) -> EP15_OUT_W { EP15_OUT_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. @@ -507,6 +497,7 @@ impl crate::RegisterSpec for EP_STATUS_STALL_NAK_SPEC { impl crate::Readable for EP_STATUS_STALL_NAK_SPEC {} #[doc = "`write(|w| ..)` method takes [`ep_status_stall_nak::W`](W) writer structure"] impl crate::Writable for EP_STATUS_STALL_NAK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff_ffff; } diff --git a/src/usbctrl_regs/host_addr_endp.rs b/src/usbctrl_regs/host_addr_endp.rs index 7d17e9016..98e813c05 100644 --- a/src/usbctrl_regs/host_addr_endp.rs +++ b/src/usbctrl_regs/host_addr_endp.rs @@ -65,16 +65,6 @@ impl W { pub fn intep_preamble(&mut self) -> INTEP_PREAMBLE_W { INTEP_PREAMBLE_W::new(self, 26) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt endpoints. Only valid in HOST mode. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for HOST_ADDR_ENDP_SPEC { impl crate::Readable for HOST_ADDR_ENDP_SPEC {} #[doc = "`write(|w| ..)` method takes [`host_addr_endp::W`](W) writer structure"] impl crate::Writable for HOST_ADDR_ENDP_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/int_ep_ctrl.rs b/src/usbctrl_regs/int_ep_ctrl.rs index d23ecd2c0..9a2797a76 100644 --- a/src/usbctrl_regs/int_ep_ctrl.rs +++ b/src/usbctrl_regs/int_ep_ctrl.rs @@ -20,16 +20,6 @@ impl W { pub fn int_ep_active(&mut self) -> INT_EP_ACTIVE_W { INT_EP_ACTIVE_W::new(self, 1) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "interrupt endpoint control register @@ -42,6 +32,7 @@ impl crate::RegisterSpec for INT_EP_CTRL_SPEC { impl crate::Readable for INT_EP_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`int_ep_ctrl::W`](W) writer structure"] impl crate::Writable for INT_EP_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/inte.rs b/src/usbctrl_regs/inte.rs index 964b40492..2bd0946d8 100644 --- a/src/usbctrl_regs/inte.rs +++ b/src/usbctrl_regs/inte.rs @@ -305,16 +305,6 @@ impl W { pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W { EP_STALL_NAK_W::new(self, 19) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Enable @@ -327,6 +317,7 @@ impl crate::RegisterSpec for INTE_SPEC { impl crate::Readable for INTE_SPEC {} #[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"] impl crate::Writable for INTE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/intf.rs b/src/usbctrl_regs/intf.rs index d5e9e8912..3a5fb3f64 100644 --- a/src/usbctrl_regs/intf.rs +++ b/src/usbctrl_regs/intf.rs @@ -305,16 +305,6 @@ impl W { pub fn ep_stall_nak(&mut self) -> EP_STALL_NAK_W { EP_STALL_NAK_W::new(self, 19) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt Force @@ -327,6 +317,7 @@ impl crate::RegisterSpec for INTF_SPEC { impl crate::Readable for INTF_SPEC {} #[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"] impl crate::Writable for INTF_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/main_ctrl.rs b/src/usbctrl_regs/main_ctrl.rs index ea1ee6d15..65d7bd8c9 100644 --- a/src/usbctrl_regs/main_ctrl.rs +++ b/src/usbctrl_regs/main_ctrl.rs @@ -50,16 +50,6 @@ impl W { pub fn sim_timing(&mut self) -> SIM_TIMING_W { SIM_TIMING_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Main control register @@ -72,6 +62,7 @@ impl crate::RegisterSpec for MAIN_CTRL_SPEC { impl crate::Readable for MAIN_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`main_ctrl::W`](W) writer structure"] impl crate::Writable for MAIN_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/nak_poll.rs b/src/usbctrl_regs/nak_poll.rs index 6f49dd4e9..d132486dc 100644 --- a/src/usbctrl_regs/nak_poll.rs +++ b/src/usbctrl_regs/nak_poll.rs @@ -35,16 +35,6 @@ impl W { pub fn delay_fs(&mut self) -> DELAY_FS_W { DELAY_FS_W::new(self, 16) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. @@ -57,6 +47,7 @@ impl crate::RegisterSpec for NAK_POLL_SPEC { impl crate::Readable for NAK_POLL_SPEC {} #[doc = "`write(|w| ..)` method takes [`nak_poll::W`](W) writer structure"] impl crate::Writable for NAK_POLL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/sie_ctrl.rs b/src/usbctrl_regs/sie_ctrl.rs index 63d266320..c49bffb7c 100644 --- a/src/usbctrl_regs/sie_ctrl.rs +++ b/src/usbctrl_regs/sie_ctrl.rs @@ -365,16 +365,6 @@ impl W { pub fn ep0_int_stall(&mut self) -> EP0_INT_STALL_W { EP0_INT_STALL_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "SIE control register @@ -387,6 +377,7 @@ impl crate::RegisterSpec for SIE_CTRL_SPEC { impl crate::Readable for SIE_CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`sie_ctrl::W`](W) writer structure"] impl crate::Writable for SIE_CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/sie_status.rs b/src/usbctrl_regs/sie_status.rs index 3be4cdc8e..56bea6d3d 100644 --- a/src/usbctrl_regs/sie_status.rs +++ b/src/usbctrl_regs/sie_status.rs @@ -4,8 +4,6 @@ pub type R = crate::R; pub type W = crate::W; #[doc = "Field `VBUS_DETECTED` reader - Device: VBUS Detected"] pub type VBUS_DETECTED_R = crate::BitReader; -#[doc = "Field `LINE_STATE` reader - USB bus line state"] -pub type LINE_STATE_R = crate::FieldReader; #[doc = "USB bus line state Value on reset: 0"] @@ -30,6 +28,8 @@ impl From for u8 { impl crate::FieldSpec for LINE_STATE_A { type Ux = u8; } +#[doc = "Field `LINE_STATE` reader - USB bus line state"] +pub type LINE_STATE_R = crate::FieldReader; impl LINE_STATE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -372,16 +372,6 @@ impl W { pub fn data_seq_error(&mut self) -> DATA_SEQ_ERROR_W { DATA_SEQ_ERROR_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "SIE status register @@ -394,6 +384,7 @@ impl crate::RegisterSpec for SIE_STATUS_SPEC { impl crate::Readable for SIE_STATUS_SPEC {} #[doc = "`write(|w| ..)` method takes [`sie_status::W`](W) writer structure"] impl crate::Writable for SIE_STATUS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xff0f_0b10; } diff --git a/src/usbctrl_regs/sof_wr.rs b/src/usbctrl_regs/sof_wr.rs index fb530bd84..e5f59e1fe 100644 --- a/src/usbctrl_regs/sof_wr.rs +++ b/src/usbctrl_regs/sof_wr.rs @@ -9,16 +9,6 @@ impl W { pub fn count(&mut self) -> COUNT_W { COUNT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. @@ -29,6 +19,7 @@ impl crate::RegisterSpec for SOF_WR_SPEC { } #[doc = "`write(|w| ..)` method takes [`sof_wr::W`](W) writer structure"] impl crate::Writable for SOF_WR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/usb_muxing.rs b/src/usbctrl_regs/usb_muxing.rs index 58b8c8524..7b5b1c9ae 100644 --- a/src/usbctrl_regs/usb_muxing.rs +++ b/src/usbctrl_regs/usb_muxing.rs @@ -65,16 +65,6 @@ impl W { pub fn softcon(&mut self) -> SOFTCON_W { SOFTCON_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Where to connect the USB controller. Should be to_phy by default. @@ -87,6 +77,7 @@ impl crate::RegisterSpec for USB_MUXING_SPEC { impl crate::Readable for USB_MUXING_SPEC {} #[doc = "`write(|w| ..)` method takes [`usb_muxing::W`](W) writer structure"] impl crate::Writable for USB_MUXING_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/usb_pwr.rs b/src/usbctrl_regs/usb_pwr.rs index 6041a8a4c..18c2502cc 100644 --- a/src/usbctrl_regs/usb_pwr.rs +++ b/src/usbctrl_regs/usb_pwr.rs @@ -95,16 +95,6 @@ impl W { pub fn overcurr_detect_en(&mut self) -> OVERCURR_DETECT_EN_W { OVERCURR_DETECT_EN_W::new(self, 5) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. @@ -117,6 +107,7 @@ impl crate::RegisterSpec for USB_PWR_SPEC { impl crate::Readable for USB_PWR_SPEC {} #[doc = "`write(|w| ..)` method takes [`usb_pwr::W`](W) writer structure"] impl crate::Writable for USB_PWR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/usbphy_direct.rs b/src/usbctrl_regs/usbphy_direct.rs index 20425d935..92262e905 100644 --- a/src/usbctrl_regs/usbphy_direct.rs +++ b/src/usbctrl_regs/usbphy_direct.rs @@ -288,16 +288,6 @@ impl W { pub fn tx_diffmode(&mut self) -> TX_DIFFMODE_W { TX_DIFFMODE_W::new(self, 15) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. @@ -310,6 +300,7 @@ impl crate::RegisterSpec for USBPHY_DIRECT_SPEC { impl crate::Readable for USBPHY_DIRECT_SPEC {} #[doc = "`write(|w| ..)` method takes [`usbphy_direct::W`](W) writer structure"] impl crate::Writable for USBPHY_DIRECT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/usbphy_direct_override.rs b/src/usbctrl_regs/usbphy_direct_override.rs index 0a5189017..f0e4ede99 100644 --- a/src/usbctrl_regs/usbphy_direct_override.rs +++ b/src/usbctrl_regs/usbphy_direct_override.rs @@ -231,16 +231,6 @@ impl W { ) -> TX_DIFFMODE_OVERRIDE_EN_W { TX_DIFFMODE_OVERRIDE_EN_W::new(self, 15) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Override enable for each control in usbphy_direct @@ -253,6 +243,7 @@ impl crate::RegisterSpec for USBPHY_DIRECT_OVERRIDE_SPEC { impl crate::Readable for USBPHY_DIRECT_OVERRIDE_SPEC {} #[doc = "`write(|w| ..)` method takes [`usbphy_direct_override::W`](W) writer structure"] impl crate::Writable for USBPHY_DIRECT_OVERRIDE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/usbctrl_regs/usbphy_trim.rs b/src/usbctrl_regs/usbphy_trim.rs index 94b233bc1..072f3d20d 100644 --- a/src/usbctrl_regs/usbphy_trim.rs +++ b/src/usbctrl_regs/usbphy_trim.rs @@ -51,16 +51,6 @@ impl W { pub fn dm_pulldn_trim(&mut self) -> DM_PULLDN_TRIM_W { DM_PULLDN_TRIM_W::new(self, 8) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Used to adjust trim values of USB phy pull down resistors. @@ -73,6 +63,7 @@ impl crate::RegisterSpec for USBPHY_TRIM_SPEC { impl crate::Readable for USBPHY_TRIM_SPEC {} #[doc = "`write(|w| ..)` method takes [`usbphy_trim::W`](W) writer structure"] impl crate::Writable for USBPHY_TRIM_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/vreg_and_chip_reset.rs b/src/vreg_and_chip_reset.rs index 99509b120..89f9ef0fb 100644 --- a/src/vreg_and_chip_reset.rs +++ b/src/vreg_and_chip_reset.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { vreg: VREG, bod: BOD, diff --git a/src/vreg_and_chip_reset/bod.rs b/src/vreg_and_chip_reset/bod.rs index 831ca941a..ca8451f8e 100644 --- a/src/vreg_and_chip_reset/bod.rs +++ b/src/vreg_and_chip_reset/bod.rs @@ -103,16 +103,6 @@ impl W { pub fn vsel(&mut self) -> VSEL_W { VSEL_W::new(self, 4) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "brown-out detection control @@ -125,6 +115,7 @@ impl crate::RegisterSpec for BOD_SPEC { impl crate::Readable for BOD_SPEC {} #[doc = "`write(|w| ..)` method takes [`bod::W`](W) writer structure"] impl crate::Writable for BOD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/vreg_and_chip_reset/chip_reset.rs b/src/vreg_and_chip_reset/chip_reset.rs index 850bf94eb..f8d0ef6f2 100644 --- a/src/vreg_and_chip_reset/chip_reset.rs +++ b/src/vreg_and_chip_reset/chip_reset.rs @@ -49,16 +49,6 @@ impl W { pub fn psm_restart_flag(&mut self) -> PSM_RESTART_FLAG_W { PSM_RESTART_FLAG_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Chip reset control and status @@ -71,6 +61,7 @@ impl crate::RegisterSpec for CHIP_RESET_SPEC { impl crate::Readable for CHIP_RESET_SPEC {} #[doc = "`write(|w| ..)` method takes [`chip_reset::W`](W) writer structure"] impl crate::Writable for CHIP_RESET_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0100_0000; } diff --git a/src/vreg_and_chip_reset/vreg.rs b/src/vreg_and_chip_reset/vreg.rs index 44b3d1e4e..fe1362f68 100644 --- a/src/vreg_and_chip_reset/vreg.rs +++ b/src/vreg_and_chip_reset/vreg.rs @@ -14,8 +14,6 @@ pub type HIZ_R = crate::BitReader; #[doc = "Field `HIZ` writer - high impedance mode select 0=not in high impedance mode, 1=in high impedance mode"] pub type HIZ_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `VSEL` reader - Output voltage select for on-chip voltage regulator."] -pub type VSEL_R = crate::FieldReader; #[doc = "Output voltage select for on-chip voltage regulator. Value on reset: 11"] @@ -54,6 +52,8 @@ impl From for u8 { impl crate::FieldSpec for VSEL_A { type Ux = u8; } +#[doc = "Field `VSEL` reader - Output voltage select for on-chip voltage regulator."] +pub type VSEL_R = crate::FieldReader; impl VSEL_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -241,16 +241,6 @@ impl W { pub fn vsel(&mut self) -> VSEL_W { VSEL_W::new(self, 4) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Voltage regulator control and status @@ -263,6 +253,7 @@ impl crate::RegisterSpec for VREG_SPEC { impl crate::Readable for VREG_SPEC {} #[doc = "`write(|w| ..)` method takes [`vreg::W`](W) writer structure"] impl crate::Writable for VREG_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog.rs b/src/watchdog.rs index a53abde04..1be794984 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ctrl: CTRL, load: LOAD, diff --git a/src/watchdog/ctrl.rs b/src/watchdog/ctrl.rs index 8549720df..001919eca 100644 --- a/src/watchdog/ctrl.rs +++ b/src/watchdog/ctrl.rs @@ -87,16 +87,6 @@ impl W { pub fn trigger(&mut self) -> TRIGGER_W { TRIGGER_W::new(self, 31) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. @@ -111,6 +101,7 @@ impl crate::RegisterSpec for CTRL_SPEC { impl crate::Readable for CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/load.rs b/src/watchdog/load.rs index ad8b26689..2825a6257 100644 --- a/src/watchdog/load.rs +++ b/src/watchdog/load.rs @@ -9,16 +9,6 @@ impl W { pub fn load(&mut self) -> LOAD_W { LOAD_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). @@ -29,6 +19,7 @@ impl crate::RegisterSpec for LOAD_SPEC { } #[doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"] impl crate::Writable for LOAD_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch0.rs b/src/watchdog/scratch0.rs index 19da34386..a2eae729a 100644 --- a/src/watchdog/scratch0.rs +++ b/src/watchdog/scratch0.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH0_SPEC { impl crate::Readable for SCRATCH0_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch0::W`](W) writer structure"] impl crate::Writable for SCRATCH0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch1.rs b/src/watchdog/scratch1.rs index 3853e6240..0bb7e84bc 100644 --- a/src/watchdog/scratch1.rs +++ b/src/watchdog/scratch1.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH1_SPEC { impl crate::Readable for SCRATCH1_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch1::W`](W) writer structure"] impl crate::Writable for SCRATCH1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch2.rs b/src/watchdog/scratch2.rs index d3426436d..32f137a3d 100644 --- a/src/watchdog/scratch2.rs +++ b/src/watchdog/scratch2.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH2_SPEC { impl crate::Readable for SCRATCH2_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch2::W`](W) writer structure"] impl crate::Writable for SCRATCH2_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch3.rs b/src/watchdog/scratch3.rs index 8f65461ce..ac456ffae 100644 --- a/src/watchdog/scratch3.rs +++ b/src/watchdog/scratch3.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH3_SPEC { impl crate::Readable for SCRATCH3_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch3::W`](W) writer structure"] impl crate::Writable for SCRATCH3_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch4.rs b/src/watchdog/scratch4.rs index 001fc92dc..70cc061ee 100644 --- a/src/watchdog/scratch4.rs +++ b/src/watchdog/scratch4.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH4_SPEC { impl crate::Readable for SCRATCH4_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch4::W`](W) writer structure"] impl crate::Writable for SCRATCH4_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch5.rs b/src/watchdog/scratch5.rs index e05abc5bb..f4326a151 100644 --- a/src/watchdog/scratch5.rs +++ b/src/watchdog/scratch5.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH5_SPEC { impl crate::Readable for SCRATCH5_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch5::W`](W) writer structure"] impl crate::Writable for SCRATCH5_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch6.rs b/src/watchdog/scratch6.rs index b2e13be45..f6b084e35 100644 --- a/src/watchdog/scratch6.rs +++ b/src/watchdog/scratch6.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH6_SPEC { impl crate::Readable for SCRATCH6_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch6::W`](W) writer structure"] impl crate::Writable for SCRATCH6_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/scratch7.rs b/src/watchdog/scratch7.rs index 96b70d989..7366acd53 100644 --- a/src/watchdog/scratch7.rs +++ b/src/watchdog/scratch7.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Scratch register. Information persists through soft reset of the chip. You can [`read`](crate::generic::Reg::read) this register and get [`scratch7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scratch7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] @@ -35,6 +24,7 @@ impl crate::RegisterSpec for SCRATCH7_SPEC { impl crate::Readable for SCRATCH7_SPEC {} #[doc = "`write(|w| ..)` method takes [`scratch7::W`](W) writer structure"] impl crate::Writable for SCRATCH7_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/watchdog/tick.rs b/src/watchdog/tick.rs index 8c11931ef..8a5a257d2 100644 --- a/src/watchdog/tick.rs +++ b/src/watchdog/tick.rs @@ -49,16 +49,6 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 9) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Controls the tick generator @@ -71,6 +61,7 @@ impl crate::RegisterSpec for TICK_SPEC { impl crate::Readable for TICK_SPEC {} #[doc = "`write(|w| ..)` method takes [`tick::W`](W) writer structure"] impl crate::Writable for TICK_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ctrl.rs b/src/xip_ctrl.rs index 74a79a7a2..7e89236fa 100644 --- a/src/xip_ctrl.rs +++ b/src/xip_ctrl.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ctrl: CTRL, flush: FLUSH, diff --git a/src/xip_ctrl/ctr_acc.rs b/src/xip_ctrl/ctr_acc.rs index c2a0a9d59..f22926893 100644 --- a/src/xip_ctrl/ctr_acc.rs +++ b/src/xip_ctrl/ctr_acc.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Cache Access counter A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. @@ -38,6 +27,7 @@ impl crate::RegisterSpec for CTR_ACC_SPEC { impl crate::Readable for CTR_ACC_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctr_acc::W`](W) writer structure"] impl crate::Writable for CTR_ACC_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ctrl/ctr_hit.rs b/src/xip_ctrl/ctr_hit.rs index 8d0ab0b22..1ec689767 100644 --- a/src/xip_ctrl/ctr_hit.rs +++ b/src/xip_ctrl/ctr_hit.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Cache Hit counter A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. @@ -38,6 +27,7 @@ impl crate::RegisterSpec for CTR_HIT_SPEC { impl crate::Readable for CTR_HIT_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctr_hit::W`](W) writer structure"] impl crate::Writable for CTR_HIT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ctrl/ctrl.rs b/src/xip_ctrl/ctrl.rs index 1c7d93796..30068d207 100644 --- a/src/xip_ctrl/ctrl.rs +++ b/src/xip_ctrl/ctrl.rs @@ -106,16 +106,6 @@ impl W { pub fn power_down(&mut self) -> POWER_DOWN_W { POWER_DOWN_W::new(self, 3) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Cache control @@ -128,6 +118,7 @@ impl crate::RegisterSpec for CTRL_SPEC { impl crate::Readable for CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ctrl/flush.rs b/src/xip_ctrl/flush.rs index 500c041bc..8598d60d1 100644 --- a/src/xip_ctrl/flush.rs +++ b/src/xip_ctrl/flush.rs @@ -36,16 +36,6 @@ impl W { pub fn flush(&mut self) -> FLUSH_W { FLUSH_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Cache Flush control @@ -58,6 +48,7 @@ impl crate::RegisterSpec for FLUSH_SPEC { impl crate::Readable for FLUSH_SPEC {} #[doc = "`write(|w| ..)` method takes [`flush::W`](W) writer structure"] impl crate::Writable for FLUSH_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ctrl/stream_addr.rs b/src/xip_ctrl/stream_addr.rs index aa95e9dd8..384aaf518 100644 --- a/src/xip_ctrl/stream_addr.rs +++ b/src/xip_ctrl/stream_addr.rs @@ -28,16 +28,6 @@ impl W { pub fn stream_addr(&mut self) -> STREAM_ADDR_W { STREAM_ADDR_W::new(self, 2) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "FIFO stream address @@ -50,6 +40,7 @@ impl crate::RegisterSpec for STREAM_ADDR_SPEC { impl crate::Readable for STREAM_ADDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`stream_addr::W`](W) writer structure"] impl crate::Writable for STREAM_ADDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ctrl/stream_ctr.rs b/src/xip_ctrl/stream_ctr.rs index 492955e59..430b2d567 100644 --- a/src/xip_ctrl/stream_ctr.rs +++ b/src/xip_ctrl/stream_ctr.rs @@ -48,16 +48,6 @@ impl W { pub fn stream_ctr(&mut self) -> STREAM_CTR_W { STREAM_CTR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "FIFO stream control @@ -70,6 +60,7 @@ impl crate::RegisterSpec for STREAM_CTR_SPEC { impl crate::Readable for STREAM_CTR_SPEC {} #[doc = "`write(|w| ..)` method takes [`stream_ctr::W`](W) writer structure"] impl crate::Writable for STREAM_CTR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi.rs b/src/xip_ssi.rs index 9ab935849..71ff0a4de 100644 --- a/src/xip_ssi.rs +++ b/src/xip_ssi.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ctrlr0: CTRLR0, ctrlr1: CTRLR1, diff --git a/src/xip_ssi/baudr.rs b/src/xip_ssi/baudr.rs index bc37ace02..1b6fce8e8 100644 --- a/src/xip_ssi/baudr.rs +++ b/src/xip_ssi/baudr.rs @@ -20,16 +20,6 @@ impl W { pub fn sckdv(&mut self) -> SCKDV_W { SCKDV_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Baud rate @@ -42,6 +32,7 @@ impl crate::RegisterSpec for BAUDR_SPEC { impl crate::Readable for BAUDR_SPEC {} #[doc = "`write(|w| ..)` method takes [`baudr::W`](W) writer structure"] impl crate::Writable for BAUDR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/ctrlr0.rs b/src/xip_ssi/ctrlr0.rs index d661cd7fb..7c6221a3f 100644 --- a/src/xip_ssi/ctrlr0.rs +++ b/src/xip_ssi/ctrlr0.rs @@ -18,8 +18,6 @@ pub type SCPH_W<'a, REG> = crate::BitWriter<'a, REG>; pub type SCPOL_R = crate::BitReader; #[doc = "Field `SCPOL` writer - Serial clock polarity"] pub type SCPOL_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `TMOD` reader - Transfer mode"] -pub type TMOD_R = crate::FieldReader; #[doc = "Transfer mode Value on reset: 0"] @@ -44,6 +42,8 @@ impl From for u8 { impl crate::FieldSpec for TMOD_A { type Ux = u8; } +#[doc = "Field `TMOD` reader - Transfer mode"] +pub type TMOD_R = crate::FieldReader; impl TMOD_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -125,8 +125,6 @@ pub type DFS_32_R = crate::FieldReader; #[doc = "Field `DFS_32` writer - Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame."] pub type DFS_32_W<'a, REG> = crate::FieldWriter<'a, REG, 5>; -#[doc = "Field `SPI_FRF` reader - SPI frame format"] -pub type SPI_FRF_R = crate::FieldReader; #[doc = "SPI frame format Value on reset: 0"] @@ -149,6 +147,8 @@ impl From for u8 { impl crate::FieldSpec for SPI_FRF_A { type Ux = u8; } +#[doc = "Field `SPI_FRF` reader - SPI frame format"] +pub type SPI_FRF_R = crate::FieldReader; impl SPI_FRF_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -331,16 +331,6 @@ impl W { pub fn sste(&mut self) -> SSTE_W { SSTE_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Control register 0 @@ -353,6 +343,7 @@ impl crate::RegisterSpec for CTRLR0_SPEC { impl crate::Readable for CTRLR0_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrlr0::W`](W) writer structure"] impl crate::Writable for CTRLR0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/ctrlr1.rs b/src/xip_ssi/ctrlr1.rs index bd51dea29..774910136 100644 --- a/src/xip_ssi/ctrlr1.rs +++ b/src/xip_ssi/ctrlr1.rs @@ -20,16 +20,6 @@ impl W { pub fn ndf(&mut self) -> NDF_W { NDF_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Master Control register 1 @@ -42,6 +32,7 @@ impl crate::RegisterSpec for CTRLR1_SPEC { impl crate::Readable for CTRLR1_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrlr1::W`](W) writer structure"] impl crate::Writable for CTRLR1_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/dmacr.rs b/src/xip_ssi/dmacr.rs index 4ac4fa6f9..49ba1b124 100644 --- a/src/xip_ssi/dmacr.rs +++ b/src/xip_ssi/dmacr.rs @@ -35,16 +35,6 @@ impl W { pub fn tdmae(&mut self) -> TDMAE_W { TDMAE_W::new(self, 1) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA control @@ -57,6 +47,7 @@ impl crate::RegisterSpec for DMACR_SPEC { impl crate::Readable for DMACR_SPEC {} #[doc = "`write(|w| ..)` method takes [`dmacr::W`](W) writer structure"] impl crate::Writable for DMACR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/dmardlr.rs b/src/xip_ssi/dmardlr.rs index 88a20df3a..8e4be1c5f 100644 --- a/src/xip_ssi/dmardlr.rs +++ b/src/xip_ssi/dmardlr.rs @@ -20,16 +20,6 @@ impl W { pub fn dmardl(&mut self) -> DMARDL_W { DMARDL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA RX data level @@ -42,6 +32,7 @@ impl crate::RegisterSpec for DMARDLR_SPEC { impl crate::Readable for DMARDLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`dmardlr::W`](W) writer structure"] impl crate::Writable for DMARDLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/dmatdlr.rs b/src/xip_ssi/dmatdlr.rs index 061ff71c4..f9cd31035 100644 --- a/src/xip_ssi/dmatdlr.rs +++ b/src/xip_ssi/dmatdlr.rs @@ -20,16 +20,6 @@ impl W { pub fn dmatdl(&mut self) -> DMATDL_W { DMATDL_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "DMA TX data level @@ -42,6 +32,7 @@ impl crate::RegisterSpec for DMATDLR_SPEC { impl crate::Readable for DMATDLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`dmatdlr::W`](W) writer structure"] impl crate::Writable for DMATDLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/dr0.rs b/src/xip_ssi/dr0.rs index 2902befab..db1f94def 100644 --- a/src/xip_ssi/dr0.rs +++ b/src/xip_ssi/dr0.rs @@ -20,16 +20,6 @@ impl W { pub fn dr(&mut self) -> DR_W { DR_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Data Register 0 (of 36) @@ -42,6 +32,7 @@ impl crate::RegisterSpec for DR0_SPEC { impl crate::Readable for DR0_SPEC {} #[doc = "`write(|w| ..)` method takes [`dr0::W`](W) writer structure"] impl crate::Writable for DR0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/imr.rs b/src/xip_ssi/imr.rs index 0ee3b273d..ecc016a9a 100644 --- a/src/xip_ssi/imr.rs +++ b/src/xip_ssi/imr.rs @@ -95,16 +95,6 @@ impl W { pub fn mstim(&mut self) -> MSTIM_W { MSTIM_W::new(self, 5) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Interrupt mask @@ -117,6 +107,7 @@ impl crate::RegisterSpec for IMR_SPEC { impl crate::Readable for IMR_SPEC {} #[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"] impl crate::Writable for IMR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/mwcr.rs b/src/xip_ssi/mwcr.rs index c20a36cc5..78e88d6ed 100644 --- a/src/xip_ssi/mwcr.rs +++ b/src/xip_ssi/mwcr.rs @@ -50,16 +50,6 @@ impl W { pub fn mhs(&mut self) -> MHS_W { MHS_W::new(self, 2) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Microwire Control @@ -72,6 +62,7 @@ impl crate::RegisterSpec for MWCR_SPEC { impl crate::Readable for MWCR_SPEC {} #[doc = "`write(|w| ..)` method takes [`mwcr::W`](W) writer structure"] impl crate::Writable for MWCR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/rx_sample_dly.rs b/src/xip_ssi/rx_sample_dly.rs index a1dbd159b..07e61c663 100644 --- a/src/xip_ssi/rx_sample_dly.rs +++ b/src/xip_ssi/rx_sample_dly.rs @@ -20,16 +20,6 @@ impl W { pub fn rsd(&mut self) -> RSD_W { RSD_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "RX sample delay @@ -42,6 +32,7 @@ impl crate::RegisterSpec for RX_SAMPLE_DLY_SPEC { impl crate::Readable for RX_SAMPLE_DLY_SPEC {} #[doc = "`write(|w| ..)` method takes [`rx_sample_dly::W`](W) writer structure"] impl crate::Writable for RX_SAMPLE_DLY_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/rxftlr.rs b/src/xip_ssi/rxftlr.rs index 60273e3c4..63ae9087e 100644 --- a/src/xip_ssi/rxftlr.rs +++ b/src/xip_ssi/rxftlr.rs @@ -20,16 +20,6 @@ impl W { pub fn rft(&mut self) -> RFT_W { RFT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "RX FIFO threshold level @@ -42,6 +32,7 @@ impl crate::RegisterSpec for RXFTLR_SPEC { impl crate::Readable for RXFTLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`rxftlr::W`](W) writer structure"] impl crate::Writable for RXFTLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/ser.rs b/src/xip_ssi/ser.rs index 7239fe40f..39966b034 100644 --- a/src/xip_ssi/ser.rs +++ b/src/xip_ssi/ser.rs @@ -28,16 +28,6 @@ impl W { pub fn ser(&mut self) -> SER_W { SER_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Slave enable @@ -50,6 +40,7 @@ impl crate::RegisterSpec for SER_SPEC { impl crate::Readable for SER_SPEC {} #[doc = "`write(|w| ..)` method takes [`ser::W`](W) writer structure"] impl crate::Writable for SER_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/spi_ctrlr0.rs b/src/xip_ssi/spi_ctrlr0.rs index 3fce2ddbd..e025f4861 100644 --- a/src/xip_ssi/spi_ctrlr0.rs +++ b/src/xip_ssi/spi_ctrlr0.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `SPI_CTRLR0` writer"] pub type W = crate::W; -#[doc = "Field `TRANS_TYPE` reader - Address and instruction transfer format"] -pub type TRANS_TYPE_R = crate::FieldReader; #[doc = "Address and instruction transfer format Value on reset: 0"] @@ -26,6 +24,8 @@ impl From for u8 { impl crate::FieldSpec for TRANS_TYPE_A { type Ux = u8; } +#[doc = "Field `TRANS_TYPE` reader - Address and instruction transfer format"] +pub type TRANS_TYPE_R = crate::FieldReader; impl TRANS_TYPE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -80,8 +80,6 @@ where pub type ADDR_L_R = crate::FieldReader; #[doc = "Field `ADDR_L` writer - Address length (0b-60b in 4b increments)"] pub type ADDR_L_W<'a, REG> = crate::FieldWriter<'a, REG, 4>; -#[doc = "Field `INST_L` reader - Instruction length (0/4/8/16b)"] -pub type INST_L_R = crate::FieldReader; #[doc = "Instruction length (0/4/8/16b) Value on reset: 0"] @@ -106,6 +104,8 @@ impl From for u8 { impl crate::FieldSpec for INST_L_A { type Ux = u8; } +#[doc = "Field `INST_L` reader - Instruction length (0/4/8/16b)"] +pub type INST_L_R = crate::FieldReader; impl INST_L_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -278,16 +278,6 @@ impl W { pub fn xip_cmd(&mut self) -> XIP_CMD_W { XIP_CMD_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "SPI control @@ -300,6 +290,7 @@ impl crate::RegisterSpec for SPI_CTRLR0_SPEC { impl crate::Readable for SPI_CTRLR0_SPEC {} #[doc = "`write(|w| ..)` method takes [`spi_ctrlr0::W`](W) writer structure"] impl crate::Writable for SPI_CTRLR0_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/ssienr.rs b/src/xip_ssi/ssienr.rs index 592719855..32c7dca35 100644 --- a/src/xip_ssi/ssienr.rs +++ b/src/xip_ssi/ssienr.rs @@ -20,16 +20,6 @@ impl W { pub fn ssi_en(&mut self) -> SSI_EN_W { SSI_EN_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "SSI Enable @@ -42,6 +32,7 @@ impl crate::RegisterSpec for SSIENR_SPEC { impl crate::Readable for SSIENR_SPEC {} #[doc = "`write(|w| ..)` method takes [`ssienr::W`](W) writer structure"] impl crate::Writable for SSIENR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/txd_drive_edge.rs b/src/xip_ssi/txd_drive_edge.rs index 9614764df..e111cf304 100644 --- a/src/xip_ssi/txd_drive_edge.rs +++ b/src/xip_ssi/txd_drive_edge.rs @@ -20,16 +20,6 @@ impl W { pub fn tde(&mut self) -> TDE_W { TDE_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "TX drive edge @@ -42,6 +32,7 @@ impl crate::RegisterSpec for TXD_DRIVE_EDGE_SPEC { impl crate::Readable for TXD_DRIVE_EDGE_SPEC {} #[doc = "`write(|w| ..)` method takes [`txd_drive_edge::W`](W) writer structure"] impl crate::Writable for TXD_DRIVE_EDGE_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xip_ssi/txftlr.rs b/src/xip_ssi/txftlr.rs index 3bea41342..add51d481 100644 --- a/src/xip_ssi/txftlr.rs +++ b/src/xip_ssi/txftlr.rs @@ -20,16 +20,6 @@ impl W { pub fn tft(&mut self) -> TFT_W { TFT_W::new(self, 0) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "TX FIFO threshold level @@ -42,6 +32,7 @@ impl crate::RegisterSpec for TXFTLR_SPEC { impl crate::Readable for TXFTLR_SPEC {} #[doc = "`write(|w| ..)` method takes [`txftlr::W`](W) writer structure"] impl crate::Writable for TXFTLR_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xosc.rs b/src/xosc.rs index ee4e051d3..5602a887a 100644 --- a/src/xosc.rs +++ b/src/xosc.rs @@ -1,5 +1,5 @@ -#[doc = r"Register block"] #[repr(C)] +#[doc = "Register block"] pub struct RegisterBlock { ctrl: CTRL, status: STATUS, diff --git a/src/xosc/ctrl.rs b/src/xosc/ctrl.rs index 67695405c..3251a3d4c 100644 --- a/src/xosc/ctrl.rs +++ b/src/xosc/ctrl.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `CTRL` writer"] pub type W = crate::W; -#[doc = "Field `FREQ_RANGE` reader - Frequency range. This resets to 0xAA0 and cannot be changed."] -pub type FREQ_RANGE_R = crate::FieldReader; #[doc = "Frequency range. This resets to 0xAA0 and cannot be changed. Value on reset: 0"] @@ -28,6 +26,8 @@ impl From for u16 { impl crate::FieldSpec for FREQ_RANGE_A { type Ux = u16; } +#[doc = "Field `FREQ_RANGE` reader - Frequency range. This resets to 0xAA0 and cannot be changed."] +pub type FREQ_RANGE_R = crate::FieldReader; impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -89,10 +89,6 @@ where self.variant(FREQ_RANGE_A::RESERVED_3) } } -#[doc = "Field `ENABLE` reader - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. - If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] -pub type ENABLE_R = crate::FieldReader; #[doc = "On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. @@ -115,6 +111,10 @@ impl From for u16 { impl crate::FieldSpec for ENABLE_A { type Ux = u16; } +#[doc = "Field `ENABLE` reader - On power-up this field is initialised to DISABLE and the chip runs from the ROSC. + If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. + The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator."] +pub type ENABLE_R = crate::FieldReader; impl ENABLE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -185,16 +185,6 @@ impl W { pub fn enable(&mut self) -> ENABLE_W { ENABLE_W::new(self, 12) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Crystal Oscillator Control @@ -207,6 +197,7 @@ impl crate::RegisterSpec for CTRL_SPEC { impl crate::Readable for CTRL_SPEC {} #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] impl crate::Writable for CTRL_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xosc/dormant.rs b/src/xosc/dormant.rs index a0de06278..05a6f0650 100644 --- a/src/xosc/dormant.rs +++ b/src/xosc/dormant.rs @@ -12,18 +12,7 @@ impl core::fmt::Debug for crate::generic::Reg { core::fmt::Debug::fmt(&self.read(), f) } } -impl W { - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } -} +impl W {} #[doc = "Crystal Oscillator pause control This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE @@ -40,6 +29,7 @@ impl crate::RegisterSpec for DORMANT_SPEC { impl crate::Readable for DORMANT_SPEC {} #[doc = "`write(|w| ..)` method takes [`dormant::W`](W) writer structure"] impl crate::Writable for DORMANT_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xosc/startup.rs b/src/xosc/startup.rs index 6456fffd9..7bb4f02a9 100644 --- a/src/xosc/startup.rs +++ b/src/xosc/startup.rs @@ -35,16 +35,6 @@ impl W { pub fn x4(&mut self) -> X4_W { X4_W::new(self, 20) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Controls the startup delay @@ -57,6 +47,7 @@ impl crate::RegisterSpec for STARTUP_SPEC { impl crate::Readable for STARTUP_SPEC {} #[doc = "`write(|w| ..)` method takes [`startup::W`](W) writer structure"] impl crate::Writable for STARTUP_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; } diff --git a/src/xosc/status.rs b/src/xosc/status.rs index cef121614..519761725 100644 --- a/src/xosc/status.rs +++ b/src/xosc/status.rs @@ -2,8 +2,6 @@ pub type R = crate::R; #[doc = "Register `STATUS` writer"] pub type W = crate::W; -#[doc = "Field `FREQ_RANGE` reader - The current frequency range setting, always reads 0"] -pub type FREQ_RANGE_R = crate::FieldReader; #[doc = "The current frequency range setting, always reads 0 Value on reset: 0"] @@ -28,6 +26,8 @@ impl From for u8 { impl crate::FieldSpec for FREQ_RANGE_A { type Ux = u8; } +#[doc = "Field `FREQ_RANGE` reader - The current frequency range setting, always reads 0"] +pub type FREQ_RANGE_R = crate::FieldReader; impl FREQ_RANGE_R { #[doc = "Get enumerated values variant"] #[inline(always)] @@ -98,16 +98,6 @@ impl W { pub fn badwrite(&mut self) -> BADWRITE_W { BADWRITE_W::new(self, 24) } - #[doc = r" Writes raw bits to the register."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"] - #[inline(always)] - pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { - self.bits = bits; - self - } } #[doc = "Crystal Oscillator Status @@ -120,6 +110,7 @@ impl crate::RegisterSpec for STATUS_SPEC { impl crate::Readable for STATUS_SPEC {} #[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] impl crate::Writable for STATUS_SPEC { + type Safety = crate::Unsafe; const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0100_0000; }