From 97138482c29b3e07af3c9b72b7e8bb3b4e53c0fe Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Tue, 30 Apr 2019 22:15:14 -0700 Subject: [PATCH] Rewrite in asciidoc Signed-off-by: Palmer Dabbelt --- riscv-unix.adoc | 72 +++++++++++++++++++++++++++++++++++++++++++++++++ riscv-unix.md | 51 ----------------------------------- 2 files changed, 72 insertions(+), 51 deletions(-) create mode 100644 riscv-unix.adoc delete mode 100644 riscv-unix.md diff --git a/riscv-unix.adoc b/riscv-unix.adoc new file mode 100644 index 0000000..48e989e --- /dev/null +++ b/riscv-unix.adoc @@ -0,0 +1,72 @@ +# RISC-V UNIX-Class Platform Specification + +## Copyright and license information + +This RISC-V Unix-class platform specification is + +[%hardbreaks] +(C) 2017 Krste Asanovic +(C) 2017-2019 Palmer Dabbelt +(C) 2017 Andrew Waterman + +It is licensed under the Creative Commons Attribution 4.0 International +License (CC-BY 4.0). The full license text is available at +https://creativecommons.org/licenses/by/4.0/. + +## Introduction + +This document contains the RISC-V UNIX-class platform specification. This +specification defines additional restrictions on implementations in order to +allow software to be compatible between these implementations. These +restrictions are enumerated along with the least privileged level to which they +apply. Implementations can be compatible with a subset of this specification, +but that subset must include all restrictions placed on a privilege level as +well as all less-privileged levels. For example: implementations can claim to +be compatible with the "RISC-V Supervisor-Level UNIX Platform" if they are +compatible with the entire "User-Level Platform" and "Supervisor-Level +Platform" chapters of this document. + +### Versioning + +## User-Level Platform + +* User-mode environments must implement at least version 2.2 of the RISC-V User + ISA specification, which can be found at + https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf. +* User-mode programs may not execute the `fence.i` instruction. +* User-mode environments may provide additional ISA extensions, but if those + extensions add user-visible state they must be initially disabled. +* Within main-memory regions, aligned instruction fetch must be atomic, up to + the smaller of ILEN and XLEN bits. In particular, if an aligned 4-byte word + is stored with the `sw` instruction, then any processor attempts to execute + that word, the processor either fetches the newly stored word, or some previous + value stored to that location. (That is, the fetched instruction is not an + unpredictable value, nor is it a hybrid of the bytes of the old and new + values.) + +## Supervisor-Level Platform + +* Supervisor-mode environments must implement at least version 0.2.0 of the + RISC-V SBI specification, which can be found at + https://github.com/riscv/riscv-sbi-doc/blob/v0.2.0/riscv-sbi.adoc +* Supervisor-mode environments must implement the Sv39 page-based + virtual-memory scheme. Systems that support Sv48 must support Sv39, systems + that support Sv57 must support Sv48, and so forth. +* Unless otherwise specified by a given I/O device, I/O regions are at least + point-to-point strongly ordered. All devices attached to a given PCIe root + complex are on the same ordered channel (numbered 2 or above), though + different root complexes might not be on the same ordering channel. +* On RV64I-based Unix-class systems the negative virtual addresses are reserved + for the kernel. +* External devices (DMA engines, the debug unit, non RISC-V cores, etc) that + are visible to RISC-V harts must appear as coherent agents, just like any + RISC-V hart would. If additional ordering constraints are necessary for a + device to function, those will be provide by a device-specific mechanism. + +## Machine-Level Platform + +## Profiles + +### Portable UNIX Platform Profile + +* Supervisor-mode environments must implement RV64GC. diff --git a/riscv-unix.md b/riscv-unix.md deleted file mode 100644 index e0eaf30..0000000 --- a/riscv-unix.md +++ /dev/null @@ -1,51 +0,0 @@ -# RISC-V Unix-class Platform Specification - -# Copyright and license information - -This RISC-V Unix-class platform specification is - - © 2017 Krste Asanovic - - © 2017 Palmer Dabbelt - - © 2017 Andrew Waterman - -It is licensed under the Creative Commons Attribution 4.0 International -License (CC-BY 4.0). The full license text is available at -https://creativecommons.org/licenses/by/4.0/. - -# Unix-class Platform Specification - -This Unix-class platform specification is incomplete. Currently, it only -lists the constraints on a RISC-V implementation beyond those in the -architecture manual. It only describes the RV64 Unix platform; a future -version of this specification will describe the RV32 Unix platform. - -RISC-V Unix-class systems implement the RV64GC ISA with supervisor mode and -the Sv39 page-based virtual-memory scheme. Systems may support additional ISA -extensions, but if these extensions add user-visible architectural state, they -must be initially disabled. Systems that support Sv48 must support Sv39, -systems that support Sv57 must support Sv48, and so forth. - -Within main-memory regions, aligned instruction fetch must be atomic, up to -the smaller of ILEN and XLEN bits. In particular, if an aligned 4-byte word -is stored with the `sw` instruction, then any processor attempts to execute -that word, the processor either fetches the newly stored word, or some -previous value stored to that location. (That is, the fetched instruction is -not an unpredictable value, nor is it a hybrid of the bytes of the old and new -values.) - -Unless otherwise specified by a given I/O device, -I/O regions are at least point-to-point strongly ordered. -All devices attached to a given PCIe root complex are on the same ordered -channel (numbered 2 or above), though different root complexes might not -be on the same ordering channel. - -On RV64I-based Unix-class systems the negative virtual addresses are -reserved for the kernel. - -External devices (DMA engines, the debug unit, non RISC-V cores, etc) -that are visible to RISC-V harts must appear as coherent agents, just -like any RISC-V hart would. If additional ordering constraints are -necessary for a device to function, those will be provide by a -device-specific mechanism.