diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 0ec067769847..42767165d25f 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -68,6 +68,9 @@ riscv_implied_info_t riscv_implied_info[] =
   {"zks", "zksh"},
   {"zks", "zkg"},
   {"zks", "zkb"},
+  {"p", "zbpbo"},
+  {"p", "zpn"},
+  {"p", "zpsf"},
   {NULL, NULL}
 };
 
@@ -833,6 +836,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zksed", &gcc_options::x_riscv_crypto_subext, MASK_ZKSED},
   {"zksh", &gcc_options::x_riscv_crypto_subext, MASK_ZKSH},
 
+  {"zbpbo", &gcc_options::x_riscv_rvp_subext, MASK_ZBPBO},
+  {"zpn",  &gcc_options::x_riscv_rvp_subext, MASK_ZPN},
+  {"zpsf", &gcc_options::x_riscv_rvp_subext, MASK_ZPSF},
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 8d0e4de710ff..45b53f0a06d0 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -525,6 +525,7 @@ pru-*-*)
 	;;
 riscv*)
 	cpu_type=riscv
+	extra_headers="rvp_intrinsic.h"
 	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o"
 	d_target_objs="riscv-d.o"
 	;;
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index ef9c81e424ec..481786d50b1a 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -81,3 +81,73 @@
    A constant @code{move_operand}."
   (and (match_operand 0 "move_operand")
        (match_test "CONSTANT_P (op)")))
+
+(define_constraint "u02"
+  "Unsigned immediate 2-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 2) && ival >= 0")))
+
+(define_constraint "u03"
+  "Unsigned immediate 3-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 3) && ival >= 0")))
+
+(define_constraint "u04"
+  "Unsigned immediate 4-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 4) && ival >= 0")))
+
+(define_constraint "u05"
+  "Unsigned immediate 5-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 5) && ival >= 0")))
+
+(define_constraint "u06"
+  "Unsigned immediate 6-bit value"
+  (and (match_code "const_int")
+       (match_test "ival < (1 << 6) && ival >= 0")))
+
+(define_constraint "C00"
+  "Constant value 0"
+  (and (match_code "const_int")
+       (match_test "ival == 0")))
+
+(define_constraint "C01"
+  "Constant value 1"
+  (and (match_code "const_int")
+       (match_test "ival == 1")))
+
+(define_constraint "C02"
+  "Constant value 2"
+  (and (match_code "const_int")
+       (match_test "ival == 2")))
+
+(define_constraint "C03"
+  "Constant value 3"
+  (and (match_code "const_int")
+       (match_test "ival == 3")))
+
+(define_constraint "C04"
+  "Constant value 4"
+  (and (match_code "const_int")
+       (match_test "ival == 4")))
+
+(define_constraint "C08"
+  "Constant value 8"
+  (and (match_code "const_int")
+       (match_test "ival == 8")))
+
+(define_constraint "D07"
+  "A constraint that matches the integers 2^(0...7)."
+  (and (match_code "const_int")
+       (match_test "(unsigned) exact_log2 (ival) <= 7")))
+
+(define_constraint "C15"
+  "Constant value 15"
+  (and (match_code "const_int")
+       (match_test "ival == 15")))
+
+(define_constraint "C16"
+  "Constant value 16"
+  (and (match_code "const_int")
+       (match_test "ival == 16")))
\ No newline at end of file
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index f764fe7ba016..6684ff9d4856 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -212,3 +212,84 @@
 {
   return riscv_gpr_save_operation_p (op);
 })
+
+(define_predicate "imm2u_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "satisfies_constraint_u02 (op)")))
+
+(define_predicate "imm3u_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "satisfies_constraint_u03 (op)")))
+
+(define_predicate "imm4u_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "satisfies_constraint_u04 (op)")))
+       
+(define_predicate "imm5u_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "satisfies_constraint_u05 (op)")))
+
+(define_predicate "imm6u_operand"
+  (and (match_operand 0 "const_int_operand")
+       (match_test "satisfies_constraint_u06 (op)")))
+
+(define_predicate "rimm3u_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "imm3u_operand")))
+
+(define_predicate "rimm4u_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "imm4u_operand")))
+
+(define_predicate "rimm5u_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "imm5u_operand")))
+
+(define_predicate "rimm6u_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_operand 0 "imm6u_operand")))
+
+(define_predicate "const_insb64_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
+
+(define_predicate "imm_1_2_4_8_operand"
+  (and (match_operand 0 "const_int_operand")
+       (ior (ior (match_test "satisfies_constraint_C01 (op)")
+		 (match_test "satisfies_constraint_C02 (op)"))
+	    (ior (match_test "satisfies_constraint_C04 (op)")
+		 (match_test "satisfies_constraint_C08 (op)")))))
+
+(define_predicate "pwr_7_operand"
+  (and (match_code "const_int")
+       (match_test "INTVAL (op) != 0
+		    && (unsigned) exact_log2 (INTVAL (op)) <= 7")))
+
+(define_predicate "imm_0_1_operand"
+  (and (match_operand 0 "const_int_operand")
+       (ior (match_test "satisfies_constraint_C00 (op)")
+	    (match_test "satisfies_constraint_C01 (op)"))))
+
+(define_predicate "imm_1_2_operand"
+  (and (match_operand 0 "const_int_operand")
+       (ior (match_test "satisfies_constraint_C01 (op)")
+	    (match_test "satisfies_constraint_C02 (op)"))))
+
+(define_predicate "imm_2_3_operand"
+  (and (match_operand 0 "const_int_operand")
+       (ior (match_test "satisfies_constraint_C02 (op)")
+	    (match_test "satisfies_constraint_C03 (op)"))))
+
+(define_predicate "imm_15_16_operand"
+  (and (match_operand 0 "const_int_operand")
+       (ior (match_test "satisfies_constraint_C15 (op)")
+	    (match_test "satisfies_constraint_C16 (op)"))))
+
+(define_predicate "rev_rimm_operand"
+  (ior (match_operand 0 "const_arith_operand")
+       (match_test "INTVAL (op) == (BITS_PER_WORD - 1)")))
+
+(define_predicate "fsr_shamt_imm"
+  (ior (match_operand 0 "register_operand")
+       (and (match_operand 0 "const_arith_operand")
+            (match_test "IN_RANGE (INTVAL (op), 1, 31)"))))
diff --git a/gcc/config/riscv/riscv-builtins-rvp.def b/gcc/config/riscv/riscv-builtins-rvp.def
new file mode 100644
index 000000000000..59e14d707a81
--- /dev/null
+++ b/gcc/config/riscv/riscv-builtins-rvp.def
@@ -0,0 +1,967 @@
+/* Builtin definitions for P extension
+   Copyright (C) 2021 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+/* zpn subset */
+DIRECT_BUILTIN_NO_PREFIX (addv4qi3, add8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (addv8qi3, add8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv4qi3, v_uadd8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (addv4qi3, v_sadd8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (addv8qi3, v64_uadd8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv8qi3, v64_sadd8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv2hi3, add16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (addv4hi3, add16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv2hi3, v_uadd16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (addv2hi3, v_sadd16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (addv4hi3, v64_uadd16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv4hi3, v64_sadd16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ave, ave, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (avedi, ave, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (bitrevsi, bitrev, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (bitrevdi, bitrev, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_NO_TARGET_BUILTIN_NO_PREFIX (clrovsi, clrov, RISCV_VOID_FTYPE_VOID, zpn32),
+DIRECT_NO_TARGET_BUILTIN_NO_PREFIX (clrovdi, clrov, RISCV_VOID_FTYPE_VOID, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv4qi2, clrs8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv4qi2, v_clrs8, RISCV_UV4QI_FTYPE_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv8qi2, clrs8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv8qi2, v64_clrs8, RISCV_UV8QI_FTYPE_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv2hi2, clrs16, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv4hi2, clrs16, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv2hi2, v_clrs16, RISCV_UV2HI_FTYPE_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv4hi2, v64_clrs16, RISCV_UV4HI_FTYPE_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clrsbsi2, clrs32, RISCV_UIXLEN_FTYPE_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv2si2, clrs32, RISCV_UIXLEN_FTYPE_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clrsbv2si2, v_clrs32, RISCV_UV2SI_FTYPE_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clzv4qi2, clz8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clzv8qi2, clz8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clzv4qi2, v_clz8, RISCV_UV4QI_FTYPE_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clzv8qi2, v64_clz8, RISCV_UV8QI_FTYPE_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clzv2hi2, clz16, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clzv4hi2, clz16, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clzv2hi2, v_clz16, RISCV_UV2HI_FTYPE_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clzv4hi2, v64_clz16, RISCV_UV4HI_FTYPE_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clzsi2, clz32, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (clzv2si2, clz32, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (clzv2si2, v_clz32, RISCV_UV2SI_FTYPE_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv4qi, cmpeq8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv8qi, cmpeq8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv4qi, v_scmpeq8, RISCV_UV4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv4qi, v_ucmpeq8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv8qi, v64_scmpeq8, RISCV_UV8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv8qi, v64_ucmpeq8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv2hi, cmpeq16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv4hi, cmpeq16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv2hi, v_scmpeq16, RISCV_UV2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv2hi, v_ucmpeq16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv4hi, v64_scmpeq16, RISCV_UV4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cmpeqv4hi, v64_ucmpeq16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crasv2hi, cras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (crasv2hi, v_ucras16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (crasv2hi, v_scras16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (cras16_64, cras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cras16_64, v64_ucras16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (cras16_64, v64_scras16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crsav2hi, crsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (crsav2hi, v_ucrsa16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (crsav2hi, v_scrsa16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (crsa16_64, crsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crsa16_64, v64_ucrsa16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crsa16_64, v64_scrsa16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (insb, insb, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (insb64, insb, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kabsv4qi2, kabs8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kabsv4qi2, v_kabs8, RISCV_V4QI_FTYPE_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kabsv8qi2, kabs8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kabsv8qi2, v64_kabs8, RISCV_V8QI_FTYPE_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kabsv2hi2, kabs16, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kabsv2hi2, v_kabs16, RISCV_V2HI_FTYPE_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kabsv4hi2, kabs16, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kabsv4hi2, v64_kabs16, RISCV_V4HI_FTYPE_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kabsw, kabsw, RISCV_SI_FTYPE_SI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kaddv4qi3, kadd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kaddv4qi3, v_kadd8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kaddv8qi3, kadd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kaddv8qi3, v64_kadd8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kaddv2hi3, kadd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kaddv2hi3, v_kadd16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kaddv4hi3, kadd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kaddv4hi3, v64_kadd16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ssaddhi3, kaddh, RISCV_HI_FTYPE_HI_HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kcrasv2hi, kcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kcrasv2hi, v_kcras16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kcras16_64, kcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kcras16_64, v64_kcras16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kcrsav2hi, kcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kcrsav2hi, v_kcrsa16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kcrsa16_64, kcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kcrsa16_64, v64_kcrsa16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmbb, kdmbb, RISCV_SI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmbt, kdmbt, RISCV_SI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmtt, kdmtt, RISCV_SI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmbb, v_kdmbb, RISCV_SI_FTYPE_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmbt, v_kdmbt, RISCV_SI_FTYPE_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmtt, v_kdmtt, RISCV_SI_FTYPE_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmabb, kdmabb, RISCV_SI_FTYPE_SI_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmabt, kdmabt, RISCV_SI_FTYPE_SI_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmatt, kdmatt, RISCV_SI_FTYPE_SI_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmabb, v_kdmabb, RISCV_SI_FTYPE_SI_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmabt, v_kdmabt, RISCV_SI_FTYPE_SI_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kdmatt, v_kdmatt, RISCV_SI_FTYPE_SI_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (khm8v4qi, khm8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khmx8v4qi, khmx8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khm8v4qi, v_khm8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khmx8v4qi, v_khmx8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khm8v8qi, khm8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmx8v8qi, khmx8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khm8v8qi, v64_khm8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmx8v8qi, v64_khmx8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khm16v2hi, khm16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khmx16v2hi, khmx16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khm16v2hi, v_khm16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khmx16v2hi, v_khmx16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (khm16v4hi, khm16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmx16v4hi, khmx16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khm16v4hi, v64_khm16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmx16v4hi, v64_khmx16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmbbsi, khmbb, RISCV_SI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (khmbtsi, khmbt, RISCV_SI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (khmttsi, khmtt, RISCV_SI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (khmbbsi, v_khmbb, RISCV_SI_FTYPE_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (khmbtsi, v_khmbt, RISCV_SI_FTYPE_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (khmttsi, v_khmtt, RISCV_SI_FTYPE_V2HI_V2HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kmabb, kmabb, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmabt, kmabt, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmatt, kmatt, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmabb, v_kmabb, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmabt, v_kmabt, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmatt, v_kmatt, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmabb64, kmabb, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmabt64, kmabt, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmatt64, kmatt, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmabb64, v64_kmabb, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmabt64, v64_kmabt, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmatt64, v64_kmatt, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmada, kmada, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmaxda, kmaxda, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmada, v_kmada, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmaxda, v_kmaxda, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmada64, kmada, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxda64, kmaxda, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmada64, v64_kmada, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxda64, v64_kmaxda, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmads, kmads, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmadrs, kmadrs, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmaxds, kmaxds, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmads, v_kmads, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmadrs, v_kmadrs, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmaxds, v_kmaxds, RISCV_IXLEN_FTYPE_IXLEN_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmads64, kmads, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmadrs64, kmadrs, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxds64, kmaxds, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmads64, v64_kmads, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmadrs64, v64_kmadrs, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxds64, v64_kmaxds, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmda, kmda, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmxda, kmxda, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmda, v_kmda, RISCV_IXLEN_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmxda, v_kmxda, RISCV_IXLEN_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmda64, kmda, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmxda64, kmxda, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmda64, v64_kmda, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmxda64, v64_kmxda, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmac, kmmac, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmac_round, kmmac_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmac_64, kmmac, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmac64_round, kmmac_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmac_64, v_kmmac, RISCV_V2SI_FTYPE_V2SI_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmac64_round, v_kmmac_u, RISCV_V2SI_FTYPE_V2SI_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb, kmmawb, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb_round, kmmawb_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb, v_kmmawb, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb_round, v_kmmawb_u, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb64, kmmawb, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb64_round, kmmawb_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb64, v64_kmmawb, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb64_round, v64_kmmawb_u, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2, kmmawb2, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2_round, kmmawb2_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2, v_kmmawb2, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2_round, v_kmmawb2_u, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2_64, kmmawb2, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2_64_round, kmmawb2_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2_64, v64_kmmawb2, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawb2_64_round, v64_kmmawb2_u, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt, kmmawt, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt_round, kmmawt_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2, kmmawt2, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2_round, kmmawt2_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt, v_kmmawt, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt_round, v_kmmawt_u, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2, v_kmmawt2, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2_round, v_kmmawt2_u, RISCV_SI_FTYPE_SI_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt64, kmmawt, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt64_round, kmmawt_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2_64, kmmawt2, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2_64_round, kmmawt2_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt64, v64_kmmawt, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt64_round, v64_kmmawt_u, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2_64, v64_kmmawt2, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmawt2_64_round, v64_kmmawt2_u, RISCV_V2SI_FTYPE_V2SI_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmsb, kmmsb, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmsb_round, kmmsb_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmsb_64, kmmsb, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmsb64_round, kmmsb_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmsb_64, v_kmmsb, RISCV_V2SI_FTYPE_V2SI_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmsb64_round, v_kmmsb_u, RISCV_V2SI_FTYPE_V2SI_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb2, kmmwb2, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb2_round, kmmwb2_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb2, v_kmmwb2, RISCV_SI_FTYPE_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb2_round, v_kmmwb2_u, RISCV_SI_FTYPE_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb64, kmmwb2, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb64_round, kmmwb2_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb64, v64_kmmwb2, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwb64_round, v64_kmmwb2_u, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt2, kmmwt2, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt2_round, kmmwt2_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt2, v_kmmwt2, RISCV_SI_FTYPE_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt2_round, v_kmmwt2_u, RISCV_SI_FTYPE_SI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt64, kmmwt2, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt64_round, kmmwt2_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt64, v64_kmmwt2, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmmwt64_round, v64_kmmwt2_u, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsda, kmsda, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmsxda, kmsxda, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmsda, v_kmsda, RISCV_SI_FTYPE_SI_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmsxda, v_kmsxda, RISCV_SI_FTYPE_SI_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kmsda64, kmsda, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsxda64, kmsxda, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsda64, v64_kmsda, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsxda64, v64_kmsxda, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksll, ksllw, RISCV_SI_FTYPE_SI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kslli8v4qisi, ksll8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslli8v4qisi, v_ksll8, RISCV_V4QI_FTYPE_V4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslli8v8qidi, ksll8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslli8v8qidi, v64_ksll8, RISCV_V8QI_FTYPE_V8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslli16v2hi, ksll16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslli16v2hi, v_ksll16, RISCV_V2HI_FTYPE_V2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslli16v4hi, ksll16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslli16v4hi, v64_ksll16, RISCV_V4HI_FTYPE_V4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4qi, kslra8, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4qi_round, kslra8_u, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4qi, v_kslra8, RISCV_V4QI_FTYPE_V4QI_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4qi_round, v_kslra8_u, RISCV_V4QI_FTYPE_V4QI_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav8qi, kslra8, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav8qi_round, kslra8_u, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav8qi, v64_kslra8, RISCV_V8QI_FTYPE_V8QI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav8qi_round, v64_kslra8_u, RISCV_V8QI_FTYPE_V8QI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2hi, kslra16, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2hi_round, kslra16_u, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2hi, v_kslra16, RISCV_V2HI_FTYPE_V2HI_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2hi_round, v_kslra16_u, RISCV_V2HI_FTYPE_V2HI_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4hi, kslra16, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4hi_round, kslra16_u, RISCV_UIXLEN_FTYPE_UIXLEN_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4hi, v64_kslra16, RISCV_V4HI_FTYPE_V4HI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav4hi_round, v64_kslra16_u, RISCV_V4HI_FTYPE_V4HI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslraw, kslraw, RISCV_IXLEN_FTYPE_SI_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslrawu, kslraw_u, RISCV_IXLEN_FTYPE_SI_SI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kslraw64, kslraw, RISCV_IXLEN_FTYPE_SI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrawu64, kslraw_u, RISCV_IXLEN_FTYPE_SI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstasv2hi, kstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kstasv2hi, v_kstas16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kstas16_64, kstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstas16_64, v64_kstas16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstsav2hi, kstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kstsav2hi, v_kstsa16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kstsa16_64, kstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstsa16_64, v64_kstsa16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksubv4qi3, ksub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ksubv4qi3, v_ksub8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ksubv8qi3, ksub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksubv8qi3, v64_ksub8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksubv2hi3, ksub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ksubv2hi3, v_ksub16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ksubv4hi3, ksub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksubv4hi3, v64_ksub16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sssubhi3, ksubh, RISCV_HI_FTYPE_HI_HI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (sssubsi3, ksubw, RISCV_SI_FTYPE_SI_SI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (kwmmul, kwmmul, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kwmmul_round, kwmmul_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (kwmmul_64, kwmmul, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kwmmul64_round, kwmmul_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kwmmul_64, v_kwmmul, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kwmmul64_round, v_kwmmul_u, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (maddr32, maddr32, RISCV_SI_FTYPE_SI_SI_SI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (msubr32, msubr32, RISCV_SI_FTYPE_SI_SI_SI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (pbsadsi, pbsad, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pbsadasi, pbsada, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pbsadsi, v_pbsad, RISCV_USI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pbsadasi, v_pbsada, RISCV_USI_FTYPE_USI_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pbsaddi, pbsad, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pbsadadi, pbsada, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pbsaddi, v64_pbsad, RISCV_UIXLEN_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pbsadadi, v64_pbsada, RISCV_UIXLEN_FTYPE_UIXLEN_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbbv2hi, pkbb16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pkbtv2hi, pkbt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pktbv2hi, pktb16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pkttv2hi, pktt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pkbbv2hi, v_pkbb16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pkbtv2hi, v_pkbt16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pktbv2hi, v_pktb16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pkttv2hi, v_pktt16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (pkbb64, pkbb16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbt64, pkbt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pktb64, pktb16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pktt64, pktt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbb64, v64_pkbb16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbt64, v64_pkbt16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pktb64, v64_pktb16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pktt64, v64_pktt16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (raddv4qi3, radd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (raddv4qi3, v_radd8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (raddv8qi3, radd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (raddv8qi3, v64_radd8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (raddv2hi3, radd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (raddv2hi3, v_radd16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (raddv4hi3, radd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (raddv4hi3, v64_radd16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (raddsi3, raddw, RISCV_SI_FTYPE_SI_SI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (rcrasv2hi, rcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rcrasv2hi, v_rcras16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rcras16_64, rcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rcras16_64, v64_rcras16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rcrsav2hi, rcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rcrsav2hi, v_rcrsa16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rcrsa16_64, rcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rcrsa16_64, v64_rcrsa16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rdovsi, rdov, RISCV_UIXLEN_FTYPE_VOID, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rdovdi, rdov, RISCV_UIXLEN_FTYPE_VOID, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstasv2hi, rstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rstasv2hi, v_rstas16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rstas16_64, rstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstas16_64, v64_rstas16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstsav2hi, rstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rstsav2hi, v_rstsa16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rstsa16_64, rstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstsa16_64, v64_rstsa16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rsubv4qi3, rsub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rsubv4qi3, v_rsub8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rsubv8qi3, rsub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rsubv8qi3, v64_rsub8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rsubv2hi3, rsub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rsubv4hi3, rsub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rsubv2hi3, v_rsub16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (rsubv4hi3, v64_rsub16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rsubsi3, rsubw, RISCV_SI_FTYPE_SI_SI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (sclip8v4qi, sclip8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sclip8v4qi, v_sclip8, RISCV_V4QI_FTYPE_V4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sclip8v8qi, sclip8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sclip8v8qi, v64_sclip8, RISCV_V8QI_FTYPE_V8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sclip16v2hi, sclip16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sclip16v2hi, v_sclip16, RISCV_V2HI_FTYPE_V2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sclip16v4hi, sclip16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sclip16v4hi, v64_sclip16, RISCV_V4HI_FTYPE_V4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sclip32sisi, sclip32, RISCV_IXLEN_FTYPE_IXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sclip32v2sidi, sclip32, RISCV_IXLEN_FTYPE_IXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sclip32v2sidi, v_sclip32, RISCV_V2SI_FTYPE_V2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmplev4qi, scmple8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmplev4qi, v_scmple8, RISCV_UV4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmplev8qi, scmple8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmplev8qi, v64_scmple8, RISCV_UV8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmplev2hi, scmple16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmplev2hi, v_scmple16, RISCV_UV2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmplev4hi, scmple16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmplev4hi, v64_scmple16, RISCV_UV4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv4qi, scmplt8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv4qi, v_scmplt8, RISCV_UV4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv8qi, scmplt8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv8qi, v64_scmplt8, RISCV_UV8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv2hi, scmplt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv2hi, v_scmplt16, RISCV_UV2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv4hi, scmplt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (scmpltv4hi, v64_scmplt16, RISCV_UV4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashlv4qi3, sll8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashlv4qi3, v_sll8, RISCV_UV4QI_FTYPE_UV4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashlv8qi3, sll8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashlv8qi3, v64_sll8, RISCV_UV8QI_FTYPE_UV8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashlv2hi3, sll16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashlv2hi3, v_sll16, RISCV_UV2HI_FTYPE_UV2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashlv4hi3, sll16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashlv4hi3, v64_sll16, RISCV_UV4HI_FTYPE_UV4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaqa, smaqa, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smaqa, v_smaqa, RISCV_SI_FTYPE_SI_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smaqa64, smaqa, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaqa64, v64_smaqa, RISCV_V2SI_FTYPE_V2SI_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sumaqa, smaqa_su, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sumaqa, v_smaqa_su, RISCV_SI_FTYPE_SI_V4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sumaqa64, smaqa_su, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sumaqa64, v64_smaqa_su, RISCV_V2SI_FTYPE_V2SI_V8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaxv4qi3, smax8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smaxv4qi3, v_smax8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smaxv8qi3, smax8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaxv8qi3, v64_smax8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaxv2hi3, smax16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smaxv2hi3, v_smax16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smaxv4hi3, smax16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaxv4hi3, v64_smax16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbb, smbb16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smbt, smbt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smtt, smtt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smbb, v_smbb16, RISCV_SI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smbt, v_smbt16, RISCV_SI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smtt, v_smtt16, RISCV_SI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smbb64, smbb16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbt64, smbt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smtt64, smtt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbb64, v64_smbb16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbt64, v64_smbt16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smtt64, v64_smtt16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smds, smds, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smds, v_smds, RISCV_SI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smds64, smds, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smds64, v64_smds, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smdrs, smdrs, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smdrs, v_smdrs, RISCV_SI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smdrs64, smdrs, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smdrs64, v64_smdrs, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smxdsv, smxds, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smxdsv, v_smxds, RISCV_SI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smxds64, smxds, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smxds64, v64_smxds, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sminv4qi3, smin8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sminv4qi3, v_smin8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sminv8qi3, smin8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sminv8qi3, v64_smin8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sminv2hi3, smin16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sminv2hi3, v_smin16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sminv4hi3, smin16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sminv4hi3, v64_smin16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smulsi3_highpart, smmul, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smulv2si3_highpart, smmul, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smulv2si3_highpart, v_smmul, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmul_round, smmul_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmulv2si3_round, smmul_u, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmulv2si3_round, v_smmul_u, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwb, smmwb, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwb_round, smmwb_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwb, v_smmwb, RISCV_IXLEN_FTYPE_IXLEN_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwb_round, v_smmwb_u, RISCV_IXLEN_FTYPE_IXLEN_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwb64, smmwb, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwb64_round, smmwb_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwb64, v64_smmwb, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwb64_round, v64_smmwb_u, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwt, smmwt, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwt_round, smmwt_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwt, v_smmwt, RISCV_IXLEN_FTYPE_IXLEN_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwt_round, v_smmwt_u, RISCV_IXLEN_FTYPE_IXLEN_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (smmwt64, smmwt, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwt64_round, smmwt_u, RISCV_IXLEN_FTYPE_IXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwt64, v64_smmwt, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smmwt64_round, v64_smmwt_u, RISCV_V2SI_FTYPE_V2SI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sraiu, sra_u, RISCV_IXLEN_FTYPE_IXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sraiu64, sra_u, RISCV_IXLEN_FTYPE_IXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashrv4qi3, sra8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sra8_roundv4qi, sra8_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashrv4qi3, v_sra8, RISCV_V4QI_FTYPE_V4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sra8_roundv4qi, v_sra8_u, RISCV_V4QI_FTYPE_V4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashrv8qi3, sra8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sra8_roundv8qi, sra8_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashrv8qi3, v64_sra8, RISCV_V8QI_FTYPE_V8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sra8_roundv8qi, v64_sra8_u, RISCV_V8QI_FTYPE_V8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashrv2hi3, sra16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sra16_roundv2hi, sra16_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashrv2hi3, v_sra16, RISCV_V2HI_FTYPE_V2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sra16_roundv2hi, v_sra16_u, RISCV_V2HI_FTYPE_V2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ashrv4hi3, sra16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sra16_roundv4hi, sra16_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashrv4hi3, v64_sra16, RISCV_V4HI_FTYPE_V4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sra16_roundv4hi, v64_sra16_u, RISCV_V4HI_FTYPE_V4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (lshrv4qi3, srl8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (srl8_roundv4qi, srl8_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (lshrv4qi3, v_srl8, RISCV_UV4QI_FTYPE_UV4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (srl8_roundv4qi, v_srl8_u, RISCV_UV4QI_FTYPE_UV4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (lshrv8qi3, srl8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (srl8_roundv8qi, srl8_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (lshrv8qi3, v64_srl8, RISCV_UV8QI_FTYPE_UV8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (srl8_roundv8qi, v64_srl8_u, RISCV_UV8QI_FTYPE_UV8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (lshrv2hi3, srl16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (srl16_roundv2hi, srl16_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (lshrv2hi3, v_srl16, RISCV_UV2HI_FTYPE_UV2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (srl16_roundv2hi, v_srl16_u, RISCV_UV2HI_FTYPE_UV2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (lshrv4hi3, srl16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (srl16_roundv4hi, srl16_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (lshrv4hi3, v64_srl16, RISCV_UV4HI_FTYPE_UV4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (srl16_roundv4hi, v64_srl16_u, RISCV_UV4HI_FTYPE_UV4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stasv2hi, stas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (stasv2hi, v_ustas16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (stasv2hi, v_sstas16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (stas16_64, stas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stas16_64, v64_ustas16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stas16_64, v64_sstas16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stsav2hi, stsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (stsav2hi, v_ustsa16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (stsav2hi, v_sstsa16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (stsa16_64, stsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stsa16_64, v64_ustsa16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stsa16_64, v64_sstsa16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv4qi3, sub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (subv4qi3, v_usub8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (subv4qi3, v_ssub8, RISCV_V4QI_FTYPE_V4QI_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (subv8qi3, sub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv8qi3, v64_usub8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv8qi3, v64_ssub8, RISCV_V8QI_FTYPE_V8QI_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv2hi3, sub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (subv2hi3, v_usub16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (subv2hi3, v_ssub16, RISCV_V2HI_FTYPE_V2HI_V2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (subv4hi3, sub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv4hi3, v64_usub16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv4hi3, v64_ssub16, RISCV_V4HI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd810, sunpkd810, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd820, sunpkd820, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd830, sunpkd830, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd831, sunpkd831, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd832, sunpkd832, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd810, v_sunpkd810, RISCV_V2HI_FTYPE_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd820, v_sunpkd820, RISCV_V2HI_FTYPE_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd830, v_sunpkd830, RISCV_V2HI_FTYPE_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd831, v_sunpkd831, RISCV_V2HI_FTYPE_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd832, v_sunpkd832, RISCV_V2HI_FTYPE_V4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd810_64, sunpkd810, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd820_64, sunpkd820, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd830_64, sunpkd830, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd831_64, sunpkd831, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd832_64, sunpkd832, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd810_64, v64_sunpkd810, RISCV_V4HI_FTYPE_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd820_64, v64_sunpkd820, RISCV_V4HI_FTYPE_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd830_64, v64_sunpkd830, RISCV_V4HI_FTYPE_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd831_64, v64_sunpkd831, RISCV_V4HI_FTYPE_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sunpkd832_64, v64_sunpkd832, RISCV_V4HI_FTYPE_V8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (bswap8, swap8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (bswap8, v_swap8, RISCV_UV4QI_FTYPE_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (bswap8_64, swap8, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (bswap8_64, v64_swap8, RISCV_UV8QI_FTYPE_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uclip8v4qi, uclip8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uclip8v4qi, v_uclip8, RISCV_UV4QI_FTYPE_V4QI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uclip8v8qi, uclip8, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uclip8v8qi, v64_uclip8, RISCV_UV8QI_FTYPE_V8QI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uclip16v2hi, uclip16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uclip16v2hi, v_uclip16, RISCV_UV2HI_FTYPE_V2HI_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uclip16v4hi, uclip16, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uclip16v4hi, v64_uclip16, RISCV_UV4HI_FTYPE_V4HI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uclip32sisi, uclip32, RISCV_UIXLEN_FTYPE_IXLEN_USI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uclip32v2sidi, uclip32, RISCV_UIXLEN_FTYPE_IXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uclip32v2sidi, v_uclip32, RISCV_UV2SI_FTYPE_V2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv4qi, ucmplt8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev4qi, ucmple8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv4qi, v_ucmplt8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev4qi, v_ucmple8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv8qi, ucmplt8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev8qi, ucmple8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv8qi, v64_ucmplt8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev8qi, v64_ucmple8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv2hi, ucmplt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev2hi, ucmple16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv2hi, v_ucmplt16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev2hi, v_ucmple16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv4hi, ucmplt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev4hi, ucmple16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmpltv4hi, v64_ucmplt16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ucmplev4hi, v64_ucmple16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv4qi3, ukadd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv4qi3, v_ukadd8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv8qi3, ukadd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv8qi3, v64_ukadd8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv2hi3, ukadd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv2hi3, v_ukadd16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv4hi3, ukadd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv4hi3, v64_ukadd16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (usaddhi3, ukaddh, RISCV_UHI_FTYPE_UHI_UHI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (usaddsi3, ukaddw, RISCV_USI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (ssaddsi3, kaddw, RISCV_SI_FTYPE_SI_SI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (ukcrasv2hi, ukcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukcrasv2hi, v_ukcras16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukcras16_64, ukcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukcras16_64, v64_ukcras16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukcrsav2hi, ukcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukcrsav2hi, v_ukcrsa16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukcrsa16_64, ukcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukcrsa16_64, v64_ukcrsa16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstasv2hi, ukstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukstasv2hi, v_ukstas16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukstas16_64, ukstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstas16_64, v64_ukstas16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstsav2hi, ukstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukstsav2hi, v_ukstsa16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ukstsa16_64, ukstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstsa16_64, v64_ukstsa16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uksubv4qi3, uksub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uksubv4qi3, v_uksub8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uksubv8qi3, uksub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uksubv8qi3, v64_uksub8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uksubv2hi3, uksub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uksubv2hi3, v_uksub16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uksubv4hi3, uksub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uksubv4hi3, v64_uksub16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ussubhi3, uksubh, RISCV_UHI_FTYPE_UHI_UHI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (ussubsi3, uksubw, RISCV_USI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (umaqa, umaqa, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (umaqa, v_umaqa, RISCV_USI_FTYPE_USI_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (umaqa64, umaqa, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (umaqa64, v64_umaqa, RISCV_UV2SI_FTYPE_UV2SI_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (umaxv4qi3, umax8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (umaxv4qi3, v_umax8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (umaxv8qi3, umax8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (umaxv8qi3, v64_umax8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (umaxv2hi3, umax16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (umaxv2hi3, v_umax16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (umaxv4hi3, umax16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (umaxv4hi3, v64_umax16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uminv4qi3, umin8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uminv4qi3, v_umin8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uminv8qi3, umin8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uminv8qi3, v64_umin8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uminv2hi3, umin16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uminv2hi3, v_umin16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uminv4hi3, umin16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uminv4hi3, v64_umin16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uraddv4qi3, uradd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uraddv4qi3, v_uradd8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uraddv8qi3, uradd8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uraddv8qi3, v64_uradd8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uraddv2hi3, uradd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uraddv2hi3, v_uradd16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (uraddv4hi3, uradd16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uraddv4hi3, v64_uradd16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uraddsi3, uraddw, RISCV_USI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (urcrasv2hi, urcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urcrasv2hi, v_urcras16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urcras16_64, urcras16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urcras16_64, v64_urcras16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urcrsav2hi, urcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urcrsav2hi, v_urcrsa16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urcrsa16_64, urcrsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urcrsa16_64, v64_urcrsa16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstasv2hi, urstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urstasv2hi, v_urstas16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urstas16_64, urstas16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstas16_64, v64_urstas16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstsav2hi, urstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urstsav2hi, v_urstsa16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (urstsa16_64, urstsa16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstsa16_64, v64_urstsa16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ursubv4qi3, ursub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ursubv4qi3, v_ursub8, RISCV_UV4QI_FTYPE_UV4QI_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ursubv8qi3, ursub8, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ursubv8qi3, v64_ursub8, RISCV_UV8QI_FTYPE_UV8QI_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ursubv2hi3, ursub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ursubv2hi3, v_ursub16, RISCV_UV2HI_FTYPE_UV2HI_UV2HI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (ursubv4hi3, ursub16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ursubv4hi3, v64_ursub16, RISCV_UV4HI_FTYPE_UV4HI_UV4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ursubsi3, ursubw, RISCV_USI_FTYPE_USI_USI, zpn),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd810, zunpkd810, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd820, zunpkd820, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd830, zunpkd830, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd831, zunpkd831, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd832, zunpkd832, RISCV_UIXLEN_FTYPE_UIXLEN, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd810, v_zunpkd810, RISCV_UV2HI_FTYPE_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd820, v_zunpkd820, RISCV_UV2HI_FTYPE_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd830, v_zunpkd830, RISCV_UV2HI_FTYPE_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd831, v_zunpkd831, RISCV_UV2HI_FTYPE_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd832, v_zunpkd832, RISCV_UV2HI_FTYPE_UV4QI, zpn32),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd810_64, zunpkd810, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd820_64, zunpkd820, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd830_64, zunpkd830, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd831_64, zunpkd831, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd832_64, zunpkd832, RISCV_UIXLEN_FTYPE_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd810_64, v64_zunpkd810, RISCV_UV4HI_FTYPE_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd820_64, v64_zunpkd820, RISCV_UV4HI_FTYPE_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd830_64, v64_zunpkd830, RISCV_UV4HI_FTYPE_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd831_64, v64_zunpkd831, RISCV_UV4HI_FTYPE_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (zunpkd832_64, v64_zunpkd832, RISCV_UV4HI_FTYPE_UV8QI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv2si3, add32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv2si3, v_uadd32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (addv2si3, v_sadd32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crasv2si, cras32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crasv2si, v_ucras32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crasv2si, v_scras32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crsav2si, crsa32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crsav2si, v_ucrsa32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (crsav2si, v_scrsa32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kabsv2si2, kabs32, RISCV_DI_FTYPE_DI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kabsv2si2, v_kabs32, RISCV_V2SI_FTYPE_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kaddv2si3, kadd32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kaddv2si3, v_kadd32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kcrasv2si, kcras32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kcrasv2si, v_kcras32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kcrsav2si, kcrsa32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kcrsav2si, v_kcrsa32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmbb16, khmbb16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmbt16, khmbt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmtt16, khmtt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmbb16, kdmbb16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmbt16, kdmbt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmtt16, kdmtt16, RISCV_IXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmabb16, kdmabb16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmabt16, kdmabt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmatt16, kdmatt16, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmbb16, v_khmbb16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmbt16, v_khmbt16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (khmtt16, v_khmtt16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmbb16, v_kdmbb16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmbt16, v_kdmbt16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmtt16, v_kdmtt16, RISCV_V2SI_FTYPE_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmabb16, v_kdmabb16, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmabt16, v_kdmabt16, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kdmatt16, v_kdmatt16, RISCV_V2SI_FTYPE_V2SI_V4HI_V4HI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmabb32, kmabb32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmabt32, kmabt32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmatt32, kmatt32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmabb32, v_kmabb32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmabt32, v_kmabt32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmatt32, v_kmatt32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxda32, kmaxda32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxda32, v_kmaxda32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmda32, kmda32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmxda32, kmxda32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmda32, v_kmda32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmxda32, v_kmxda32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmads32, kmads32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmadrs32, kmadrs32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxds32, kmaxds32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmads32, v_kmads32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmadrs32, v_kmadrs32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmaxds32, v_kmaxds32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsda32, kmsda32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsxda32, kmsxda32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsda32, v_kmsda32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kmsxda32, v_kmsxda32, RISCV_IXLEN_FTYPE_IXLEN_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksll32, ksll32, RISCV_IXLEN_FTYPE_IXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksll32, v_ksll32, RISCV_V2SI_FTYPE_V2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2si, kslra32, RISCV_DI_FTYPE_DI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2si_round, kslra32_u, RISCV_DI_FTYPE_DI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2si, v_kslra32, RISCV_V2SI_FTYPE_V2SI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kslrav2si_round, v_kslra32_u, RISCV_V2SI_FTYPE_V2SI_SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstasv2si, kstas32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstasv2si, v_kstas32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstsav2si, kstsa32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (kstsav2si, v_kstsa32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksubv2si3, ksub32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ksubv2si3, v_ksub32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbbv2si, pkbb32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbtv2si, pkbt32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pktbv2si, pktb32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkttv2si, pktt32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbbv2si, v_pkbb32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkbtv2si, v_pkbt32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pktbv2si, v_pktb32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (pkttv2si, v_pktt32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (raddv2si3, radd32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (raddv2si3, v_radd32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rcrasv2si, rcras32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rcrasv2si, v_rcras32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rcrsav2si, v_rcrsa32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rcrsav2si, rcrsa32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstasv2si, rstas32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstasv2si, v_rstas32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstsav2si, rstsa32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rstsav2si, v_rstsa32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rsubv2si3, rsub32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (rsubv2si3, v_rsub32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashlv2si3, sll32, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashlv2si3, v_sll32, RISCV_UV2SI_FTYPE_UV2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaxv2si3, smax32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smaxv2si3, v_smax32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbb32, smbb32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbt32, smbt32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smtt32, smtt32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbb32, v_smbb32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smbt32, v_smbt32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smtt32, v_smtt32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smds32, smds32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smdrs32, smdrs32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smxds32, smxds32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smds32, v_smds32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smdrs32, v_smdrs32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (smxds32, v_smxds32, RISCV_IXLEN_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sminv2si3, smin32, RISCV_IXLEN_FTYPE_IXLEN_IXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sminv2si3, v_smin32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashrv2si3, v_sra32, RISCV_V2SI_FTYPE_V2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sra32_round, v_sra32_u, RISCV_V2SI_FTYPE_V2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ashrv2si3, sra32, RISCV_IXLEN_FTYPE_IXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sra32_round, sra32_u, RISCV_IXLEN_FTYPE_IXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (sraiw_u, sraw_u, RISCV_SI_FTYPE_SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (lshrv2si3, srl32, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (srl32_round, srl32_u, RISCV_UIXLEN_FTYPE_UIXLEN_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (lshrv2si3, v_srl32, RISCV_UV2SI_FTYPE_UV2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (srl32_round, v_srl32_u, RISCV_UV2SI_FTYPE_UV2SI_USI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stasv2si, stas32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stasv2si, v_ustas32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stasv2si, v_sstas32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stsav2si, stsa32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stsav2si, v_ustsa32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (stsav2si, v_sstsa32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv2si3, sub32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv2si3, v_usub32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (subv2si3, v_ssub32, RISCV_V2SI_FTYPE_V2SI_V2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv2si3, ukadd32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukaddv2si3, v_ukadd32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukcrasv2si, ukcras32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukcrsav2si, ukcrsa32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukcrasv2si, v_ukcras32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukcrsav2si, v_ukcrsa32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstasv2si, ukstas32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstasv2si, v_ukstas32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstsav2si, ukstsa32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ukstsav2si, v_ukstsa32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uksubv2si3, uksub32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uksubv2si3, v_uksub32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (umaxv2si3, umax32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (umaxv2si3, v_umax32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uminv2si3, umin32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uminv2si3, v_umin32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uraddv2si3, uradd32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (uraddv2si3, v_uradd32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urcrasv2si, urcras32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urcrasv2si, v_urcras32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urcrsav2si, urcrsa32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urcrsav2si, v_urcrsa32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstasv2si, urstas32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstasv2si, v_urstas32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstsav2si, urstsa32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (urstsav2si, v_urstsa32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ursubv2si3, ursub32, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN, zpn64),
+DIRECT_BUILTIN_NO_PREFIX (ursubv2si3, v_ursub32, RISCV_UV2SI_FTYPE_UV2SI_UV2SI, zpn64),
+
+/* zpsf subset */
+DIRECT_BUILTIN_NO_PREFIX (smal, v_smal, RISCV_DI_FTYPE_DI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smal_64, v64_smal, RISCV_DI_FTYPE_DI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smal, smal, RISCV_DI_FTYPE_DI_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smal_64, smal, RISCV_DI_FTYPE_DI_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (adddi3, sadd64, RISCV_DI_FTYPE_DI_DI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (adddi3, uadd64, RISCV_UDI_FTYPE_UDI_UDI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (radddi3, radd64, RISCV_DI_FTYPE_DI_DI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (uradddi3, uradd64, RISCV_UDI_FTYPE_UDI_UDI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (rvp_kadddi3, kadd64, RISCV_DI_FTYPE_DI_DI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (rvp_ukadddi3, ukadd64, RISCV_UDI_FTYPE_UDI_UDI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (subdi3, ssub64, RISCV_DI_FTYPE_DI_DI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (subdi3, usub64, RISCV_UDI_FTYPE_UDI_UDI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (rsubdi3, rsub64, RISCV_DI_FTYPE_DI_DI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (ursubdi3, ursub64, RISCV_UDI_FTYPE_UDI_UDI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (rvp_ksubdi3, ksub64, RISCV_DI_FTYPE_DI_DI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (rvp_uksubdi3, uksub64, RISCV_UDI_FTYPE_UDI_UDI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (maddsidi4, smar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vsmar64_1, smar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vsmar64_1, v_smar64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (msubsidi4, smsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vsmsr64, smsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vsmsr64, v_smsr64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (umaddsidi4, umar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vumar64_1, umar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vumar64_1, v_umar64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (umsubsidi4, umsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vumsr64, umsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vumsr64, v_umsr64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (ssmaddsidi4, kmar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vkmar64, kmar64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vkmar64, v_kmar64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (usmaddsidi4, ukmar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vukmar64, ukmar64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vukmar64, v_ukmar64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (ssmsubsidi4, kmsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vkmsr64, kmsr64, RISCV_DI_FTYPE_DI_IXLEN_IXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vkmsr64, v_kmsr64, RISCV_DI_FTYPE_DI_V2SI_V2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (usmsubsidi4, ukmsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (vukmsr64, ukmsr64, RISCV_UDI_FTYPE_UDI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (vukmsr64, v_ukmsr64, RISCV_UDI_FTYPE_UDI_UV2SI_UV2SI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalbb, smalbb, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalbt, smalbt, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smaltt, smaltt, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalbb64, smalbb, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalbt64, smalbt, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smaltt64, smaltt, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalbb, v_smalbb, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalbt, v_smalbt, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smaltt, v_smaltt, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalbb64, v64_smalbb, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalbt64, v64_smalbt, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smaltt64, v64_smaltt, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalda1, smalda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalda64, smalda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalda1, v_smalda, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalda64, v64_smalda, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalxda1, smalxda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalxda64, smalxda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalxda1, v_smalxda, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalxda64, v64_smalxda, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalds1, smalds, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smaldrs3, smaldrs, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalxds1, smalxds, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalds64, smalds, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smaldrs64, smaldrs, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalxds64, smalxds, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalds1, v_smalds, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smaldrs3, v_smaldrs, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalxds1, v_smalxds, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smalds64, v64_smalds, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smaldrs64, v64_smaldrs, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smalxds64, v64_smalxds, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smslxda1, smslxda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smslxda64, smslxda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smslxda1, v_smslxda, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smslxda64, v64_smslxda, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smslda1, smslda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smslda64, smslda, RISCV_DI_FTYPE_DI_UIXLEN_UIXLEN, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smslda1, v_smslda, RISCV_DI_FTYPE_DI_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smslda64, v64_smslda, RISCV_DI_FTYPE_DI_V4HI_V4HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (umulsidi3, mulr64, RISCV_UDI_FTYPE_USI_USI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (mulsidi3, mulsr64, RISCV_DI_FTYPE_SI_SI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (umul8, umul8, RISCV_UDI_FTYPE_USI_USI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (umul8, v_umul8, RISCV_UV4HI_FTYPE_UV4QI_UV4QI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (umulx8, umulx8, RISCV_UDI_FTYPE_USI_USI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (umulx8, v_umulx8, RISCV_UV4HI_FTYPE_UV4QI_UV4QI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (umul16, umul16, RISCV_UDI_FTYPE_USI_USI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (umul16_64, umul16, RISCV_UDI_FTYPE_USI_USI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (umul16, v_umul16, RISCV_UV2SI_FTYPE_UV2HI_UV2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (umul16_64, v_umul16, RISCV_UV2SI_FTYPE_UV2HI_UV2HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (umulx16, umulx16, RISCV_UDI_FTYPE_USI_USI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (umulx16_64, umulx16, RISCV_UDI_FTYPE_USI_USI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (umulx16, v_umulx16, RISCV_UV2SI_FTYPE_UV2HI_UV2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (umulx16_64, v_umulx16, RISCV_UV2SI_FTYPE_UV2HI_UV2HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smul8, smul8, RISCV_UDI_FTYPE_USI_USI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (smul8, v_smul8, RISCV_V4HI_FTYPE_V4QI_V4QI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (smulx8, smulx8, RISCV_UDI_FTYPE_USI_USI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (smulx8, v_smulx8, RISCV_V4HI_FTYPE_V4QI_V4QI, zpsf),
+DIRECT_BUILTIN_NO_PREFIX (smul16, smul16, RISCV_DI_FTYPE_USI_USI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smul16_64, smul16, RISCV_DI_FTYPE_USI_USI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smul16, v_smul16, RISCV_V2SI_FTYPE_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smul16_64, v64_smul16, RISCV_V2SI_FTYPE_V2HI_V2HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smulx16, smulx16, RISCV_DI_FTYPE_USI_USI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smulx16_64, smulx16, RISCV_DI_FTYPE_USI_USI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (smulx16, v_smulx16, RISCV_V2SI_FTYPE_V2HI_V2HI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (smulx16_64, v_smulx16, RISCV_V2SI_FTYPE_V2HI_V2HI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (wext, wext, RISCV_IXLEN_FTYPE_UDI_USI, zpsf32),
+DIRECT_BUILTIN_NO_PREFIX (wext64, wext, RISCV_IXLEN_FTYPE_UDI_USI, zpsf64),
+DIRECT_BUILTIN_NO_PREFIX (revsi, rev, RISCV_UIXLEN_FTYPE_UIXLEN, zbpbo32),
+DIRECT_BUILTIN_NO_PREFIX (revdi, rev, RISCV_UIXLEN_FTYPE_UIXLEN, zbpbo64),
+DIRECT_BUILTIN_NO_PREFIX (fsrw, fsrw, RISCV_USI_FTYPE_USI_USI_USI, zbpbo64),
+DIRECT_BUILTIN_NO_PREFIX (fsr, fsr, RISCV_USI_FTYPE_USI_USI_USI, zbpbo32),
+DIRECT_BUILTIN_NO_PREFIX (cmixsi, cmix, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zbpbo32),
+DIRECT_BUILTIN_NO_PREFIX (cmixdi, cmix, RISCV_UIXLEN_FTYPE_UIXLEN_UIXLEN_UIXLEN, zbpbo64),
+DIRECT_BUILTIN_NO_PREFIX (smaxsi3, max, RISCV_SI_FTYPE_SI_SI, zbpbo32),
+DIRECT_BUILTIN_NO_PREFIX (sminsi3, min, RISCV_SI_FTYPE_SI_SI, zbpbo32),
+DIRECT_BUILTIN_NO_PREFIX (smaxdi3, max, RISCV_DI_FTYPE_DI_DI, zbpbo64),
+DIRECT_BUILTIN_NO_PREFIX (smindi3, min, RISCV_DI_FTYPE_DI_DI, zbpbo64),
diff --git a/gcc/config/riscv/riscv-builtins.c b/gcc/config/riscv/riscv-builtins.c
index d187d20e4653..0fe69e607462 100644
--- a/gcc/config/riscv/riscv-builtins.c
+++ b/gcc/config/riscv/riscv-builtins.c
@@ -36,11 +36,23 @@ along with GCC; see the file COPYING3.  If not see
 #include "stor-layout.h"
 #include "expr.h"
 #include "langhooks.h"
+#include "function.h"
+#include "emit-rtl.h"
+#include "explow.h"
 
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
 #define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
+#define RISCV_FTYPE_NAME4(A, B, C, D, E) \
+  RISCV_##A##_FTYPE_##B##_##C##_##D##_##E
+#define RISCV_FTYPE_NAME5(A, B, C, D, E, F) \
+  RISCV_##A##_FTYPE_##B##_##C##_##D##_##E##_##F
+#define RISCV_FTYPE_NAME6(A, B, C, D, E, F, G) \
+  RISCV_##A##_FTYPE_##B##_##C##_##D##_##E##_##F##_##G
+#define RISCV_FTYPE_NAME7(A, B, C, D, E, F, G, H) \
+  RISCV_##A##_FTYPE_##B##_##C##_##D##_##E##_##F##_##G##_##H
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -103,6 +115,18 @@ AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (crypto_zkr32, TARGET_ZKR && !TARGET_64BIT)
 AVAIL (crypto_zkr64, TARGET_ZKR && TARGET_64BIT)
 
+/* p ext */
+AVAIL (zpn, TARGET_ZPN)
+AVAIL (zpn64, TARGET_ZPN && TARGET_64BIT)
+AVAIL (zpn32, TARGET_ZPN && !TARGET_64BIT)
+
+AVAIL (zpsf, TARGET_ZPSF)
+AVAIL (zpsf32, TARGET_ZPSF && !TARGET_64BIT)
+AVAIL (zpsf64, TARGET_ZPSF && TARGET_64BIT)
+
+AVAIL (zbpbo32, TARGET_ZBPBO && !TARGET_64BIT)
+AVAIL (zbpbo64, TARGET_ZBPBO && TARGET_64BIT)
+
 /* Construct a riscv_builtin_description from the given arguments.
 
    INSN is the name of the associated instruction pattern, without the
@@ -132,11 +156,47 @@ AVAIL (crypto_zkr64, TARGET_ZKR && TARGET_64BIT)
   RISCV_BUILTIN (INSN, #INSN, RISCV_BUILTIN_DIRECT_NO_TARGET,		\
 		FUNCTION_TYPE, AVAIL)
 
+/* Define __builtin_riscv_<NAME>, which is a RISCV_BUILTIN_DIRECT function
+   mapped to instruction CODE_FOR_<INSN>,  FUNCTION_TYPE and AVAIL
+   are as for RISCV_BUILTIN.  */
+#define DIRECT_BUILTIN_NO_PREFIX(INSN, NAME, FUNCTION_TYPE, AVAIL)			\
+  { CODE_FOR_ ## INSN, "__builtin_riscv_" # NAME,			\
+    RISCV_BUILTIN_DIRECT, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+
+/* Define __builtin_riscv_<NAME>, which is a RISCV_BUILTIN_DIRECT_NO_TARGET function
+   mapped to instruction CODE_FOR_<INSN>,  FUNCTION_TYPE and AVAIL
+   are as for RISCV_BUILTIN.  */
+#define DIRECT_NO_TARGET_BUILTIN_NO_PREFIX(INSN, NAME, FUNCTION_TYPE, AVAIL)			\
+  { CODE_FOR_ ## INSN, "__builtin_riscv_" # NAME,			\
+    RISCV_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, riscv_builtin_avail_ ## AVAIL }
+
+/* type nodes for target-specific width support (xlen_t) */
+tree uint_xlen_node;
+tree int_xlen_node;
+
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
+#define RISCV_ATYPE_UHI unsigned_intHI_type_node
+#define RISCV_ATYPE_HI intHI_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
+#define RISCV_ATYPE_UDI unsigned_intDI_type_node
+#define RISCV_ATYPE_V4QI build_vector_type (intQI_type_node, 4)
+#define RISCV_ATYPE_UV4QI build_vector_type (unsigned_intQI_type_node, 4)
+#define RISCV_ATYPE_V8QI build_vector_type (intQI_type_node, 8)
+#define RISCV_ATYPE_UV8QI build_vector_type (unsigned_intQI_type_node, 8)
+#define RISCV_ATYPE_V2HI build_vector_type (intHI_type_node, 2)
+#define RISCV_ATYPE_UV2HI build_vector_type (unsigned_intHI_type_node, 2)
+#define RISCV_ATYPE_V4HI build_vector_type (intHI_type_node, 4)
+#define RISCV_ATYPE_UV4HI build_vector_type (unsigned_intHI_type_node, 4)
+#define RISCV_ATYPE_V2SI build_vector_type (intSI_type_node, 2)
+#define RISCV_ATYPE_UV2SI build_vector_type (unsigned_intSI_type_node, 2)
+#define RISCV_ATYPE_V8HI build_vector_type (intHI_type_node, 8)
+#define RISCV_ATYPE_UV8HI build_vector_type (unsigned_intHI_type_node, 8)
+
+#define RISCV_ATYPE_IXLEN  int_xlen_node
+#define RISCV_ATYPE_UIXLEN uint_xlen_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
    their associated RISCV_ATYPEs.  */
@@ -146,9 +206,24 @@ AVAIL (crypto_zkr64, TARGET_ZKR && TARGET_64BIT)
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
 #define RISCV_FTYPE_ATYPES2(A, B, C) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
+#define RISCV_FTYPE_ATYPES4(A, B, C, D, E) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \
+  RISCV_ATYPE_##E
+#define RISCV_FTYPE_ATYPES5(A, B, C, D, E, F) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \
+  RISCV_ATYPE_##E, RISCV_ATYPE_##F
+#define RISCV_FTYPE_ATYPES6(A, B, C, D, E, F, G) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \
+  RISCV_ATYPE_##E, RISCV_ATYPE_##F, RISCV_ATYPE_##G
+#define RISCV_FTYPE_ATYPES7(A, B, C, D, E, F, G, H) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D, \
+  RISCV_ATYPE_##E, RISCV_ATYPE_##F, RISCV_ATYPE_##G, RISCV_ATYPE_##H
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-builtins-crypto.def"
+  #include "riscv-builtins-rvp.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float)
@@ -195,6 +270,17 @@ riscv_build_function_type (enum riscv_function_type type)
 void
 riscv_init_builtins (void)
 {
+  if (TARGET_64BIT)
+    {
+      int_xlen_node  = intDI_type_node;
+      uint_xlen_node = unsigned_intDI_type_node;
+    }
+  else
+    {
+      int_xlen_node  = intSI_type_node;
+      uint_xlen_node = unsigned_intSI_type_node;
+    }
+
   for (size_t i = 0; i < ARRAY_SIZE (riscv_builtins); i++)
     {
       const struct riscv_builtin_description *d = &riscv_builtins[i];
@@ -222,10 +308,47 @@ riscv_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
    an expand operand.  Store the operand in *OP.  */
 
 static void
-riscv_prepare_builtin_arg (struct expand_operand *op, tree exp, unsigned argno)
+riscv_prepare_builtin_arg (struct expand_operand *op, tree exp, unsigned argno,
+			   enum insn_code icode, bool has_target_p)
 {
-  tree arg = CALL_EXPR_ARG (exp, argno);
-  create_input_operand (op, expand_normal (arg), TYPE_MODE (TREE_TYPE (arg)));
+  rtx arg_rtx = expand_normal (CALL_EXPR_ARG (exp, argno));
+  enum machine_mode mode = insn_data[icode].operand[argno + has_target_p].mode;
+
+  if (!(*insn_data[icode].operand[argno + has_target_p].predicate) (arg_rtx, mode))
+    {
+      rtx tmp_rtx = gen_reg_rtx (mode);
+      if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (arg_rtx)))
+	{
+	  tmp_rtx = simplify_gen_subreg (mode, arg_rtx, GET_MODE (arg_rtx), 0);
+	  arg_rtx = tmp_rtx;
+	}
+      else if (VECTOR_MODE_P (mode) && CONST_INT_P (arg_rtx))
+	{
+	  /* Handle CONST_INT covert to CONST_VECTOR.  */
+	  int nunits = GET_MODE_NUNITS (mode);
+	  int i, shift = 0;
+	  rtvec v = rtvec_alloc (nunits);
+	  HOST_WIDE_INT val = INTVAL (arg_rtx);
+	  enum machine_mode val_mode = GET_MODE_INNER (mode);
+	  int shift_acc = GET_MODE_BITSIZE (val_mode);
+	  unsigned HOST_WIDE_INT mask = GET_MODE_MASK (val_mode);
+	  HOST_WIDE_INT tmp_val = val;
+	  for (i = 0; i < nunits; i++)
+	    {
+	      tmp_val = (val >> shift) & mask;
+	      RTVEC_ELT (v, i) = gen_int_mode (tmp_val, val_mode);
+	      shift += shift_acc;
+	    }
+
+	  arg_rtx = copy_to_mode_reg (mode, gen_rtx_CONST_VECTOR (mode, v));
+	}
+      else
+	{
+	  convert_move (tmp_rtx, arg_rtx, false);
+	  arg_rtx = tmp_rtx;
+	}
+    }
+  create_input_operand (op, arg_rtx, mode);
 }
 
 /* Expand instruction ICODE as part of a built-in function sequence.
@@ -261,14 +384,28 @@ riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
 
   /* Map any target to operand 0.  */
   int opno = 0;
+  enum machine_mode insn_return_mode = insn_data[icode].operand[opno].mode;
+  enum machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
+
   if (has_target_p)
-    create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
+    {
+      /* p extension vector and scalar mode convension */
+      if ((!target
+	  || GET_MODE (target) != insn_return_mode
+	  || ! (*insn_data[icode].operand[opno].predicate) (target, insn_return_mode)))
+	{
+	  mode = insn_return_mode;
+	  target = gen_reg_rtx (mode);
+	}
+
+      create_output_operand (&ops[opno++], target, mode);
+    }
 
   /* Map the arguments to the other operands.  */
   gcc_assert (opno + call_expr_nargs (exp)
 	      == insn_data[icode].n_generator_args);
   for (int argno = 0; argno < call_expr_nargs (exp); argno++)
-    riscv_prepare_builtin_arg (&ops[opno++], exp, argno);
+    riscv_prepare_builtin_arg (&ops[opno++], exp, argno, icode, has_target_p);
 
   return riscv_expand_builtin_insn (icode, opno, ops, has_target_p);
 }
diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index c600badb313b..92375d5dfe0d 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -52,6 +52,13 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_DIV && TARGET_MUL)
     builtin_define ("__riscv_muldiv");
 
+  if (TARGET_ZPN)
+    builtin_define ("__riscv_zpn");
+  if (TARGET_ZPSF)
+    builtin_define ("__riscv_zpsf");
+  if (TARGET_ZBPBO)
+    builtin_define ("__riscv_zbpbo");
+
   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
   if (TARGET_HARD_FLOAT)
     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 7d27530d2464..5dcb89e5ad6f 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -30,8 +30,131 @@ DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (0, (SI))
 DEF_RISCV_FTYPE (0, (DI))
 DEF_RISCV_FTYPE (1, (VOID, USI))
-DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
-DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (1, (SI, SI))
+DEF_RISCV_FTYPE (1, (UIXLEN, IXLEN))
+DEF_RISCV_FTYPE (1, (UIXLEN, UIXLEN))
+DEF_RISCV_FTYPE (1, (UIXLEN, VOID))
+DEF_RISCV_FTYPE (1, (UV2HI, UV2HI))
+DEF_RISCV_FTYPE (1, (UV2HI, UV4QI))
+DEF_RISCV_FTYPE (1, (UV2HI, V2HI))
+DEF_RISCV_FTYPE (1, (UV2SI, UV2SI))
+DEF_RISCV_FTYPE (1, (UV2SI, V2SI))
+DEF_RISCV_FTYPE (1, (UV4HI, UV4HI))
+DEF_RISCV_FTYPE (1, (UV4HI, UV8QI))
+DEF_RISCV_FTYPE (1, (UV4HI, V4HI))
+DEF_RISCV_FTYPE (1, (UV4QI, UV4QI))
+DEF_RISCV_FTYPE (1, (UV4QI, V4QI))
+DEF_RISCV_FTYPE (1, (UV8QI, UV8QI))
+DEF_RISCV_FTYPE (1, (UV8QI, V8QI))
+DEF_RISCV_FTYPE (1, (V2HI, V2HI))
+DEF_RISCV_FTYPE (1, (V2HI, V4QI))
+DEF_RISCV_FTYPE (1, (V2SI, V2SI))
+DEF_RISCV_FTYPE (1, (V4HI, V4HI))
+DEF_RISCV_FTYPE (1, (V4HI, V8QI))
+DEF_RISCV_FTYPE (1, (V4QI, V4QI))
+DEF_RISCV_FTYPE (1, (V8QI, V8QI))
+DEF_RISCV_FTYPE (1, (VOID, VOID))
 DEF_RISCV_FTYPE (2, (DI, DI, DI))
 DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, UIXLEN))
+DEF_RISCV_FTYPE (2, (DI, DI, USI))
+DEF_RISCV_FTYPE (2, (DI, DI, V2HI))
+DEF_RISCV_FTYPE (2, (DI, DI, V4HI))
+DEF_RISCV_FTYPE (2, (DI, USI, USI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (IXLEN, IXLEN, IXLEN))
+DEF_RISCV_FTYPE (2, (IXLEN, IXLEN, UIXLEN))
+DEF_RISCV_FTYPE (2, (IXLEN, IXLEN, USI))
+DEF_RISCV_FTYPE (2, (IXLEN, IXLEN, V2HI))
+DEF_RISCV_FTYPE (2, (IXLEN, SI, SI))
+DEF_RISCV_FTYPE (2, (IXLEN, UDI, USI))
+DEF_RISCV_FTYPE (2, (IXLEN, UIXLEN, UIXLEN))
+DEF_RISCV_FTYPE (2, (IXLEN, V2HI, V2HI))
+DEF_RISCV_FTYPE (2, (IXLEN, V2SI, V2SI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (SI, SI, USI))
+DEF_RISCV_FTYPE (2, (SI, SI, V2HI))
+DEF_RISCV_FTYPE (2, (SI, USI, USI))
+DEF_RISCV_FTYPE (2, (SI, V2HI, V2HI))
+DEF_RISCV_FTYPE (2, (UDI, UDI, UDI))
+DEF_RISCV_FTYPE (2, (UDI, USI, USI))
+DEF_RISCV_FTYPE (2, (UIXLEN, IXLEN, USI))
+DEF_RISCV_FTYPE (2, (UIXLEN, UIXLEN, SI))
+DEF_RISCV_FTYPE (2, (UIXLEN, UIXLEN, UIXLEN))
+DEF_RISCV_FTYPE (2, (UIXLEN, UIXLEN, USI))
+DEF_RISCV_FTYPE (2, (UIXLEN, UV8QI, UV8QI))
+DEF_RISCV_FTYPE (2, (USI, USI, USI))
+DEF_RISCV_FTYPE (2, (USI, UV4QI, UV4QI))
+DEF_RISCV_FTYPE (2, (UV2HI, UV2HI, USI))
+DEF_RISCV_FTYPE (2, (UV2HI, UV2HI, UV2HI))
+DEF_RISCV_FTYPE (2, (UV2HI, V2HI, USI))
+DEF_RISCV_FTYPE (2, (UV2HI, V2HI, V2HI))
+DEF_RISCV_FTYPE (2, (UV2SI, UV2HI, UV2HI))
+DEF_RISCV_FTYPE (2, (UV2SI, UV2SI, USI))
+DEF_RISCV_FTYPE (2, (UV2SI, UV2SI, UV2SI))
+DEF_RISCV_FTYPE (2, (UV2SI, V2SI, USI))
+DEF_RISCV_FTYPE (2, (UV4HI, UV4HI, USI))
+DEF_RISCV_FTYPE (2, (UV4HI, UV4HI, UV4HI))
+DEF_RISCV_FTYPE (2, (UV4HI, UV4QI, UV4QI))
+DEF_RISCV_FTYPE (2, (UV4HI, V4HI, USI))
+DEF_RISCV_FTYPE (2, (UV4HI, V4HI, V4HI))
+DEF_RISCV_FTYPE (2, (UV4QI, UV4QI, USI))
+DEF_RISCV_FTYPE (2, (UV4QI, UV4QI, UV4QI))
+DEF_RISCV_FTYPE (2, (UV4QI, V4QI, USI))
+DEF_RISCV_FTYPE (2, (UV4QI, V4QI, V4QI))
+DEF_RISCV_FTYPE (2, (UV8QI, UV8QI, USI))
+DEF_RISCV_FTYPE (2, (UV8QI, UV8QI, UV8QI))
+DEF_RISCV_FTYPE (2, (UV8QI, V8QI, USI))
+DEF_RISCV_FTYPE (2, (UV8QI, V8QI, V8QI))
+DEF_RISCV_FTYPE (2, (V2HI, V2HI, SI))
+DEF_RISCV_FTYPE (2, (V2HI, V2HI, USI))
+DEF_RISCV_FTYPE (2, (V2HI, V2HI, V2HI))
+DEF_RISCV_FTYPE (2, (V2SI, V2HI, V2HI))
+DEF_RISCV_FTYPE (2, (V2SI, V2SI, SI))
+DEF_RISCV_FTYPE (2, (V2SI, V2SI, USI))
+DEF_RISCV_FTYPE (2, (V2SI, V2SI, V2SI))
+DEF_RISCV_FTYPE (2, (V2SI, V2SI, V4HI))
+DEF_RISCV_FTYPE (2, (V2SI, V4HI, V4HI))
+DEF_RISCV_FTYPE (2, (V4HI, V4HI, SI))
+DEF_RISCV_FTYPE (2, (V4HI, V4HI, USI))
+DEF_RISCV_FTYPE (2, (V4HI, V4HI, V4HI))
+DEF_RISCV_FTYPE (2, (V4HI, V4QI, V4QI))
+DEF_RISCV_FTYPE (2, (V4QI, V4QI, SI))
+DEF_RISCV_FTYPE (2, (V4QI, V4QI, USI))
+DEF_RISCV_FTYPE (2, (V4QI, V4QI, V4QI))
+DEF_RISCV_FTYPE (2, (V8QI, V8QI, SI))
+DEF_RISCV_FTYPE (2, (V8QI, V8QI, USI))
+DEF_RISCV_FTYPE (2, (V8QI, V8QI, V8QI))
+DEF_RISCV_FTYPE (2, (HI, HI, HI))
+DEF_RISCV_FTYPE (2, (UHI, UHI, UHI))
+DEF_RISCV_FTYPE (3, (DI, DI, IXLEN, IXLEN))
+DEF_RISCV_FTYPE (3, (DI, DI, UIXLEN, UIXLEN))
+DEF_RISCV_FTYPE (3, (DI, DI, V2HI, V2HI))
+DEF_RISCV_FTYPE (3, (DI, DI, V2SI, V2SI))
+DEF_RISCV_FTYPE (3, (DI, DI, V4HI, V4HI))
+DEF_RISCV_FTYPE (3, (IXLEN, IXLEN, IXLEN, IXLEN))
+DEF_RISCV_FTYPE (3, (IXLEN, IXLEN, IXLEN, UIXLEN))
+DEF_RISCV_FTYPE (3, (IXLEN, IXLEN, UIXLEN, UIXLEN))
+DEF_RISCV_FTYPE (3, (IXLEN, IXLEN, V2HI, V2HI))
+DEF_RISCV_FTYPE (3, (IXLEN, IXLEN, V2SI, V2SI))
+DEF_RISCV_FTYPE (3, (SI, IXLEN, V2HI, V2HI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, V2HI))
+DEF_RISCV_FTYPE (3, (SI, SI, USI, USI))
+DEF_RISCV_FTYPE (3, (SI, SI, V2HI, V2HI))
+DEF_RISCV_FTYPE (3, (SI, SI, V4QI, UV4QI))
+DEF_RISCV_FTYPE (3, (SI, SI, V4QI, V4QI))
+DEF_RISCV_FTYPE (3, (UDI, UDI, UIXLEN, UIXLEN))
+DEF_RISCV_FTYPE (3, (UDI, UDI, UV2SI, UV2SI))
+DEF_RISCV_FTYPE (3, (UIXLEN, UIXLEN, UIXLEN, UIXLEN))
+DEF_RISCV_FTYPE (3, (UIXLEN, UIXLEN, UIXLEN, USI))
+DEF_RISCV_FTYPE (3, (UIXLEN, UIXLEN, UV8QI, UV8QI))
+DEF_RISCV_FTYPE (3, (USI, USI, USI, USI))
+DEF_RISCV_FTYPE (3, (USI, USI, UV4QI, UV4QI))
+DEF_RISCV_FTYPE (3, (UV2SI, UV2SI, UV8QI, UV8QI))
+DEF_RISCV_FTYPE (3, (V2SI, V2SI, V2SI, V2SI))
+DEF_RISCV_FTYPE (3, (V2SI, V2SI, V2SI, V4HI))
+DEF_RISCV_FTYPE (3, (V2SI, V2SI, V4HI, V4HI))
+DEF_RISCV_FTYPE (3, (V2SI, V2SI, V8QI, UV8QI))
+DEF_RISCV_FTYPE (3, (V2SI, V2SI, V8QI, V8QI))
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index d66c198b66c8..605e44d6d777 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -20,3 +20,8 @@ along with GCC; see the file COPYING3.  If not see
 <http://www.gnu.org/licenses/>.  */
 
 FLOAT_MODE (TF, 16, ieee_quad_format);
+
+/* vector mode for p extension */
+VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
+VECTOR_MODES (INT, 8);        /*            V8QI V4HI V2SI */
+VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI */
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 6ee08bc206f0..3db664ba1898 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -69,4 +69,12 @@ enum riscv_align_data {
 #define TARGET_ZKSED ((riscv_crypto_subext & MASK_ZKSED) != 0)
 #define TARGET_ZKSH ((riscv_crypto_subext & MASK_ZKSH) != 0)
 
+/* P extension subset */
+#define MASK_ZPN (1 << 0)
+#define MASK_ZBPBO (1 << 1)
+#define MASK_ZPSF (1 << 2)
+
+#define TARGET_ZPN ((riscv_rvp_subext & MASK_ZPN) != 0)
+#define TARGET_ZBPBO ((riscv_rvp_subext & MASK_ZBPBO) != 0)
+#define TARGET_ZPSF ((riscv_rvp_subext & MASK_ZPSF) != 0)
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index d489717b2a51..05a4f407f2ae 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4516,6 +4516,14 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 	!= call_used_or_fixed_reg_p (regno + i))
       return false;
 
+  /* use even/odd pair of registers in rv32 zpsf subset */
+  if (TARGET_ZPSF && !TARGET_64BIT)
+    {
+      if ((GET_MODE_CLASS (mode) == MODE_INT ||
+		GET_MODE_CLASS (mode) == MODE_VECTOR_INT) &&
+		GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DImode))
+        return !(regno & 1);
+    }
   return true;
 }
 
@@ -5253,6 +5261,27 @@ riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr)
   return new_cost <= old_cost;
 }
 
+/* return true if vector mode is supported in rvp */
+static bool
+riscv_rvp_support_vector_mode_p (machine_mode mode)
+{
+  if (mode == V2HImode || mode == V4QImode)
+    return true;
+
+  if (TARGET_64BIT
+      && (mode == V8QImode || mode == V4HImode || mode == V2SImode))
+    return true;
+
+  return false;
+}
+
+/* implement TARGET_VECTOR_MODE_SUPPORTED_P. */
+bool
+riscv_vector_mode_supported_p (enum machine_mode mode)
+{
+  return TARGET_ZPN && riscv_rvp_support_vector_mode_p (mode);
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5436,6 +5465,10 @@ riscv_new_address_profitable_p (rtx memref, rtx_insn *insn, rtx new_addr)
 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
 
+/* rvp */
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P riscv_vector_mode_supported_p
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 7d2edb63195c..d97f08cfa385 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -45,6 +45,60 @@
 
   ;; Stack tie
   UNSPEC_TIE
+
+  ;; rvp
+  UNSPEC_KABS
+  UNSPEC_KADDW
+  UNSPEC_KSUBW
+  UNSPEC_KADDH
+  UNSPEC_KSUBH
+  UNSPEC_UKADDW
+  UNSPEC_UKSUBW
+  UNSPEC_UKADDH
+  UNSPEC_UKSUBH
+  UNSPEC_BITREV
+  UNSPEC_VEC_COMPARE
+  UNSPEC_KDMABB
+  UNSPEC_KDMABT
+  UNSPEC_KDMATT
+  UNSPEC_KHMBB
+  UNSPEC_KHMBT
+  UNSPEC_KHMTT
+  UNSPEC_KDMTT
+  UNSPEC_KDMBT
+  UNSPEC_KDMBB
+  UNSPEC_KHM
+  UNSPEC_KHMX
+  UNSPEC_ROUND
+  UNSPEC_KMMWU
+  UNSPEC_KMMW
+  UNSPEC_KSLRAW
+  UNSPEC_KSLRAWU
+  UNSPEC_PBSAD
+  UNSPEC_PBSADA
+  UNSPEC_RDOV
+  UNSPEC_CLIPS
+  UNSPEC_CLIPS_OV
+  UNSPEC_SMUL8
+  UNSPEC_SMULX8
+  UNSPEC_UMUL8
+  UNSPEC_UMULX8
+  UNSPEC_SMUL16
+  UNSPEC_SMULX16
+  UNSPEC_UMUL16
+  UNSPEC_UMULX16
+  UNSPEC_ROUND64
+  UNSPEC_BSWAP
+  UNSPEC_UCLIP
+  UNSPEC_UCLIP_OV
+  UNSPEC_KDMBB16
+  UNSPEC_KDMBT16
+  UNSPEC_KDMTT16
+  UNSPEC_KHMBB16
+  UNSPEC_KHMBT16
+  UNSPEC_KHMTT16
+  UNSPEC_FSR
+  UNSPEC_FSRW
 ])
 
 (define_c_enum "unspecv" [
@@ -65,6 +119,9 @@
   UNSPECV_BLOCKAGE
   UNSPECV_FENCE
   UNSPECV_FENCE_I
+
+  ;; RVP
+  UNSPEC_CLROV
 ])
 
 (define_constants
@@ -119,7 +176,7 @@
   (const_string "unknown"))
 
 ;; Main data type used by the insn
-(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF"
+(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,V2HI,V4HI,V8HI,V4QI,V8QI,V2SI,V4SI"
   (const_string "unknown"))
 
 ;; True if the main data type is twice the size of a word.
@@ -162,10 +219,15 @@
 ;; multi	multiword sequence (or user asm statements)
 ;; nop		no operation
 ;; ghost	an instruction that produces no real code
+;; simd   simd instruction for p extension
+;; psimd  partial-simd data processing instructions
+;; dsp    instructions for increasing the DSP processing capabilities
+;; dsp64  as the same as dsp, but RV64P only
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
-   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost"
+   fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,
+   simd,psimd,dsp,dsp64"
   (cond [(eq_attr "got" "load") (const_string "load")
 
 	 ;; If a doubleword move uses these expensive instructions,
@@ -297,9 +359,9 @@
 ;; Iterator for floating-point modes that can be loaded into X registers.
 (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT")])
 
-;; This attribute gives the length suffix for a sign- or zero-extension
-;; instruction.
-(define_mode_attr size [(QI "b") (HI "h")])
+;; This attribute gives the length suffix for a sign-, zero-extension
+;; ,ksub- or kadd- instruction in RVP.
+(define_mode_attr size [(QI "b") (HI "h") (SI "w")])
 
 ;; Mode attributes for loads.
 (define_mode_attr load [(QI "lb") (HI "lh") (SI "lw") (DI "ld") (SF "flw") (DF "fld")])
@@ -453,7 +515,19 @@
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
 
-(define_insn "adddi3"
+(define_expand "adddi3"
+  [(set (match_operand:DI          0 "register_operand" "=r,r")
+	(plus:DI (match_operand:DI 1 "register_operand" " r,r")
+		 (match_operand:DI 2 "arith_operand"    " r,I")))]
+  "TARGET_64BIT || TARGET_ZPSF"
+  {
+    if (!TARGET_64BIT)
+      operands[2] = force_reg (DImode, operands[2]);
+  }
+  [(set_attr "type" "arith")
+   (set_attr "mode" "DI")])
+
+(define_insn "*adddi_rv64"
   [(set (match_operand:DI          0 "register_operand" "=r,r")
 	(plus:DI (match_operand:DI 1 "register_operand" " r,r")
 		 (match_operand:DI 2 "arith_operand"    " r,I")))]
@@ -504,8 +578,8 @@
   [(set (match_operand:DI 0            "register_operand" "= r")
 	(minus:DI (match_operand:DI 1  "reg_or_0_operand" " rJ")
 		   (match_operand:DI 2 "register_operand" "  r")))]
-  "TARGET_64BIT"
-  "sub\t%0,%z1,%2"
+  "TARGET_64BIT || TARGET_ZPSF"
+  { return TARGET_64BIT ? "sub\t%0,%z1,%2" : "sub64\t%0,%z1,%2"; }
   [(set_attr "type" "arith")
    (set_attr "mode" "DI")])
 
@@ -709,11 +783,18 @@
 		   (match_operand:SI 2 "register_operand" " r"))))]
   "TARGET_MUL && !TARGET_64BIT"
 {
-  rtx temp = gen_reg_rtx (SImode);
-  emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
-  emit_insn (gen_<u>mulsi3_highpart (riscv_subword (operands[0], true),
-				     operands[1], operands[2]));
-  emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
+  if (TARGET_ZPN)
+    {
+      emit_insn (gen_rvp_<u>mulsidi3 (operands[0], operands[1], operands[2]));
+    }
+  else
+    {
+      rtx temp = gen_reg_rtx (SImode);
+      emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
+      emit_insn (gen_<u>mulsi3_highpart (riscv_subword (operands[0], true),
+                operands[1], operands[2]));
+      emit_insn (gen_movsi (riscv_subword (operands[0], false), temp));
+    }
   DONE;
 })
 
@@ -2499,6 +2580,7 @@
 )
 
 (include "crypto.md")
+(include "rvp.md")
 
 ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a
 ;; 32-bit target when using -mtune=sifive-7-series.  The first sched pass
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index cd4807c1d27d..93957db09e07 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -158,3 +158,6 @@ Enum(riscv_align_data) String(natural) Value(riscv_align_data_type_natural)
 
 TargetVariable
 int riscv_crypto_subext
+
+TargetVariable
+int riscv_rvp_subext
diff --git a/gcc/config/riscv/rvp.md b/gcc/config/riscv/rvp.md
new file mode 100644
index 000000000000..0b552f9bb141
--- /dev/null
+++ b/gcc/config/riscv/rvp.md
@@ -0,0 +1,6912 @@
+;; Machine description for P extension.
+;; Copyright (C) 2021 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; A list of the modes that are up to one word long vector.
+(define_mode_iterator VECI [(V4QI "!TARGET_64BIT") (V2HI "!TARGET_64BIT")
+                            (V8QI "TARGET_64BIT") (V4HI "TARGET_64BIT")
+			                      (V2SI "TARGET_64BIT")])
+;; v2hi, v4qi is also used in rv64p
+(define_mode_iterator VPMOVE [(V4QI "") (V2HI "")
+                             (V8QI "TARGET_64BIT")  (V4HI "TARGET_64BIT")])
+(define_mode_iterator VQIHI [(V4QI "!TARGET_64BIT") (V2HI "!TARGET_64BIT")
+                             (V8QI "TARGET_64BIT")  (V4HI "TARGET_64BIT")])
+(define_mode_iterator VSHI [(V2HI "!TARGET_64BIT") (V2SI "TARGET_64BIT")])
+(define_mode_iterator VHI  [(V2HI "!TARGET_64BIT") (V4HI "TARGET_64BIT")])
+(define_mode_iterator VQI [(V4QI "!TARGET_64BIT") (V8QI "TARGET_64BIT")])
+(define_mode_iterator VD_SI [(SI "!TARGET_64BIT") (V2SI "TARGET_64BIT")])
+
+;; <bits> for specific bit number in 'simd' type instruction
+(define_mode_attr bits [(V8QI "8") (V4QI "8") (QI "8") (V4HI "16") (V2HI "16")
+			            (HI "16") (V2SI "32") (DI "64")])
+
+(define_mode_attr VNHALF [(V2SI "SI") (V2HI "HI")])
+(define_mode_attr VSH_EXT [(V2SI "DI") (V2HI "HI")])
+(define_mode_attr VEXT [(V4QI "V4HI") (V2HI "V2SI") (V8QI "V8HI") (V4HI "V4SI")
+			(V2SI "V2DI")])
+
+;; clz, clrs
+(define_code_iterator unop [clrsb clz])
+
+;; add/sub iterator
+(define_code_iterator all_plus [plus ss_plus us_plus])
+(define_code_iterator all_minus [minus ss_minus us_minus])
+(define_code_iterator saturation_plus [ss_plus us_plus])
+(define_code_iterator saturation_minus [ss_minus us_minus])
+(define_code_iterator ssat_op [ss_plus ss_minus])
+(define_code_iterator usat_op [us_plus us_minus])
+(define_code_iterator plus_minus [plus minus])
+
+;; smax[8|16] and umax[8|16]
+(define_code_iterator sumax [smax umax])
+(define_code_iterator sumin [smin umin])
+
+;; rvp shift
+(define_code_attr shift [(ashift "ashl") (ashiftrt "ashr") (lshiftrt "lshr")])
+
+;; smalxd[s|a] smald[s|a]
+(define_code_attr add_sub [(plus "a")
+  (ss_plus "a")
+  (us_plus "a")
+  (ss_minus "s")
+  (us_minus "s")
+  (minus "s")])
+
+;; (un)signed unpacking patterns
+(define_code_attr zs [(sign_extend "s") (zero_extend "z")])
+
+(define_code_attr opcode [(plus "add")
+   (minus "sub")
+   (ss_plus "add")
+   (us_plus "add")
+   (ss_minus "sub")
+   (us_minus "sub")
+   (smax "smax")
+   (umax "umax")
+   (smin "smin")
+   (umin "umin")])
+
+;; <uk> expands to (un)signed (saturating) arithmetic operations
+(define_code_attr uk
+  [(plus "") (ss_plus "k") (us_plus "uk")
+   (minus "") (ss_minus "k") (us_minus "uk")])
+
+;; <rvp_optab> expands to the name of the optab for a particular code.
+(define_code_attr rvp_optab [(clrsb "clrsb")
+	(clz "clz")
+	(ashift "ashl")
+	(ashiftrt "ashr")
+	(lshiftrt "lshr")])
+
+;; <rvp_insn> expands to the name of the insn that implements a particular code.
+(define_code_attr rvp_insn [(clrsb "clrs")
+	(clz "clz")
+	(ashift "sll")
+	(ashiftrt "sra")
+	(lshiftrt "srl")])
+
+;; kabs
+(define_insn "kabsw"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_KABS))]
+  "TARGET_ZPN"
+  "kabsw\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_insn "kabs<mode>2"
+  [(set (match_operand:VECI 0 "register_operand"              "=r")
+	(ss_abs:VECI (match_operand:VECI 1 "register_operand" " r")))]
+  "TARGET_ZPN"
+  "kabs<bits>\t%0, %1"
+  [(set_attr "type"   "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; k|(uk)|? add
+(define_insn "<uk>add<mode>3"
+  [(set (match_operand:VECI 0 "register_operand"                "=r")
+	(all_plus:VECI (match_operand:VECI 1 "register_operand" " r")
+		       (match_operand:VECI 2 "register_operand" " r")))]
+  "TARGET_ZPN"
+  "<uk>add<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; add64/sub64
+(define_insn "*add64_rvp"
+  [(set (match_operand:DI          0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" " r")
+		 (match_operand:DI 2 "register_operand" " r")))]
+  "!TARGET_64BIT && TARGET_ZPSF"
+  "add64\t%0,%1,%2"
+  [(set_attr "type" "arith")
+   (set_attr "mode" "DI")])
+
+;; rv64
+(define_insn "rvp_<uk>adddi3"
+  [(set (match_operand:DI 0 "register_operand"              "=r")
+	(saturation_plus:DI (match_operand:DI 1 "register_operand" " r")
+		     (match_operand:DI 2 "register_operand" " r")))]
+  "TARGET_ZPSF"
+  "<uk>add64 %0, %1, %2"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; k|(uk)|? sub
+(define_insn "<uk>sub<mode>3"
+  [(set (match_operand:VECI 0 "register_operand"                  "=r")
+	(all_minus:VECI (match_operand:VECI 1 "register_operand" " r")
+			(match_operand:VECI 2 "register_operand" " r")))]
+  "TARGET_ZPN"
+  "<uk>sub<bits> %0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; rv64
+(define_insn "rvp_<uk>subdi3"
+  [(set (match_operand:DI 0 "register_operand"               "=r")
+	(saturation_minus:DI (match_operand:DI 1 "register_operand" " r")
+		      (match_operand:DI 2 "register_operand" " r")))]
+  "TARGET_ZPSF"
+  "<uk>sub64 %0, %1, %2"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; uk|k add|sub w|h
+(define_code_iterator sat_op [ss_plus us_plus ss_minus us_minus])
+(define_code_attr us [(ss_plus "s") (us_plus "u") (ss_minus "s") (us_minus "u")])
+
+(define_insn "<us>s<opcode><HISI:mode>3"
+  [(set (match_operand:HISI 0 "register_operand"               "=r")
+	(sat_op:HISI (match_operand:HISI 1 "register_operand"  " r")
+		     (match_operand:HISI 2 "register_operand"  " r")))]
+  "TARGET_ZPN"
+  "<uk><opcode><HISI:size>\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "<MODE>")])
+
+;; ave
+(define_insn "ave"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(truncate:SI
+	  (ashiftrt:DI
+	    (plus:DI
+	      (plus:DI
+		(sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+		(sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
+	      (const_int 1))
+	  (const_int 1))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "ave\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_insn "avedi"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(truncate:DI
+	  (ashiftrt:TI
+	    (plus:TI
+	      (plus:TI
+		(sign_extend:TI (match_operand:DI 1 "register_operand" "r"))
+		(sign_extend:TI (match_operand:DI 2 "register_operand" "r")))
+	      (const_int 1))
+	  (const_int 1))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "ave\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "DI")])
+
+;; bitrev
+(define_insn "bitrevsi"
+  [(set (match_operand:SI 0 "register_operand"             "=r,   r")
+	(unspec:SI [(match_operand:SI 1 "register_operand" " r,   r")
+		    (match_operand:SI 2 "rimm5u_operand"   " r, u05")]
+		   UNSPEC_BITREV))]
+  "TARGET_ZPN && !TARGET_64BIT && !TARGET_ZBPBO"
+  "@
+   bitrev\t%0, %1, %2
+   bitrevi\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "SI")])
+
+(define_insn "bitrevdi"
+  [(set (match_operand:DI 0 "register_operand"             "=r,   r")
+	(unspec:DI [(match_operand:DI 1 "register_operand" " r,   r")
+		    (match_operand:SI 2 "rimm6u_operand"   " r, u06")]
+		   UNSPEC_BITREV))]
+  "TARGET_ZPN && TARGET_64BIT && !TARGET_ZBPBO"
+  "@
+   bitrev\t%0, %1, %2
+   bitrevi\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "SI")])
+
+;; cmix
+(define_insn "cmix<X:mode>"
+  [(set (match_operand:X 0 "register_operand"       "=r")
+	  (ior:X
+	    (and:X
+	      (match_operand:X 1 "register_operand" " r")
+	      (match_operand:X 3 "register_operand" " r"))
+	    (and:X
+	      (match_operand:X 2 "register_operand" " r")
+	      (not:X (match_dup 3)))))]
+  "TARGET_ZBPBO"
+  "cmix\t%0, %3, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "<MODE>")])
+
+;; clrov
+(define_insn "clrov<X:mode>"
+  [(unspec_volatile:X [(const_int 0)] UNSPEC_CLROV)]
+  "TARGET_ZPN"
+  "csrrci zero, vxsat, 1"
+  [(set_attr "mode" "<MODE>")])
+
+;; clrs, clz
+(define_insn "<rvp_optab><mode>2"
+  [(set (match_operand:VECI 0 "register_operand" "=r")
+        (unop:VECI (match_operand:VECI 1 "register_operand" "r")))]
+  "TARGET_ZPN"
+  "<rvp_insn><bits>\t%0, %1"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; clrs32, clz32
+(define_insn "clrsbsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (clrsb:SI (match_operand:SI 1 "register_operand" "r")))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "clrs32\t%0, %1"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "SI")])
+
+(define_insn "clzsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (clz:SI (match_operand:SI 1 "register_operand" "r")))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  { return TARGET_ZBPBO ? "clz\t%0, %1" : "clz32\t%0, %1"; }
+  [(set_attr "type" "simd")
+   (set_attr "mode" "SI")])
+
+;; simd integer compare equal
+(define_insn "cmpeq<mode>"
+  [(set (match_operand:VQIHI 0 "register_operand"                          "=r")
+	(unspec:VQIHI [(eq:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
+				 (match_operand:VQIHI 2 "register_operand" " r"))]
+		       UNSPEC_VEC_COMPARE))]
+  "TARGET_ZPN"
+  "cmpeq<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; cras, crsa
+(define_expand "cras<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_cras<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "cras<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 1)]))))
+	  (vec_duplicate:VSHI
+	    (plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "cras<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "cras16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_cras16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "cras16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (minus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				     (parallel [(const_int 0)]))
+		      (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				     (parallel [(const_int 1)])))
+	    (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+		     (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+	  (vec_concat:V2HI
+	    (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		      (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+	    (plus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+		      (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "cras16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "crsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_crsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "crsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "crsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "crsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_crsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "crsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (plus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				    (parallel [(const_int 0)]))
+		     (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 1)])))
+	    (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+		      (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+	  (vec_concat:V2HI
+	    (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		     (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+	    (minus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+		       (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "crsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; kcras, kcrsa
+(define_expand "kcras<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kcras<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kcras<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (ss_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 1)]))))
+	  (vec_duplicate:VSHI
+	    (ss_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "kcras<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "kcras16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kcras16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kcras16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (ss_minus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+					(parallel [(const_int 0)]))
+			 (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+					(parallel [(const_int 1)])))
+	    (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+	  (vec_concat:V2HI
+	    (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+	    (ss_plus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kcras16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "kcrsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kcrsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kcrsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (ss_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (ss_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "kcrsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "kcrsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kcrsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kcrsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (ss_plus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				       (parallel [(const_int 0)]))
+			(vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				       (parallel [(const_int 1)])))
+	    (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+	  (vec_concat:V2HI
+	    (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+	    (ss_minus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			  (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kcrsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; ukcras ukcrsa
+(define_expand "ukcras<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_ukcras<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukcras<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (us_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 1)]))))
+	  (vec_duplicate:VSHI
+	    (us_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "ukcras<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "ukcras16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_ukcras16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukcras16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (us_minus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+					(parallel [(const_int 0)]))
+			 (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+					(parallel [(const_int 1)])))
+	    (us_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+	  (vec_concat:V2HI
+	    (us_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+	    (us_plus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "ukcras16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "ukcrsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_ukcrsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukcrsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (us_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (us_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "ukcrsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "ukcrsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_ukcrsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukcrsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (us_plus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				       (parallel [(const_int 0)]))
+			(vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				       (parallel [(const_int 1)])))
+	    (us_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+	  (vec_concat:V2HI
+	    (us_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+	    (us_minus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			  (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "ukcrsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; rcras rcrsa
+(define_expand "rcras<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_rcras<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rcras<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+		(minus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 0)])))
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 0)])))
+		  (sign_extend:SI
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "rcras<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "rcras16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_rcras16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rcras16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 1)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "rcras16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "rcrsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_rcrsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rcrsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+	        (minus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 1)])))
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 0)])))
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "rcrsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "rcrsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_rcrsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rcrsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 1)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "rcrsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; urcras urcrsa
+(define_expand "urcras<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_urcras<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urcras<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+		(minus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 0)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 0)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "urcras<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "urcras16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_urcras16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urcras16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 1)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "urcras16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "urcrsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_urcrsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urcrsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+	        (minus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 1)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 0)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "urcrsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "urcrsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_urcrsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urcrsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 1)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "urcrsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; insb
+(define_expand "insb"
+  [(match_operand:V4QI 0 "register_operand" "")
+   (match_operand:V4QI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:SI 3 "const_int_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  if (INTVAL (operands[3]) > 3 || INTVAL (operands[3]) < 0)
+    gcc_unreachable ();
+
+  rtx src = gen_reg_rtx (QImode);
+
+  convert_move (src, operands[2], false);
+
+  HOST_WIDE_INT selector_index;
+  selector_index = INTVAL (operands[3]);
+  rtx selector = gen_int_mode (1 << selector_index, SImode);
+  emit_insn (gen_vec_setv4qi_internal (operands[0], src,
+				       operands[1], selector));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "vec_setv4qi_internal"
+  [(set (match_operand:V4QI 0 "register_operand"    "=   r,    r,    r,    r")
+	(vec_merge:V4QI
+	  (vec_duplicate:V4QI
+	    (match_operand:QI 1 "register_operand"  "    r,    r,    r,    r"))
+	  (match_operand:V4QI 2 "register_operand"  "    0,    0,    0,    0")
+	  (match_operand:SI 3 "imm_1_2_4_8_operand" " C01, C02, C04, C08")))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+   insb\t%0, %1, 0
+   insb\t%0, %1, 1
+   insb\t%0, %1, 2
+   insb\t%0, %1, 3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V4QI")])
+
+(define_expand "insb64"
+  [(match_operand:V8QI 0 "register_operand" "")
+   (match_operand:V8QI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:SI 3 "const_insb64_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  if (INTVAL (operands[3]) > 7 || INTVAL (operands[3]) < 0)
+    gcc_unreachable ();
+
+  rtx src = gen_reg_rtx (QImode);
+
+  convert_move (src, operands[2], false);
+
+  HOST_WIDE_INT selector_index;
+  selector_index = INTVAL (operands[3]);
+  rtx selector = gen_int_mode (1 << selector_index, SImode);
+  emit_insn (gen_vec_setv8qi_internal (operands[0], src,
+				       operands[1], selector));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "vec_setv8qi_internal"
+  [(set (match_operand:V8QI 0 "register_operand"    "=r")
+	(vec_merge:V8QI
+	  (vec_duplicate:V8QI
+	    (match_operand:QI 1 "register_operand"  "r"))
+	  (match_operand:V8QI 2 "register_operand"  "0")
+	  (match_operand:SI 3 "pwr_7_operand" " D07")))]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
+  return "insb\t%0, %1, %3";
+}
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V8QI")])
+
+;; KDMBB, KDMBT, KDMTT
+(define_expand "kdmbb"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kdm_internal (operands[0], operands[1], operands[2],
+				GEN_INT (0), GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "kdmbt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kdm_internal (operands[0], operands[1], operands[2],
+				GEN_INT (0), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "kdmtt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kdm_internal (operands[0], operands[1], operands[2],
+				GEN_INT (1), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "kdm_internal"
+  [(set (match_operand:SI 0 "register_operand"                      "=   r,   r,   r,   r")
+	(ashift:SI
+	  (mult:SI
+	    (sign_extend:SI
+	  (vec_select:HI
+		(match_operand:V2HI 1 "register_operand"          "   r,   r,   r,   r")
+		(parallel [(match_operand:SI 3 "imm_0_1_operand"  " C00, C00, C01, C01")])))
+	    (sign_extend:SI
+	  (vec_select:HI
+		(match_operand:V2HI 2 "register_operand"          "   r,   r,   r,   r")
+		(parallel [(match_operand:SI 4 "imm_0_1_operand"  " C00, C01, C01, C00")]))))
+	(const_int 1)))]
+  "TARGET_ZPN"
+  "@
+   kdmbb\t%0, %1, %2
+   kdmbt\t%0, %1, %2
+   kdmtt\t%0, %1, %2
+   kdmbt\t%0, %2, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+;; KDMABB, KDMABT, KDMATT
+(define_expand "kdmabb"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kdma_internal (operands[0], operands[2], operands[3],
+				GEN_INT (0), GEN_INT (0), operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "kdmabt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kdma_internal (operands[0], operands[2], operands[3],
+				GEN_INT (0), GEN_INT (1), operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "kdmatt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kdma_internal (operands[0], operands[2], operands[3],
+				GEN_INT (1), GEN_INT (1), operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "kdma_internal"
+  [(set (match_operand:SI 0 "register_operand"                      "=   r,   r,   r,   r")
+	(ss_plus:SI
+	  (ashift:SI
+	    (mult:SI
+	      (sign_extend:SI
+		(vec_select:HI
+		  (match_operand:V2HI 1 "register_operand"          "   r,   r,   r,   r")
+		  (parallel [(match_operand:SI 3 "imm_0_1_operand"  " C00, C00, C01, C01")])))
+	      (sign_extend:SI
+		(vec_select:HI
+		  (match_operand:V2HI 2 "register_operand"          "   r,   r,   r,   r")
+		  (parallel [(match_operand:SI 4 "imm_0_1_operand"  " C00, C01, C01, C00")]))))
+	    (const_int 1))
+	  (match_operand:SI 5 "register_operand"                    "   0,   0,   0,   0")))]
+  "TARGET_ZPN"
+  "@
+   kdmabb\t%0, %1, %2
+   kdmabt\t%0, %1, %2
+   kdmatt\t%0, %1, %2
+   kdmabt\t%0, %2, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+;; KHMBB, KHMBT, KHMTT
+(define_expand "khmbbsi"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_khmsi_internal (operands[0], operands[1], operands[2],
+				GEN_INT (0), GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "khmbtsi"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_khmsi_internal (operands[0], operands[1], operands[2],
+				GEN_INT (0), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "khmttsi"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_khmsi_internal (operands[0], operands[1], operands[2],
+				GEN_INT (1), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "khmsi_internal"
+  [(set (match_operand:SI 0 "register_operand"                      "=   r,   r,   r,   r")
+    (sign_extend:SI
+      (ss_truncate:QI
+	    (ashiftrt:SI
+	      (mult:SI
+	        (sign_extend:SI
+	          (vec_select:HI
+		        (match_operand:V2HI 1 "register_operand"          "   r,   r,   r,   r")
+		        (parallel [(match_operand:SI 3 "imm_0_1_operand"  " C00, C00, C01, C01")])))
+	        (sign_extend:SI
+	          (vec_select:HI
+		        (match_operand:V2HI 2 "register_operand"          "   r,   r,   r,   r")
+		        (parallel [(match_operand:SI 4 "imm_0_1_operand"  " C00, C01, C01, C00")]))))
+	    (const_int 15)))))]
+  "TARGET_ZPN"
+  "@
+   khmbb\t%0, %1, %2
+   khmbt\t%0, %1, %2
+   khmtt\t%0, %1, %2
+   khmbt\t%0, %2, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+;; KMABB, KMABT, KMATT
+(define_expand "kmabb"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
+			       GEN_INT (0), GEN_INT (0),
+			       operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmabt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
+			       GEN_INT (0), GEN_INT (1),
+			       operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmatt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kma_internal (operands[0], operands[2], operands[3],
+			       GEN_INT (1), GEN_INT (1),
+			       operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kma_internal"
+  [(set (match_operand:SI 0 "register_operand"                   "=   r,   r,   r,   r")
+	(ss_plus:SI
+	  (mult:SI
+	    (sign_extend:SI
+	      (vec_select:HI
+		(match_operand:V2HI 1 "register_operand"         "   r,   r,   r,   r")
+	        (parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
+	    (sign_extend:SI
+	      (vec_select:HI
+	        (match_operand:V2HI 2 "register_operand"         "   r,   r,   r,   r")
+	        (parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
+	  (match_operand:SI 5 "register_operand"                 "   0,   0,   0,   0")))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+  kmabb\t%0, %1, %2
+	kmabt\t%0, %1, %2
+	kmatt\t%0, %1, %2
+	kmabt\t%0, %2, %1"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "SI")])
+
+(define_expand "kmabb64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kma64_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), GEN_INT (2), GEN_INT (0),
+				 GEN_INT (2), operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmabt64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kma64_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), GEN_INT (2), GEN_INT (1),
+				 GEN_INT (3), operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmatt64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kma64_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (1), GEN_INT (3), GEN_INT (1),
+				 GEN_INT (3), operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kma64_internal"
+  [(set (match_operand:V2SI 0 "register_operand"                 "=   r,   r,   r,   r")
+	(ss_plus:V2SI
+	  (mult:V2SI
+	    (sign_extend:V2SI
+	      (vec_select:V2HI
+		(match_operand:V4HI 1 "register_operand"         "   r,   r,   r,   r")
+	        (parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")
+			   (match_operand:SI 4 "imm_2_3_operand" " C02, C02, C03, C03")])))
+	    (sign_extend:V2SI
+	      (vec_select:V2HI
+	        (match_operand:V4HI 2 "register_operand"         "   r,   r,   r,   r")
+	        (parallel [(match_operand:SI 5 "imm_0_1_operand" " C00, C01, C01, C00")
+			   (match_operand:SI 6 "imm_2_3_operand" " C02, C03, C03, C02")]))))
+	  (match_operand:V2SI 7 "register_operand"               "   0,   0,   0,   0")))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+  kmabb\t%0, %1, %2
+  kmabt\t%0, %1, %2
+  kmatt\t%0, %1, %2
+  kmabt\t%0, %2, %1"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V2SI")])
+
+;; KHM8, KHMX8, KHM16, KHMX16
+(define_insn "khm8<mode>"
+  [(set (match_operand:VQI 0 "register_operand"              "=r")
+	(unspec:VQI [(match_operand:VQI 1 "register_operand" " r")
+		     (match_operand:VQI 2 "register_operand" " r")]
+		     UNSPEC_KHM))]
+  "TARGET_ZPN"
+  "khm8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "khmx8<mode>"
+  [(set (match_operand:VQI 0 "register_operand"              "=r")
+	(unspec:VQI [(match_operand:VQI 1 "register_operand" " r")
+		     (match_operand:VQI 2 "register_operand" " r")]
+		     UNSPEC_KHMX))]
+  "TARGET_ZPN"
+  "khmx8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "khm16<mode>"
+  [(set (match_operand:VHI 0 "register_operand"              "=r")
+	(unspec:VHI [(match_operand:VHI 1 "register_operand" " r")
+		     (match_operand:VHI 2 "register_operand" " r")]
+		     UNSPEC_KHM))]
+  "TARGET_ZPN"
+  "khm16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "khmx16<mode>"
+  [(set (match_operand:VHI 0 "register_operand"              "=r")
+	(unspec:VHI [(match_operand:VHI 1 "register_operand" " r")
+		     (match_operand:VHI 2 "register_operand" " r")]
+		     UNSPEC_KHMX))]
+  "TARGET_ZPN"
+  "khmx16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; KMADA, KMAXDA
+(define_insn "kmada"
+  [(set (match_operand:SI 0 "register_operand"                           "=r")
+	(ss_plus:SI
+	  (match_operand:SI 1 "register_operand"                         " 0")
+	  (ss_plus:SI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 3 "register_operand" " r")
+				(parallel [(const_int 1)]))))
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 0)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmada\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmada64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_plus:V2SI
+	  (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (ss_plus:V2SI
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 3 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)]))))
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 3)
+				(parallel [(const_int 0) (const_int 2)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmada\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmaxda"
+  [(set (match_operand:SI 0 "register_operand"                           "=r")
+	(ss_plus:SI
+	  (match_operand:SI 1 "register_operand"                         " 0")
+	  (ss_plus:SI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmaxda\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmaxda64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_plus:V2SI
+	  (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (ss_plus:V2SI
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 3 "register_operand" " r")
+				(parallel [(const_int 0) (const_int 2)]))))
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 3)
+				(parallel [(const_int 1) (const_int 3)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmaxda\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+;; KMADS, KMADRS, KMAXDS
+(define_insn "kmads"
+  [(set (match_operand:SI 0 "register_operand"                           "=r")
+	(ss_plus:SI
+	  (match_operand:SI 1 "register_operand"                         " 0")
+	  (ss_minus:SI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 3 "register_operand" " r")
+				(parallel [(const_int 1)]))))
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 0)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmads\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmads64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_plus:V2SI
+	  (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (ss_minus:V2SI
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 3 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)]))))
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 3)
+				(parallel [(const_int 0) (const_int 2)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmads\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmadrs"
+  [(set (match_operand:SI 0 "register_operand"                           "=r")
+	(ss_plus:SI
+	  (match_operand:SI 1 "register_operand"                         " 0")
+	  (ss_minus:SI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 2 "register_operand" " r")
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 1)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmadrs\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmadrs64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_plus:V2SI
+	  (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (ss_minus:V2SI
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" " r")
+				(parallel [(const_int 0) (const_int 2)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 3 "register_operand" " r")
+				(parallel [(const_int 0) (const_int 2)]))))
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 1) (const_int 3)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 3)
+				(parallel [(const_int 1) (const_int 3)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmadrs\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmaxds"
+  [(set (match_operand:SI 0 "register_operand"                           "=r")
+	(ss_plus:SI
+	  (match_operand:SI 1 "register_operand"                         " 0")
+	  (ss_minus:SI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmaxds\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmaxds64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_plus:V2SI
+	  (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (ss_minus:V2SI
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 3 "register_operand" " r")
+				(parallel [(const_int 0) (const_int 2)]))))
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 3)
+				(parallel [(const_int 1) (const_int 3)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmaxds\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+;; RV64P KMAR64
+(define_insn "vkmar64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(ss_plus:DI (match_operand:DI 1 "register_operand"    " 0")
+	  (plus:DI
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 2 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (sign_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 3 "register_operand" " r")
+		  (parallel [(const_int 0)]))))
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 3) (parallel [(const_int 1)])))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "kmar64\t%0, %2, %3"
+  [(set_attr "type"   "dsp64")
+   (set_attr "mode" "DI")])
+
+;; KMDA, KMXDA
+(define_insn "kmda"
+  [(set (match_operand:SI 0 "register_operand"                         "=r")
+	(ss_plus:SI
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 1 "register_operand" "r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 2 "register_operand" "r")
+			      (parallel [(const_int 1)]))))
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 2)
+			      (parallel [(const_int 0)]))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmda\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmxda"
+  [(set (match_operand:SI 0 "register_operand"                        "=r")
+	(ss_plus:SI
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 1 "register_operand" "r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 2 "register_operand" "r")
+			      (parallel [(const_int 0)]))))
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 2)
+			      (parallel [(const_int 1)]))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmxda\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmxda64"
+  [(set (match_operand:V2SI 0 "register_operand"                      "=r")
+	(ss_plus:V2SI
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 1 "register_operand" "r")
+				(parallel [(const_int 1) (const_int 3)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" "r")
+				(parallel [(const_int 0) (const_int 2)]))))
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 1)
+				(parallel [(const_int 0) (const_int 2)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 1) (const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmxda\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmda64"
+  [(set (match_operand:V2SI 0 "register_operand"                      "=r")
+	(ss_plus:V2SI
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 1 "register_operand" "r")
+				(parallel [(const_int 1) (const_int 3)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" "r")
+				(parallel [(const_int 1) (const_int 3)]))))
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 1)
+				(parallel [(const_int 0) (const_int 2)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmda\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+;; KMMAC, KMMAC.u
+(define_insn "kmmac"
+  [(set (match_operand:SI 0 "register_operand"                         "=r")
+	(ss_plus:SI (match_operand:SI 1 "register_operand"             " 0")
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (mult:DI
+		(sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
+		(sign_extend:DI (match_operand:SI 3 "register_operand" " r")))
+	      (const_int 32)))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmmac\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmmac_64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_plus:V2SI (match_operand:V2SI 1 "register_operand"             " 0")
+	  (truncate:V2SI
+	    (lshiftrt:V2DI
+	      (mult:V2DI
+		(sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r"))
+		(sign_extend:V2DI (match_operand:V2SI 3 "register_operand" " r")))
+	      (const_int 32)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmmac\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmmac_round"
+  [(set (match_operand:SI 0 "register_operand"                                     "=r")
+	(ss_plus:SI (match_operand:SI 1 "register_operand"                         " 0")
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI [(mult:DI
+			    (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
+			    (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))]
+			 UNSPEC_ROUND)
+	      (const_int 32)))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmmac.u\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmmac64_round"
+  [(set (match_operand:V2SI 0 "register_operand"                                     "=r")
+	(ss_plus:V2SI (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (truncate:V2SI
+	    (lshiftrt:V2DI
+	      (unspec:V2DI [(mult:V2DI
+			    (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r"))
+			    (sign_extend:V2DI (match_operand:V2SI 3 "register_operand" " r")))]
+			 UNSPEC_ROUND)
+	      (const_int 32)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmmac.u\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+;; KMMAWB, KMMAWB.u, KMMAWB2, KMMAWB2.u, KMMAWT2, KMMAWT2.u
+(define_insn "kmmaw_internal"
+  [(set (match_operand:SI 0 "register_operand"                         "=  r,   r,   r,   r")
+	(ss_plus:SI
+	  (match_operand:SI 4 "register_operand"                       "   0,   0,   0,   0")
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (mult:DI
+		(sign_extend:DI (match_operand:SI 1 "register_operand" "   r,   r,   r,   r"))
+		  (sign_extend:DI
+		    (vec_select:HI
+		      (match_operand:V2HI 2 "register_operand"         "   r,   r,   r,   r")
+		      (parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C01, C00, C01")]))))
+	      (match_operand:SI 5 "imm_15_16_operand"                  " C16, C16, C15, C15" )))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+  kmmawb\t%0, %1, %2
+  kmmawt\t%0, %1, %2
+  kmmawb2\t%0, %1, %2
+  kmmawt2\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_expand "kmmawb"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), operands[1], GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (1), operands[1], GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawb2"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), operands[1], GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt2"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (1), operands[1], GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kmmaw_round_internal"
+  [(set (match_operand:SI 0 "register_operand"                            "=  r,   r,   r,   r")
+	(ss_plus:SI
+	  (match_operand:SI 4 "register_operand"                          "   0,   0,   0,   0")
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI
+		[(mult:DI
+		   (sign_extend:DI (match_operand:SI 1 "register_operand" "   r,   r,   r,   r"))
+		   (sign_extend:DI
+		     (vec_select:HI
+		       (match_operand:V2HI 2 "register_operand"           "   r,   r,   r,   r")
+		       (parallel [(match_operand:SI 3 "imm_0_1_operand"   " C00, C01, C00, C01")]))))]
+		UNSPEC_ROUND)
+	      (match_operand:SI 5 "imm_15_16_operand"                     " C16, C16, C15, C15")))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+  kmmawb.u\t%0, %1, %2
+  kmmawt.u\t%0, %1, %2
+  kmmawb2.u\t%0, %1, %2
+  kmmawt2.u\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_expand "kmmawb_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3],
+				       GEN_INT (0), operands[1], GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3],
+				       GEN_INT (1), operands[1], GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawb2_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3],
+				       GEN_INT (0), operands[1], GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt2_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3],
+				       GEN_INT (1), operands[1], GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kmmaw64_internal"
+[(set (match_operand:V2SI 0 "register_operand" "=r, r, r, r")
+      (ss_plus:V2SI
+	(match_operand:V2SI 5 "register_operand" "0, 0, 0, 0")
+	(vec_concat:V2SI
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (mult:DI
+		(sign_extend:DI
+		  (vec_select:SI
+		    (match_operand:V2SI 1 "register_operand" "r, r, r, r")
+		      (parallel [(const_int 0)])))
+		(sign_extend:DI
+		  (vec_select:HI
+		    (match_operand:V4HI 2 "register_operand"           "  r,   r,   r,   r")
+		      (parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01, C00, C01")]))))
+	      (match_operand:SI 6 "imm_15_16_operand"                  "C16, C16, C15, C15")))
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (mult:DI
+		(sign_extend:DI
+		  (vec_select:SI
+		    (match_dup 1)
+		      (parallel [(const_int 1)])))
+		(sign_extend:DI
+		  (vec_select:HI
+		    (match_dup 2)
+		      (parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03, C02, C03")]))))
+	      (match_dup 6))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+  kmmawb\t%0, %1, %2
+  kmmawt\t%0, %1, %2
+  kmmawb2\t%0, %1, %2
+  kmmawt2\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_expand "kmmawb64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_internal (operands[0], operands[2], operands[3],
+				   GEN_INT (0), GEN_INT (2), operands[1],
+				   GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_internal (operands[0], operands[2], operands[3],
+				   GEN_INT (1), GEN_INT (3), operands[1],
+				   GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawb2_64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_internal (operands[0], operands[2], operands[3],
+				   GEN_INT (0), GEN_INT (2), operands[1],
+				   GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt2_64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_internal (operands[0], operands[2], operands[3],
+				   GEN_INT (1), GEN_INT (3), operands[1],
+				   GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kmmaw64_round_internal"
+[(set (match_operand:V2SI 0 "register_operand"                           "=r,    r,   r,   r")
+      (ss_plus:V2SI
+	(match_operand:V2SI 5 "register_operand"                         "  0,   0,   0,   0")
+	(vec_concat:V2SI
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI
+		[(mult:DI
+		  (sign_extend:DI
+		    (vec_select:SI
+		      (match_operand:V2SI 1 "register_operand"           "  r,   r,   r,   r")
+			(parallel [(const_int 0)])))
+		  (sign_extend:DI
+		    (vec_select:HI
+		      (match_operand:V4HI 2 "register_operand"           "  r,   r,   r,   r")
+			(parallel [(match_operand:SI 3 "imm_0_1_operand" "C00, C01, C00, C01")]))))]
+		UNSPEC_ROUND)
+	      (const_int 16)))
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI
+		[(mult:DI
+		  (sign_extend:DI
+		    (vec_select:SI
+		      (match_dup 1)
+			(parallel [(const_int 1)])))
+		  (sign_extend:DI
+		    (vec_select:HI
+		      (match_dup 2)
+			(parallel [(match_operand:SI 4 "imm_2_3_operand" "C02, C03, C02, C03")]))))]
+		  UNSPEC_ROUND)
+	      (match_operand:SI 6 "imm_15_16_operand"                    "C16, C16, C15, C15"))))))]
+"TARGET_ZPN && TARGET_64BIT"
+  "@
+  kmmawb.u\t%0, %1, %2
+  kmmawt.u\t%0, %1, %2
+  kmmawb2.u\t%0, %1, %2
+  kmmawt2.u\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_expand "kmmawb64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_round_internal (operands[0], operands[2], operands[3],
+					 GEN_INT (0), GEN_INT (2), operands[1],
+					 GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_round_internal (operands[0], operands[2], operands[3],
+					 GEN_INT (1), GEN_INT (3), operands[1],
+					 GEN_INT (16)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawb2_64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_round_internal (operands[0], operands[2], operands[3],
+					 GEN_INT (0), GEN_INT (2), operands[1],
+					 GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmawt2_64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmaw64_round_internal (operands[0], operands[2], operands[3],
+					 GEN_INT (1), GEN_INT (3), operands[1],
+					 GEN_INT (15)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+;; KMMSB, KMMSB.u
+(define_insn "kmmsb"
+  [(set (match_operand:SI 0 "register_operand"                         "=r")
+	(ss_minus:SI (match_operand:SI 1 "register_operand"            " 0")
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (mult:DI
+		(sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
+		(sign_extend:DI (match_operand:SI 3 "register_operand" " r")))
+	      (const_int 32)))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmmsb\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmmsb_64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_minus:V2SI (match_operand:V2SI 1 "register_operand"             " 0")
+	  (truncate:V2SI
+	    (lshiftrt:V2DI
+	      (mult:V2DI
+		(sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r"))
+		(sign_extend:V2DI (match_operand:V2SI 3 "register_operand" " r")))
+	      (const_int 32)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmmsb\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmmsb_round"
+  [(set (match_operand:SI 0 "register_operand"                                     "=r")
+	(ss_minus:SI (match_operand:SI 1 "register_operand"                        " 0")
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI [(mult:DI
+			    (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))
+			    (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))]
+			 UNSPEC_ROUND)
+	      (const_int 32)))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmmsb.u\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmmsb64_round"
+  [(set (match_operand:V2SI 0 "register_operand"                                     "=r")
+	(ss_minus:V2SI (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (truncate:V2SI
+	    (lshiftrt:V2DI
+	      (unspec:V2DI [(mult:V2DI
+			    (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r"))
+			    (sign_extend:V2DI (match_operand:V2SI 3 "register_operand" " r")))]
+			 UNSPEC_ROUND)
+	      (const_int 32)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmmsb.u\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+;; KMMWB2, KMMWB2.u, KMMWT2, KMMWT2.u
+(define_insn "kmmw2_round_internal"
+  [(set (match_operand:SI 0 "register_operand"                          "=   r,    r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (unspec:DI
+	      [(ss_mult:DI
+		 (sign_extend:DI (match_operand:SI 1 "register_operand" "    r,    r"))
+		 (sign_extend:DI
+		   (vec_select:HI
+		     (match_operand:V2HI 2 "register_operand"           "    r,    r")
+		     (parallel [(match_operand:SI 3 "imm_0_1_operand"   "  C00,  C01")]))))]
+	      UNSPEC_KMMWU)
+	    (const_int 15))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+   kmmwb2.u\t%0, %1, %2
+   kmmwt2.u\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_expand "kmmwb2_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmw2_round_internal (operands[0], operands[1],
+				       operands[2], GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmwt2_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmw2_round_internal (operands[0], operands[1],
+				       operands[2], GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kmmw64_round"
+  [(set (match_operand:V2SI 0 "register_operand"                       "=r,    r")
+	(vec_concat:V2SI
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI
+		[(mult:DI
+		  (sign_extend:DI
+		    (vec_select:SI
+		      (match_operand:V2SI 1 "register_operand"           "  r,   r")
+		      (parallel [(const_int 0)])))
+		  (sign_extend:DI
+		    (vec_select:HI
+		      (match_operand:V4HI 2 "register_operand"           "  r,   r")
+		      (parallel [(match_operand:SI 3 "imm_0_1_operand"   "C00, C01")]))))]
+		UNSPEC_KMMWU)
+	      (const_int 15)))
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI
+		[(mult:DI
+		  (sign_extend:DI
+		    (vec_select:SI
+		      (match_dup 1)
+		      (parallel [(const_int 1)])))
+		  (sign_extend:DI
+		    (vec_select:HI
+		      (match_dup 2)
+		      (parallel [(match_operand:SI 4 "imm_2_3_operand"   "C02, C03")]))))]
+		UNSPEC_KMMWU)
+	      (const_int 15)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   kmmwb2.u\t%0, %1, %2
+   kmmwt2.u\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_expand "kmmwb64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmw64_round (operands[0], operands[1], operands[2],
+			       GEN_INT (0), GEN_INT (2)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmwt64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmw64_round (operands[0], operands[1], operands[2],
+			       GEN_INT (1), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+;; KMSDA, KMSXDA
+(define_insn "kmsda"
+  [(set (match_operand:SI 0 "register_operand"                           "=r")
+	(ss_minus:SI
+	  (match_operand:SI 1 "register_operand"                         " 0")
+	  (ss_minus:SI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 3 "register_operand" " r")
+				(parallel [(const_int 1)]))))
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 0)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmsda\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmsda64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_minus:V2SI
+	  (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (ss_minus:V2SI
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 3 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)]))))
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 3)
+				(parallel [(const_int 0) (const_int 2)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmsda\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmsxda"
+  [(set (match_operand:SI 0 "register_operand"                           "=r")
+	(ss_minus:SI
+	  (match_operand:SI 1 "register_operand"                         " 0")
+	  (ss_minus:SI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_operand:V2HI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kmsxda\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+(define_insn "kmsxda64"
+  [(set (match_operand:V2SI 0 "register_operand"                         "=r")
+	(ss_minus:V2SI
+	  (match_operand:V2SI 1 "register_operand"                       " 0")
+	  (ss_minus:V2SI
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" " r")
+				(parallel [(const_int 1) (const_int 3)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 3 "register_operand" " r")
+				(parallel [(const_int 0) (const_int 2)]))))
+	    (mult:V2SI
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)])))
+	      (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 3)
+				(parallel [(const_int 1) (const_int 3)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmsxda\t%0, %2, %3"
+  [(set_attr "type" "simd")])
+
+;; RV64P KMSR64
+(define_insn "vkmsr64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(ss_minus:DI
+	  (minus:DI
+	  (match_operand:DI 1 "register_operand"    " 0")
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 2 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (sign_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 3 "register_operand" " r")
+		  (parallel [(const_int 0)])))))
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 3) (parallel [(const_int 1)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmsr64\t%0, %2, %3"
+  [(set_attr "type"  "dsp64")
+   (set_attr "mode"  "DI")])
+
+(define_expand "kmmwb64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmw64 (operands[0], operands[1], operands[2],
+			  GEN_INT (0), GEN_INT (2)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmwt64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kmmw64 (operands[0], operands[1], operands[2],
+			 GEN_INT (1), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kmmw64"
+  [(set (match_operand:V2SI 0 "register_operand"                       "=r,    r")
+	(vec_concat:V2SI
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI [(mult:DI
+		(sign_extend:DI
+		  (vec_select:SI
+		    (match_operand:V2SI 1 "register_operand"           "  r,   r")
+		      (parallel [(const_int 0)])))
+		(sign_extend:DI
+		  (vec_select:HI
+		    (match_operand:V4HI 2 "register_operand"           "  r,   r")
+		      (parallel [(match_operand:SI 3 "imm_0_1_operand"   "C00, C01")]))))]
+	      UNSPEC_KMMW)
+	      (const_int 15)))
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI [(mult:DI
+		(sign_extend:DI
+		  (vec_select:SI
+		    (match_dup 1)
+		      (parallel [(const_int 1)])))
+		(sign_extend:DI
+		  (vec_select:HI
+		    (match_dup 2)
+		      (parallel [(match_operand:SI 4 "imm_2_3_operand"   "C02, C03")]))))]
+	      UNSPEC_KMMW)
+	      (const_int 15)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   kmmwb2\t%0, %1, %2
+   kmmwt2\t%0, %1, %2"
+[(set_attr "type" "simd")])
+
+(define_expand "kmmwb2"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmw2_internal (operands[0], operands[1], operands[2], GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmmwt2"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_kmmw2_internal (operands[0], operands[1], operands[2], GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kmmw2_internal"
+  [(set (match_operand:SI 0 "register_operand"                       "=   r,    r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (unspec:DI [(mult:DI
+	      (sign_extend:DI (match_operand:SI 1 "register_operand" "    r,    r"))
+	      (sign_extend:DI
+		(vec_select:HI
+		  (match_operand:V2HI 2 "register_operand"           "    r,    r")
+		  (parallel [(match_operand:SI 3 "imm_0_1_operand"   "  C00,  C01")]))))]
+	    UNSPEC_KMMW)
+	    (const_int 15))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+   kmmwb2\t%0, %1, %2
+   kmmwt2\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+;; KSLLW
+(define_insn "ksll"
+  [(set (match_operand:SI 0 "register_operand"               "=   r, r")
+	(ss_ashift:SI (match_operand:SI 1 "register_operand" "    r, r")
+		      (match_operand:SI 2 "rimm5u_operand"   " Iu05, r")))]
+  "TARGET_ZPN"
+  "@
+   kslliw\t%0, %1, %2
+   ksllw\t%0, %1, %2"
+  [(set_attr "type"  "dsp")
+   (set_attr "mode"  "SI")])
+
+;; KSLL8
+(define_insn "kslli8<VQI:mode><X:mode>"
+  [(set (match_operand:VQI 0 "register_operand"                "=  r, r")
+	(ss_ashift:VQI (match_operand:VQI 1 "register_operand" "   r, r")
+		       (match_operand:X 2   "rimm3u_operand"   " u03, r")))]
+  "TARGET_ZPN"
+  "@
+   kslli8\t%0, %1, %2
+   ksll8\t%0, %1, %2"
+  [(set_attr "type"  "simd, simd")
+   (set_attr "mode"  "<VQI:MODE>, <VQI:MODE>")])
+
+;; KSLL16
+(define_insn "kslli16<mode>"
+  [(set (match_operand:VHI 0 "register_operand"                "=  r, r")
+	(ss_ashift:VHI (match_operand:VHI 1 "register_operand" "   r, r")
+		       (match_operand:SI 2  "rimm4u_operand"   " u04, r")))]
+  "TARGET_ZPN"
+  "@
+   kslli16\t%0, %1, %2
+   ksll16\t%0, %1, %2"
+  [(set_attr "type"  "simd, simd")
+   (set_attr "mode"  "<MODE>, <MODE>")])
+
+;; KSLL32, KSLLI32
+(define_insn "ksll32"
+  [(set (match_operand:V2SI 0 "register_operand"                 "=  r, r")
+	(ss_ashift:V2SI (match_operand:V2SI 1 "register_operand" "   r, r")
+			(match_operand:SI 2   "rimm5u_operand"   " u05, r")))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   kslli32\t%0, %1, %2
+   ksll32\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V2SI")])
+
+;; KSLRA 8|16|32
+(define_expand "kslra<VECI:mode>"
+  [(match_operand:VECI 0 "register_operand" "")
+   (match_operand:VECI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
+   "TARGET_ZPN"
+{
+  unsigned int extract_bits;
+  switch (<VECI:bits>)
+  {
+    case 8: extract_bits = 4; break;
+    case 16: extract_bits = 5; break;
+    case 32: extract_bits = 6; break;
+    default: gcc_unreachable();
+  }
+  emit_insn (gen_kslra<VECI:mode>_internal (operands[0],
+    operands[1], operands[2], GEN_INT (extract_bits)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kslra<VECI:mode>_internal"
+  [(set (match_operand:VECI 0 "register_operand"                  "=r")
+	(if_then_else:VECI
+	  (lt:SI
+		(sign_extract:SI
+			(match_operand:SI 2 "register_operand" " r")
+			(match_operand:SI 3 "imm3u_operand"  " I")
+			(const_int 0))
+		(const_int 0))
+	  (ashiftrt:VECI (match_operand:VECI 1 "register_operand" " r")
+			 (neg:SI (sign_extract:SI (match_dup 2) (match_dup 3) (const_int 0))))
+	  (ss_ashift:VECI (match_dup 1)
+			  (sign_extract:SI (match_dup 2) (match_dup 3) (const_int 0)))))]
+  "TARGET_ZPN"
+  "kslra<VECI:bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<VECI:MODE>")])
+
+;; kslra32.u kslrav2sidi_round
+(define_expand "kslra<VECI:mode>_round"
+  [(match_operand:VECI 0 "register_operand" "")
+   (match_operand:VECI 1 "register_operand" "")
+   (match_operand:SI 2 "register_operand" "")]
+   "TARGET_ZPN"
+{
+  unsigned int extract_bits;
+  switch (<VECI:bits>)
+  {
+    case 8: extract_bits = 4; break;
+    case 16: extract_bits = 5; break;
+    case 32: extract_bits = 6; break;
+    default: gcc_unreachable();
+  }
+  emit_insn (gen_kslra<VECI:mode>_round_internal (operands[0],
+    operands[1], operands[2], GEN_INT (extract_bits)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kslra<VECI:mode>_round_internal"
+  [(set (match_operand:VECI 0 "register_operand"                  "=r")
+	(if_then_else:VECI
+	  (lt:SI
+		(sign_extract:SI
+			(match_operand:SI 2 "register_operand" " r")
+			(match_operand:SI 3 "imm3u_operand"  " I")
+			(const_int 0))
+		(const_int 0))
+	  (unspec:VECI [(ashiftrt:VECI (match_operand:VECI 1 "register_operand" " r")
+				       (neg:SI (sign_extract:SI (match_dup 2) (match_dup 3) (const_int 0))))]
+		        UNSPEC_ROUND)
+	  (ss_ashift:VECI (match_dup 1)
+			  (sign_extract:SI (match_dup 2) (match_dup 3) (const_int 0)))))]
+  "TARGET_ZPN"
+  "kslra<VECI:bits>.u\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<VECI:MODE>")])
+
+;; kslraw
+(define_insn "kslraw"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+		    (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAW))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kslraw\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_insn "kslraw64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI
+	  (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+		      (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAW)))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kslraw\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "DI")])
+
+(define_insn "kslrawu"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+		    (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAWU))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kslraw.u\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_insn "kslrawu64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI
+	  (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+		      (match_operand:SI 2 "register_operand" "r")] UNSPEC_KSLRAWU)))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kslraw.u\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "DI")])
+
+;; KSTAS16|32, KSTSA16|32
+(define_expand "kstas<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kstas<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kstas<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (ss_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (ss_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "kstas<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+;; rv64 kstas16
+(define_expand "kstas16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kstas16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kstas16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (ss_minus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+					(parallel [(const_int 0)]))
+			 (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+					(parallel [(const_int 0)])))
+	    (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+	  (vec_concat:V2HI
+	    (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+	    (ss_plus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kstas16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "kstsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_kstsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kstsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (ss_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (ss_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "kstsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "kstsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kstsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kstsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (ss_plus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				       (parallel [(const_int 0)]))
+			(vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				       (parallel [(const_int 0)])))
+	    (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+	  (vec_concat:V2HI
+	    (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+	    (ss_minus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			  (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kstsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; KWMMUL[.u]
+(define_insn "kwmmul"
+  [(set (match_operand:SI 0 "register_operand"                       "=r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (ss_mult:DI
+	      (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2))
+	      (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))
+	    (const_int 32))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kwmmul\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "kwmmul_64"
+  [(set (match_operand:V2SI 0 "register_operand"                       "=r")
+	(truncate:V2SI
+	  (lshiftrt:V2DI
+	    (ss_mult:V2DI
+	      (mult:V2DI (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" " r")) (const_int 2))
+	      (mult:V2DI (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r")) (const_int 2)))
+	    (const_int 32))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kwmmul\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "kwmmul_round"
+  [(set (match_operand:SI 0 "register_operand"                       "=r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (unspec:DI [
+	      (ss_mult:DI
+		(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2))
+		(mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))]
+	      UNSPEC_ROUND)
+	    (const_int 32))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "kwmmul.u\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "kwmmul64_round"
+  [(set (match_operand:V2SI 0 "register_operand"                       "=r")
+	(truncate:V2SI
+	  (lshiftrt:V2DI
+	    (unspec:V2DI [
+	      (ss_mult:V2DI
+		(mult:V2DI (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" " r")) (const_int 2))
+		(mult:V2DI (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r")) (const_int 2)))]
+	      UNSPEC_ROUND)
+	    (const_int 32))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kwmmul.u\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+;; MADDR32, MSUBR32
+(define_insn "maddr32"
+  [(set (match_operand:SI 0 "register_operand"                   "=r")
+	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" " r")
+			  (match_operand:SI 2 "register_operand" " r"))
+		 (match_operand:SI 3 "register_operand"          " 0")))]
+  "TARGET_ZPN"
+  "maddr32\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "SI")])
+
+(define_insn "msubr32"
+  [(set (match_operand:SI 0 "register_operand"                    "=r")
+	(minus:SI (match_operand:SI 3 "register_operand"          " 0")
+		  (mult:SI (match_operand:SI 1 "register_operand" " r")
+			   (match_operand:SI 2 "register_operand" " r"))))]
+  "TARGET_ZPN"
+  "msubr32\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "SI")])
+
+;; MULR64, MULSR64
+(define_insn "rvp_umulsidi3"
+  [(set (match_operand:DI 0 "register_operand"                          "=r")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
+		 (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
+  "TARGET_ZPSF"
+  "mulr64\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "DI")])
+
+(define_insn "rvp_mulsidi3"
+  [(set (match_operand:DI 0 "register_operand"                          "=r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
+		 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))]
+  "TARGET_ZPSF"
+  "mulsr64\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "DI")])
+
+;; MAX, MIN
+(define_insn "smax<mode>3"
+  [(set (match_operand:X 0 "register_operand"          "=r")
+	(smax:X (match_operand:X 1 "register_operand"  " r")
+		 (match_operand:X 2 "register_operand" " r")))]
+  "TARGET_ZBPBO"
+  "max\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "smin<mode>3"
+  [(set (match_operand:X 0 "register_operand"          "=r")
+	(smin:X (match_operand:X 1 "register_operand"  " r")
+		 (match_operand:X 2 "register_operand" " r")))]
+  "TARGET_ZBPBO"
+  "min\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "<MODE>")])
+
+;; PBSAD, PBSADA
+(define_insn "pbsad<mode>"
+  [(set (match_operand:X 0 "register_operand"              "=r")
+	(unspec:X [(match_operand:X 1 "register_operand"   " r")
+		     (match_operand:X 2 "register_operand" " r")] UNSPEC_PBSAD))]
+  "TARGET_ZPN"
+  "pbsad\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "pbsada<mode>"
+  [(set (match_operand:X 0 "register_operand"              "=r")
+	(unspec:X [(match_operand:X 1 "register_operand"   " 0")
+		     (match_operand:X 2 "register_operand" " r")
+		     (match_operand:X 3 "register_operand" " r")] UNSPEC_PBSADA))]
+  "TARGET_ZPN"
+  "pbsada\t%0, %2, %3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "<MODE>")])
+
+;; PKBB[16|32], PKBT[16|32], PKTT[16|32], PKTB[16|32]
+(define_insn "vec_merge<mode>"
+  [(set (match_operand:VSHI 0 "register_operand"               "= r,   r,   r,   r,   r,   r,   r,   r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (vec_select:<VNHALF>
+	      (match_operand:VSHI 1 "register_operand"         "  r,   r,   r,   r,   r,   r,   r,   r")
+	      (parallel [(match_operand:SI 4 "imm_0_1_operand" "C00, C00, C01, C01, C00, C00, C01, C01")])))
+	  (vec_duplicate:VSHI
+	    (vec_select:<VNHALF>
+	      (match_operand:VSHI 2 "register_operand"         "  r,   r,   r,   r,   r,   r,   r,   r")
+	      (parallel [(match_operand:SI 5 "imm_0_1_operand" "C00, C01, C01, C00, C00, C01, C01, C00")])))
+	  (match_operand:SI 3 "imm_1_2_operand"                "C01, C01, C01, C01, C02, C02, C02, C02")))]
+  "TARGET_ZPN"
+  {
+    const char *pats[] = {
+		TARGET_ZBPBO ? "pack\t%0, %2, %1" : "pkbb<bits>\t%0, %2, %1",
+        "pktb<bits>\t%0, %2, %1",
+        TARGET_ZBPBO ? "packu\t%0, %2, %1" : "pktt<bits>\t%0, %2, %1",
+        "pkbt<bits>\t%0, %2, %1",
+        TARGET_ZBPBO ? "pack\t%0, %1, %2" : "pkbb<bits>\t%0, %1, %2",
+        "pkbt<bits>\t%0, %1, %2",
+        TARGET_ZBPBO ? "packu\t%0, %1, %2" : "pktt<bits>\t%0, %1, %2",
+        "pktb<bits>\t%0, %1, %2" };
+    return pats[which_alternative];
+  }
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "<MODE>")])
+
+(define_expand "pkbb<mode>"
+  [(match_operand:VSHI 0 "register_operand")
+   (match_operand:VSHI 1 "register_operand")
+   (match_operand:VSHI 2 "register_operand")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_vec_merge<mode> (operands[0], operands[1], operands[2],
+				  GEN_INT (2), GEN_INT (0), GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "pkbt<mode>"
+  [(match_operand:VSHI 0 "register_operand")
+   (match_operand:VSHI 1 "register_operand")
+   (match_operand:VSHI 2 "register_operand")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_vec_merge<mode> (operands[0], operands[1], operands[2],
+				  GEN_INT (2), GEN_INT (0), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "pktt<mode>"
+  [(match_operand:VSHI 0 "register_operand")
+   (match_operand:VSHI 1 "register_operand")
+   (match_operand:VSHI 2 "register_operand")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_vec_merge<mode> (operands[0], operands[1], operands[2],
+				  GEN_INT (2), GEN_INT (1), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "pktb<mode>"
+  [(match_operand:VSHI 0 "register_operand")
+   (match_operand:VSHI 1 "register_operand")
+   (match_operand:VSHI 2 "register_operand")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_vec_merge<mode> (operands[0], operands[1], operands[2],
+				  GEN_INT (2), GEN_INT (1), GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+;; pkbb16 rv64p
+(define_expand "pkbb64"
+  [(match_operand:V4HI 0 "register_operand")
+   (match_operand:V4HI 1 "register_operand")
+   (match_operand:V4HI 2 "register_operand")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_vec_pkbb64 (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "vec_pkbb64"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(vec_select:V4HI
+	 (vec_concat:V8HI (match_operand:V4HI 1 "register_operand" "r")
+			  (match_operand:V4HI 2 "register_operand" "r"))
+	 (parallel [(const_int 0) (const_int 4)
+		    (const_int 2) (const_int 6)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "pkbb16\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "pkbt64"
+  [(match_operand:V4HI 0 "register_operand")
+   (match_operand:V4HI 1 "register_operand")
+   (match_operand:V4HI 2 "register_operand")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_vec_pkbt64 (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "vec_pkbt64"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(vec_select:V4HI
+	 (vec_concat:V8HI (match_operand:V4HI 1 "register_operand" "r")
+			  (match_operand:V4HI 2 "register_operand" "r"))
+	 (parallel [(const_int 0) (const_int 5)
+		    (const_int 2) (const_int 7)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "pkbt16\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "pktt64"
+  [(match_operand:V4HI 0 "register_operand")
+   (match_operand:V4HI 1 "register_operand")
+   (match_operand:V4HI 2 "register_operand")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_vec_pktt64 (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "vec_pktt64"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(vec_select:V4HI
+	 (vec_concat:V8HI (match_operand:V4HI 1 "register_operand" "r")
+			  (match_operand:V4HI 2 "register_operand" "r"))
+	 (parallel [(const_int 1) (const_int 5)
+		    (const_int 3) (const_int 7)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "pktt16\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "pktb64"
+  [(match_operand:V4HI 0 "register_operand")
+   (match_operand:V4HI 1 "register_operand")
+   (match_operand:V4HI 2 "register_operand")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_vec_pktb64 (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "vec_pktb64"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(vec_select:V4HI
+	 (vec_concat:V8HI (match_operand:V4HI 1 "register_operand" "r")
+			  (match_operand:V4HI 2 "register_operand" "r"))
+	 (parallel [(const_int 1) (const_int 4)
+		    (const_int 3) (const_int 6)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "pktb16\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V4HI")])
+
+;; [U]RADD[8|16|32|64|W], [U]RSUB[8|16|32|64|W]
+(define_insn "radd<mode>3"
+  [(set (match_operand:VECI 0 "register_operand" "=r")
+	(truncate:VECI
+	  (ashiftrt:<VEXT>
+	    (plus:<VEXT> (sign_extend:<VEXT> (match_operand:VECI 1 "register_operand" " r"))
+			 (sign_extend:<VEXT> (match_operand:VECI 2 "register_operand" " r")))
+	    (const_int 1))))]
+  "TARGET_ZPN"
+  "radd<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; radd64
+(define_insn "radddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(truncate:DI
+	  (ashiftrt:TI
+	    (plus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r"))
+		     (sign_extend:TI (match_operand:DI 2 "register_operand" " r")))
+	  (const_int 1))))]
+  "TARGET_ZPSF"
+  "radd64\t%0, %1, %2"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+(define_insn "uradd<mode>3"
+  [(set (match_operand:VECI 0 "register_operand" "=r")
+	(truncate:VECI
+	  (lshiftrt:<VEXT>
+	    (plus:<VEXT> (zero_extend:<VEXT> (match_operand:VECI 1 "register_operand" " r"))
+			 (zero_extend:<VEXT> (match_operand:VECI 2 "register_operand" " r")))
+	    (const_int 1))))]
+  "TARGET_ZPN"
+  "uradd<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; uradd64
+(define_insn "uradddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(truncate:DI
+	  (lshiftrt:TI
+	    (plus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r"))
+		     (zero_extend:TI (match_operand:DI 2 "register_operand" " r")))
+	  (const_int 1))))]
+  "TARGET_ZPSF"
+  "uradd64\t%0, %1, %2"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+(define_insn "rsub<mode>3"
+  [(set (match_operand:VECI 0 "register_operand"                                   "=r")
+	(truncate:VECI
+	  (ashiftrt:<VEXT>
+	    (minus:<VEXT> (sign_extend:<VEXT> (match_operand:VECI 1 "register_operand" " r"))
+			  (sign_extend:<VEXT> (match_operand:VECI 2 "register_operand" " r")))
+	    (const_int 1))))]
+  "TARGET_ZPN"
+  "rsub<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "ursub<mode>3"
+  [(set (match_operand:VECI 0 "register_operand"                                   "=r")
+	(truncate:VECI
+	  (ashiftrt:<VEXT>
+	    (minus:<VEXT> (zero_extend:<VEXT> (match_operand:VECI 1 "register_operand" " r"))
+			  (zero_extend:<VEXT> (match_operand:VECI 2 "register_operand" " r")))
+	    (const_int 1))))]
+  "TARGET_ZPN"
+  "ursub<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; rsub64
+(define_insn "rsubdi3"
+  [(set (match_operand:DI 0 "register_operand"                   "=r")
+	(truncate:DI
+	  (ashiftrt:TI
+	    (minus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r"))
+		      (sign_extend:TI (match_operand:DI 2 "register_operand" " r")))
+	  (const_int 1))))]
+  "TARGET_ZPSF"
+  "rsub64\t%0, %1, %2"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; ursub64
+(define_insn "ursubdi3"
+  [(set (match_operand:DI 0 "register_operand"                   "=r")
+	(truncate:DI
+	  (lshiftrt:TI
+	    (minus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r"))
+		      (zero_extend:TI (match_operand:DI 2 "register_operand" " r")))
+	  (const_int 1))))]
+  "TARGET_ZPSF"
+  "ursub64\t%0, %1, %2"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; raddw and rsubw.
+(define_insn "r<opcode>si3"
+  [(set (match_operand:SI 0 "register_operand"                       "=r")
+	(truncate:SI
+	  (ashiftrt:DI
+	    (plus_minus:DI
+	      (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
+	      (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))
+	    (const_int 1))))]
+  "TARGET_ZPN"
+  "r<opcode>w\t%0, %1, %2"
+  [(set_attr "type" "dsp")])
+
+;; uraddw and ursubw.
+(define_insn "ur<opcode>si3"
+  [(set (match_operand:SI 0 "register_operand"                       "=r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (plus_minus:DI
+	      (zero_extend:DI (match_operand:SI 1 "register_operand" " r"))
+	      (zero_extend:DI (match_operand:SI 2 "register_operand" " r")))
+	    (const_int 1))))]
+  "TARGET_ZPN"
+  "ur<opcode>w\t%0, %1, %2"
+  [(set_attr "type" "dsp")])
+
+;; RDOV
+(define_insn "rdov<X:mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+	(unspec_volatile:X [(const_int 0)] UNSPEC_RDOV))]
+  "TARGET_ZPN"
+  "csrr \t%0, vxsat, zero"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "<MODE>")])
+
+;; RSTAS[16|32], RSTSA[16|32]
+(define_expand "rstas<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_rstas<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rstas<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+		(minus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 0)])))
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 1)])))
+		  (sign_extend:SI
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "rstas<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "rstas16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_rstas16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rstas16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 0)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "rstas16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_expand "rstsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_rstsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rstsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+	        (minus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 0)])))
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (ashiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 1)])))
+		  (sign_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "rstsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "rstsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_rstsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "rstsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 0)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (ashiftrt:SI
+		(plus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (ashiftrt:SI
+		(minus:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "rstsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; SCLIP8, SCLIP16
+(define_insn "sclip8<mode>"
+  [(set (match_operand:VQI 0 "register_operand"              "=  r")
+	(unspec:VQI [(match_operand:VQI 1 "register_operand" "   r")
+		      (match_operand:SI 2 "imm3u_operand"    " u03")]
+		     UNSPEC_CLIPS))]
+  "TARGET_ZPN"
+  "sclip8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "sclip16<mode>"
+  [(set (match_operand:VHI 0 "register_operand"              "=   r")
+	(unspec:VHI [(match_operand:VHI 1 "register_operand" "    r")
+		     (match_operand:SI 2 "imm4u_operand"     " u04")]
+		     UNSPEC_CLIPS))]
+  "TARGET_ZPN"
+  "sclip16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "sclip32<VD_SI:mode><X:mode>"
+  [(set (match_operand:VD_SI 0 "register_operand" "=r")
+	(unspec:VD_SI [(match_operand:VD_SI 1 "register_operand" "r")
+		       (match_operand:X 2 "immediate_operand" "i")] UNSPEC_CLIPS_OV))]
+  "TARGET_ZPN"
+  "sclip32\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode" "<VD_SI:MODE>")])
+
+;; SCMPLE8, SCMPLE16
+(define_insn "scmple<mode>"
+  [(set (match_operand:VQIHI 0 "register_operand"                          "=r")
+	(unspec:VQIHI [(le:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
+				 (match_operand:VQIHI 2 "register_operand" " r"))]
+		       UNSPEC_VEC_COMPARE))]
+  "TARGET_ZPN"
+  "scmple<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; SCMPLT8, SCMPLT16
+(define_insn "scmplt<mode>"
+  [(set (match_operand:VQIHI 0 "register_operand"                          "=r")
+	(unspec:VQIHI [(lt:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
+				 (match_operand:VQIHI 2 "register_operand" " r"))]
+		       UNSPEC_VEC_COMPARE))]
+  "TARGET_ZPN"
+  "scmplt<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; SMAL
+(define_insn "smal"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(plus:DI (match_operand:DI 1 "register_operand"    " r")
+	  (sign_extend:DI
+	    (mult:SI
+	      (sign_extend:SI
+		(vec_select:HI
+		  (match_operand:V2HI 2 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (sign_extend:SI
+		(vec_select:HI
+		  (match_dup 2)
+		  (parallel [(const_int 1)])))))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "smal\t%0, %1, %2"
+  [(set_attr "type" "psimd")
+   (set_attr "mode" "DI")])
+
+(define_insn "smal_64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(plus:DI (match_operand:DI 1 "register_operand"    " r")
+	  (plus:DI
+	    (sign_extend:DI
+	      (mult:SI
+		(sign_extend:SI
+		  (vec_select:HI
+		    (match_operand:V4HI 2 "register_operand" " r")
+		    (parallel [(const_int 0)])))
+		(sign_extend:SI
+		  (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))
+	    (sign_extend:DI
+	      (mult:SI
+		(sign_extend:SI
+		  (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+		(sign_extend:SI
+		  (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "smal\t%0, %1, %2"
+  [(set_attr "type" "psimd")
+   (set_attr "mode" "DI")])
+
+;; SMALBB, SMALBT, SMALTT
+(define_expand "smalbb"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smaddhidi (operands[0], operands[2],
+			    operands[3], operands[1],
+			    GEN_INT (0), GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_expand "smalbt"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smaddhidi (operands[0], operands[2],
+			    operands[3], operands[1],
+			    GEN_INT (0), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_expand "smaltt"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")
+   (match_operand:V2HI 3 "register_operand" "")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smaddhidi (operands[0], operands[2],
+			    operands[3], operands[1],
+			    GEN_INT (1), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_insn "smaddhidi"
+  [(set (match_operand:DI 0 "register_operand"                   "=  r,   r,   r,   r")
+	(plus:DI
+	  (match_operand:DI 3 "register_operand"                 "   0,   0,   0,   0")
+	  (mult:DI
+	    (sign_extend:DI
+	      (vec_select:HI
+		(match_operand:V2HI 1 "register_operand"         "   r,   r,   r,   r")
+		(parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C00, C01, C01")])))
+	    (sign_extend:DI
+	      (vec_select:HI
+		(match_operand:V2HI 2 "register_operand"         "   r,   r,   r,   r")
+		(parallel [(match_operand:SI 5 "imm_0_1_operand" " C00, C01, C01, C00")]))))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "@
+   smalbb\t%0, %1, %2
+   smalbt\t%0, %1, %2
+   smaltt\t%0, %1, %2
+   smalbt\t%0, %2, %1"
+[(set_attr "type" "dsp64")])
+
+;; 64 Bit
+(define_expand "smalbb64"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPSF && TARGET_64BIT"
+{
+  emit_insn (gen_smaddhidi64 (operands[0], operands[2],
+			      operands[3], operands[1],
+			      GEN_INT (0), GEN_INT (0),
+			      GEN_INT (2), GEN_INT (2)));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_expand "smalbt64"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPSF && TARGET_64BIT"
+{
+  emit_insn (gen_smaddhidi64 (operands[0], operands[2],
+			      operands[3], operands[1],
+			      GEN_INT (0), GEN_INT (1),
+			      GEN_INT (2), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_expand "smaltt64"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPSF && TARGET_64BIT"
+{
+  emit_insn (gen_smaddhidi64 (operands[0], operands[2],
+			      operands[3], operands[1],
+			      GEN_INT (1), GEN_INT (1),
+			      GEN_INT (3), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_insn "smaddhidi64"
+  [(set (match_operand:DI 0 "register_operand"                   "=  r,   r,   r,   r")
+	(plus:DI
+	  (match_operand:DI 3 "register_operand"                 "   0,   0,   0,   0")
+	  (plus:DI
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:HI
+		  (match_operand:V4HI 1 "register_operand"         "   r,   r,   r,   r")
+		  (parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C00, C01, C01")])))
+	      (sign_extend:DI
+		(vec_select:HI
+		  (match_operand:V4HI 2 "register_operand"         "   r,   r,   r,   r")
+		  (parallel [(match_operand:SI 5 "imm_0_1_operand" " C00, C01, C01, C00")]))))
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:HI
+		  (match_dup 1)
+		  (parallel [(match_operand:SI 6 "imm_2_3_operand" " C02, C02, C03, C03")])))
+	      (sign_extend:DI
+		(vec_select:HI
+		  (match_dup 2)
+		  (parallel [(match_operand:SI 7 "imm_2_3_operand" " C02, C03, C03, C02")])))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "@
+   smalbb\t%0, %1, %2
+   smalbt\t%0, %1, %2
+   smaltt\t%0, %1, %2
+   smalbt\t%0, %2, %1"
+  [(set_attr "type" "dsp64")])
+
+;; SMALDA
+(define_expand "smalda1"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" " r")
+   (match_operand:V2HI 3 "register_operand" " r")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smalda1_le (operands[0], operands[1], operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_insn "smalda1_le"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (sign_extend:DI
+	    (plus:SI
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 2 "register_operand" " r")
+				  (parallel [(const_int 1)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 3 "register_operand" " r")
+				  (parallel [(const_int 1)]))))
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 2)
+				  (parallel [(const_int 0)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 3)
+				  (parallel [(const_int 0)]))))))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "smalda\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; 64 Bit v_smalda
+(define_insn "smalda64"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (plus:DI
+	    (sign_extend:DI
+	      (plus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 3 "register_operand" " r")
+				    (parallel [(const_int 0)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 1)]))))))
+	    (sign_extend:DI
+	      (plus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 2)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 3)])))))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "smalda\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; SMALXDA, SMALXDS
+(define_expand "smalxda1"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" " r")
+   (match_operand:V2HI 3 "register_operand" " r")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smalxda1_le (operands[0], operands[1], operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_expand "smalxds1"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" " r")
+   (match_operand:V2HI 3 "register_operand" " r")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smalxds1_le (operands[0], operands[1], operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_insn "smalxd<add_sub>1_le"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (sign_extend:DI
+	    (plus_minus:SI
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 2 "register_operand" " r")
+				  (parallel [(const_int 1)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 3 "register_operand" " r")
+				  (parallel [(const_int 0)]))))
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 2)
+				  (parallel [(const_int 0)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 3)
+				  (parallel [(const_int 1)]))))))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "smalxd<add_sub>\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+(define_insn "smalxd<add_sub>64"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (plus:DI
+	    (sign_extend:DI
+	      (plus_minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 3 "register_operand" " r")
+				    (parallel [(const_int 0)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 1)]))))))
+	    (sign_extend:DI
+	      (plus_minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 2)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 3)])))))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "smalxd<add_sub>\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; SMALDS
+(define_expand "smalds1"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" " r")
+   (match_operand:V2HI 3 "register_operand" " r")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smalds1_le (operands[0], operands[1], operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_insn "smalds1_le"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (sign_extend:DI
+	    (minus:SI
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 2 "register_operand" " r")
+				  (parallel [(const_int 1)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 3 "register_operand" " r")
+				  (parallel [(const_int 1)]))))
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 2)
+				  (parallel [(const_int 0)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 3)
+				  (parallel [(const_int 0)]))))))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "smalds\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+(define_insn "smalds64"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (plus:DI
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 3 "register_operand" " r")
+				    (parallel [(const_int 1)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 0)]))))))
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 3)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 2)])))))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "smalds\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; SMALDRS
+(define_expand "smaldrs3"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" " r")
+   (match_operand:V2HI 3 "register_operand" " r")]
+  "TARGET_ZPSF && !TARGET_64BIT"
+{
+  emit_insn (gen_smaldrs3_le (operands[0], operands[1], operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp64")])
+
+(define_insn "smaldrs3_le"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (sign_extend:DI
+	    (minus:SI
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 2 "register_operand" " r")
+				  (parallel [(const_int 0)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 3 "register_operand" " r")
+				  (parallel [(const_int 0)]))))
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 2)
+				  (parallel [(const_int 1)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_dup 3)
+				  (parallel [(const_int 1)]))))))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "smaldrs\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+(define_insn "smaldrs64"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(plus:DI
+	  (match_operand:DI 1 "register_operand"                           " 0")
+	  (plus:DI
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 3 "register_operand" " r")
+				    (parallel [(const_int 0)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 1)]))))))
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 2)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 3)])))))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "smaldrs\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; RV32P KMAR64, KMSR64
+(define_insn "ssm<opcode>sidi4"
+  [(set (match_operand:DI 0 "register_operand"       "=r")
+	(ssat_op:DI
+	  (mult:DI
+	    (sign_extend:DI
+	      (match_operand:SI 1 "register_operand" " r"))
+	    (sign_extend:DI
+	      (match_operand:SI 2 "register_operand"  " r")))
+	  (match_operand:DI 3 "register_operand"      " 0")))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "km<add_sub>r64\t%0, %1, %2"
+  [(set_attr "type"   "dsp64")
+   (set_attr "mode"   "DI")])
+
+;; RV32P UKMSR64, UKMAR64
+(define_insn "usm<opcode>sidi4"
+  [(set (match_operand:DI 0 "register_operand"       "=r")
+	(usat_op:DI
+	  (mult:DI
+	    (zero_extend:DI
+	      (match_operand:SI 1 "register_operand" " r"))
+	    (zero_extend:DI
+	      (match_operand:SI 2 "register_operand"  " r")))
+	  (match_operand:DI 3 "register_operand"      " 0")))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "ukm<add_sub>r64\t%0, %1, %2"
+  [(set_attr "type"   "dsp64")
+   (set_attr "mode"   "DI")])
+
+;; RV32P KMSR64, KMAR64
+(define_insn "<u>m<opcode>sidi4"
+  [(set (match_operand:DI 0 "register_operand"       "=r")
+	(plus_minus:DI
+	  (mult:DI
+	    (any_extend:DI
+	      (match_operand:SI 1 "register_operand" " r"))
+	    (any_extend:DI
+	      (match_operand:SI 2 "register_operand"  " r")))
+	  (match_operand:DI 3 "register_operand"      " 0")))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "<su>m<add_sub>r64\t%0, %1, %2"
+  [(set_attr "type"   "dsp64")
+   (set_attr "mode"   "DI")])
+
+;; SMAR64, UMAR64
+(define_insn "v<su>mar64_1"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(plus:DI (match_operand:DI 1 "register_operand"    " 0")
+	  (plus:DI
+	    (mult:DI
+	      (any_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 2 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (any_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 3 "register_operand" " r")
+		  (parallel [(const_int 0)]))))
+	    (mult:DI
+	      (any_extend:DI
+		(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	      (any_extend:DI
+		(vec_select:SI (match_dup 3) (parallel [(const_int 1)])))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "<su>mar64\t%0, %2, %3"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; smax[8|16] and umax[8|16]
+(define_insn "<opcode><mode>3"
+  [(set (match_operand:VECI 0 "register_operand"             "=r")
+	(sumax:VECI (match_operand:VECI 1 "register_operand" " r")
+		    (match_operand:VECI 2 "register_operand" " r")))]
+  "TARGET_ZPN"
+  "<opcode><bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+;; smin[8|16] and umin[8|16]
+(define_insn "<opcode><mode>3"
+  [(set (match_operand:VECI 0 "register_operand"             "=r")
+	(sumin:VECI (match_operand:VECI 1 "register_operand" " r")
+		    (match_operand:VECI 2 "register_operand" " r")))]
+  "TARGET_ZPN"
+  "<opcode><bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+;; SMAQA, SMAQA.SU, UMAQA, UMAQA.SU
+(define_expand "smaqa"
+  [(match_operand:SI 0 "register_operand")
+   (match_operand:SI 1 "register_operand")
+   (match_operand:V4QI 2 "register_operand")
+   (match_operand:V4QI 3 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_smaqav4qi (operands[0], operands[1],
+			    operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "umaqa"
+  [(match_operand:SI 0 "register_operand")
+   (match_operand:SI 1 "register_operand")
+   (match_operand:V4QI 2 "register_operand")
+   (match_operand:V4QI 3 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_umaqav4qi (operands[0], operands[1],
+			    operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "<su>maqav4qi"
+  [(set (match_operand:SI 0 "register_operand"             "=r")
+	(plus:SI (match_operand:SI 1 "register_operand"    " 0")
+	  (plus:SI (plus:SI
+	    (sign_extend:SI
+	      (mult:HI
+		(any_extend:HI
+		  (vec_select:QI
+		    (match_operand:V4QI 2 "register_operand" "r")
+		    (parallel [(const_int 0)])))
+		(any_extend:HI
+		  (vec_select:QI
+		    (match_operand:V4QI 3 "register_operand" "r")
+		    (parallel [(const_int 0)])))))
+	    (sign_extend:SI
+	      (mult:HI
+		(any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 1)])))
+		(any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 1)]))))))
+	  (plus:SI
+	    (sign_extend:SI
+	      (mult:HI
+		(any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 2)])))
+		(any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 2)])))))
+	    (sign_extend:SI
+	      (mult:HI
+		(any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 3)])))
+		(any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 3)])))))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "<su>maqa\t%0, %2, %3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "DI")])
+
+(define_expand "smaqa64"
+  [(match_operand:V2SI 0 "register_operand")
+   (match_operand:V2SI 1 "register_operand")
+   (match_operand:V8QI 2 "register_operand")
+   (match_operand:V8QI 3 "register_operand")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_smaqav8qi (operands[0], operands[1],
+			    operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "umaqa64"
+  [(match_operand:V2SI 0 "register_operand")
+   (match_operand:V2SI 1 "register_operand")
+   (match_operand:V8QI 2 "register_operand")
+   (match_operand:V8QI 3 "register_operand")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_umaqav8qi (operands[0], operands[1],
+			    operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "<su>maqav8qi"
+  [(set (match_operand:V2SI 0 "register_operand"             "=r")
+	(plus:V2SI (match_operand:V2SI 1 "register_operand"  " 0")
+	  (vec_concat:V2SI
+	    (plus:SI
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI
+		      (vec_select:QI
+			(match_operand:V8QI 2 "register_operand" "r")
+			(parallel [(const_int 0)])))
+		    (any_extend:HI
+		      (vec_select:QI
+			(match_operand:V8QI 3 "register_operand" "r")
+			(parallel [(const_int 0)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 1)])))
+		    (any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 1)]))))))
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 2)])))
+		    (any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 2)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 3)])))
+		    (any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 3)])))))))
+	    (plus:SI
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 4)])))
+		    (any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 4)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 5)])))
+		    (any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 5)]))))))
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 6)])))
+		    (any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 6)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (any_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 7)])))
+		    (any_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 7)]))))))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "<su>maqa\t%0, %2, %3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V2SI")])
+
+(define_expand "sumaqa"
+  [(match_operand:SI 0 "register_operand")
+   (match_operand:SI 1 "register_operand")
+   (match_operand:V4QI 2 "register_operand")
+   (match_operand:V4QI 3 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_sumaqav4qi (operands[0], operands[1],
+			     operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "sumaqav4qi"
+  [(set (match_operand:SI 0 "register_operand"             "=r")
+	(plus:SI (match_operand:SI 1 "register_operand"    " 0")
+	  (plus:SI (plus:SI
+	    (sign_extend:SI
+	      (mult:HI
+		(sign_extend:HI
+		  (vec_select:QI
+		    (match_operand:V4QI 2 "register_operand" "r")
+		    (parallel [(const_int 0)])))
+		(zero_extend:HI
+		  (vec_select:QI
+		    (match_operand:V4QI 3 "register_operand" "r")
+		    (parallel [(const_int 0)])))))
+	    (sign_extend:SI
+	      (mult:HI
+		(sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 1)])))
+		(zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 1)]))))))
+
+	  (plus:SI
+	    (sign_extend:SI
+	      (mult:HI
+		(sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 2)])))
+		(zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 2)])))))
+	    (sign_extend:SI
+	      (mult:HI
+		(sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 3)])))
+		(zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 3)])))))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "smaqa.su\t%0, %2, %3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_expand "sumaqa64"
+  [(match_operand:V2SI 0 "register_operand")
+   (match_operand:V2SI 1 "register_operand")
+   (match_operand:V8QI 2 "register_operand")
+   (match_operand:V8QI 3 "register_operand")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_sumaqav8qi (operands[0], operands[1],
+			     operands[2], operands[3]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "sumaqav8qi"
+  [(set (match_operand:V2SI 0 "register_operand"             "=r")
+	(plus:V2SI (match_operand:V2SI 1 "register_operand"  " 0")
+	  (vec_concat:V2SI
+	    (plus:SI
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI
+		      (vec_select:QI
+			(match_operand:V8QI 2 "register_operand" "r")
+			(parallel [(const_int 0)])))
+		    (zero_extend:HI
+		      (vec_select:QI
+			(match_operand:V8QI 3 "register_operand" "r")
+			(parallel [(const_int 0)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 1)])))
+		    (zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 1)]))))))
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 2)])))
+		    (zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 2)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 3)])))
+		    (zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 3)])))))))
+	    (plus:SI
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 4)])))
+		    (zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 4)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 5)])))
+		    (zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 5)]))))))
+	      (plus:SI
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 6)])))
+		    (zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 6)])))))
+		(sign_extend:SI
+		  (mult:HI
+		    (sign_extend:HI (vec_select:QI (match_dup 2) (parallel [(const_int 7)])))
+		    (zero_extend:HI (vec_select:QI (match_dup 3) (parallel [(const_int 7)]))))))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smaqa.su\t%0, %2, %3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "V2SI")])
+
+;; SMBB16, SMBT16, SMTT16
+;; 32 BIT smbb16
+(define_expand "smbb"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
+			    GEN_INT (0), GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smbt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
+			    GEN_INT (0), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smtt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:V2HI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2],
+			    GEN_INT (1), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "mulhisi3v"
+  [(set (match_operand:SI 0 "register_operand"                  "=  r,   r,   r,   r")
+	(mult:SI
+	  (sign_extend:SI
+	     (vec_select:HI
+	       (match_operand:V2HI 1 "register_operand"         "   r,   r,   r,   r")
+	       (parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
+	  (sign_extend:SI (vec_select:HI
+	       (match_operand:V2HI 2 "register_operand"         "   r,   r,   r,   r")
+	       (parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")])))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+   smbb16\t%0, %1, %2
+   smbt16\t%0, %1, %2
+   smtt16\t%0, %1, %2
+   smbt16\t%0, %2, %1"
+  [(set_attr "type"   "simd")
+   (set_attr "mode"   "SI")])
+
+;; 64 Bit smbb16
+(define_expand "smbb64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_mulv2hiv2si3v (operands[0], operands[1], operands[2],
+				GEN_INT (0), GEN_INT (2), GEN_INT (0), GEN_INT (2)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smbt64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_mulv2hiv2si3v (operands[0], operands[1], operands[2],
+				GEN_INT (0), GEN_INT (2), GEN_INT (1), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smtt64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_mulv2hiv2si3v (operands[0], operands[1], operands[2],
+				GEN_INT (1), GEN_INT (3), GEN_INT (1), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "mulv2hiv2si3v"
+  [(set (match_operand:V2SI 0 "register_operand" "=r, r, r")
+        (mult:V2SI
+	 (sign_extend:V2SI
+	  (vec_select:V2HI
+	   (match_operand:V4HI 1 "register_operand" "r, r, r")
+	   (parallel [(match_operand:SI 3 "imm2u_operand" " C00, C00, C01")
+		      (match_operand:SI 4 "imm2u_operand" " C02, C02, C03")])))
+	 (sign_extend:V2SI
+	  (vec_select:V2HI
+	   (match_operand:V4HI 2 "register_operand" "r, r, r")
+	   (parallel [(match_operand:SI 5 "imm2u_operand" " C00, C01, C01")
+		      (match_operand:SI 6 "imm2u_operand" " C02, C03, C03")])))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   smbb16\t%0, %1, %2
+   smbt16\t%0, %1, %2
+   smtt16\t%0, %1, %2"
+  [(set_attr "type"   "simd")
+   (set_attr "mode"   "DI")])
+
+;; SMBB32, SMBT32, SMTT32
+;; SMBB32, SMBT32, SMTT32
+(define_expand "smbb32"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_mulsidi3v (operands[0], operands[1], operands[2],
+			    GEN_INT (0), GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "smbt32"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_mulsidi3v (operands[0], operands[1], operands[2],
+			    GEN_INT (0), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "smtt32"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_mulsidi3v (operands[0], operands[1], operands[2],
+			    GEN_INT (1), GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "mulsidi3v"
+  [(set (match_operand:DI 0 "register_operand"                  "=  r,   r,   r,   r")
+	(mult:DI
+	  (sign_extend:DI
+	     (vec_select:SI
+	       (match_operand:V2SI 1 "register_operand"         "   r,   r,   r,   r")
+	       (parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
+	  (sign_extend:DI (vec_select:SI
+	       (match_operand:V2SI 2 "register_operand"         "   r,   r,   r,   r")
+	       (parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")])))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   smbb32\t%0, %1, %2
+   smbt32\t%0, %1, %2
+   smtt32\t%0, %1, %2
+   smbt32\t%0, %2, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "DI")])
+
+;; SMDS, SMDRS, SMXDS
+(define_insn "smds"
+  [(set (match_operand:SI 0 "register_operand"                         "=r")
+	(minus:SI
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 1 "register_operand" " r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 2 "register_operand" " r")
+			      (parallel [(const_int 1)]))))
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 2)
+			      (parallel [(const_int 0)]))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "smds\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "smds64"
+  [(set (match_operand:V2SI 0 "register_operand"                      "=r")
+	(minus:V2SI
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 1 "register_operand" "r")
+				(parallel [(const_int 1) (const_int 3)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" "r")
+				(parallel [(const_int 1) (const_int 3)]))))
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 1)
+				(parallel [(const_int 0) (const_int 2)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 0) (const_int 2)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smds\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "smdrs"
+  [(set (match_operand:SI 0 "register_operand"                         "=r")
+	(minus:SI
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 1 "register_operand" " r")
+			      (parallel [(const_int 0)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 2 "register_operand" " r")
+			      (parallel [(const_int 0)]))))
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 1)
+			      (parallel [(const_int 1)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 2)
+			      (parallel [(const_int 1)]))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "smdrs\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "smdrs64"
+  [(set (match_operand:V2SI 0 "register_operand"                      "=r")
+	(minus:V2SI
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 1 "register_operand" "r")
+				(parallel [(const_int 0) (const_int 2)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" "r")
+				(parallel [(const_int 0) (const_int 2)]))))
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 1)
+				(parallel [(const_int 1) (const_int 3)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 1) (const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smdrs\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "smxdsv"
+  [(set (match_operand:SI 0 "register_operand"                         "=r")
+	(minus:SI
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 1 "register_operand" " r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_operand:V2HI 2 "register_operand" " r")
+			      (parallel [(const_int 0)]))))
+	  (mult:SI
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:SI (vec_select:HI
+			      (match_dup 2)
+			      (parallel [(const_int 1)]))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "smxds\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+(define_insn "smxds64"
+  [(set (match_operand:V2SI 0 "register_operand"                      "=r")
+	(minus:V2SI
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 1 "register_operand" "r")
+				(parallel [(const_int 1) (const_int 3)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_operand:V4HI 2 "register_operand" "r")
+				(parallel [(const_int 0) (const_int 2)]))))
+	  (mult:V2SI
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 1)
+				(parallel [(const_int 0) (const_int 2)])))
+	    (sign_extend:V2SI (vec_select:V2HI
+				(match_dup 2)
+				(parallel [(const_int 1) (const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smxds\t%0, %1, %2"
+  [(set_attr "type" "simd")])
+
+;; SMDS32, SMDRS32, SMXDS32
+(define_insn "smxds32"
+  [(set (match_operand:DI 0 "register_operand"                         "=r")
+	(minus:DI
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 1 "register_operand" " r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 2 "register_operand" " r")
+			      (parallel [(const_int 0)]))))
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 2)
+			      (parallel [(const_int 1)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smxds32\t%0, %1, %2"
+  [(set_attr "type" "dsp")])
+
+(define_insn "smds32"
+  [(set (match_operand:DI 0 "register_operand"                         "=r")
+	(minus:DI
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 1 "register_operand" " r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 2 "register_operand" " r")
+			      (parallel [(const_int 1)]))))
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 2)
+			      (parallel [(const_int 0)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smds32\t%0, %1, %2"
+  [(set_attr "type" "dsp")])
+
+(define_insn "smdrs32"
+  [(set (match_operand:DI 0 "register_operand"                         "=r")
+	(minus:DI
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 1 "register_operand" " r")
+			      (parallel [(const_int 0)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 2 "register_operand" " r")
+			      (parallel [(const_int 0)]))))
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 1)
+			      (parallel [(const_int 1)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 2)
+			      (parallel [(const_int 1)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smdrs32\t%0, %1, %2"
+  [(set_attr "type" "dsp")])
+
+;; SMMUL, SMMUL.u
+;; rv32p smmul
+(define_insn "smulsi3_highpart"
+  [(set (match_operand:SI 0 "register_operand"                       "=r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (mult:DI
+	      (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
+	      (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))
+	    (const_int 32))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "smmul\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "HI")])
+
+(define_insn "smmul_round"
+  [(set (match_operand:SI 0 "register_operand"                       "=r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (unspec:DI [(mult:DI
+			  (sign_extend:DI (match_operand:SI 1 "register_operand" " r"))
+			  (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))]
+		       UNSPEC_ROUND)
+	    (const_int 32))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "smmul.u\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "HI")])
+
+;; rv64p smmul
+(define_insn "smulv2si3_highpart"
+  [(set (match_operand:V2SI 0 "register_operand" "=r")
+	(truncate:V2SI
+	  (lshiftrt:V2DI
+	    (mult:V2DI (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" " r"))
+		       (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r")))
+	    (const_int 32))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smmul\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V2SI")])
+
+(define_insn "smmulv2si3_round"
+  [(set (match_operand:V2SI 0 "register_operand" "=r")
+	(truncate:V2SI
+	  (lshiftrt:V2DI
+	    (unspec:V2DI [(mult:V2DI
+			    (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" " r"))
+			    (sign_extend:V2DI (match_operand:V2SI 2 "register_operand" " r")))]
+			  UNSPEC_ROUND)
+	    (const_int 32))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smmul.u\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "DI")])
+
+;; SMMWB, SMMWT
+(define_expand "smmwb"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smmwt"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "smulhisi3_highpart_1"
+  [(set (match_operand:SI 0 "register_operand"                       "= r,   r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (mult:DI
+	      (sign_extend:DI (match_operand:SI 1 "register_operand" "  r,   r"))
+	      (sign_extend:DI
+	        (vec_select:HI
+		  (match_operand:V2HI 2 "register_operand"           "  r,   r")
+		  (parallel [(match_operand:SI 3 "imm_0_1_operand"   "C00, C01")]))))
+	    (const_int 16))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+  smmwb\t%0, %1, %2
+  smmwt\t%0, %1, %2"
+[(set_attr "type" "simd")])
+
+;; RV64P smmwb
+(define_expand "smmwb64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_smulhisi3_highpart_64 (operands[0], operands[1], operands[2],
+					GEN_INT (0), GEN_INT (2)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smmwt64"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_smulhisi3_highpart_64 (operands[0], operands[1], operands[2],
+					GEN_INT (1), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "smulhisi3_highpart_64"
+  [(set (match_operand:V2SI 0 "register_operand"                       "=r,    r")
+	(vec_concat:V2SI
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (mult:DI
+		(sign_extend:DI
+		  (vec_select:SI
+		    (match_operand:V2SI 1 "register_operand"           "  r,   r")
+		      (parallel [(const_int 0)])))
+		(sign_extend:DI
+		  (vec_select:HI
+		    (match_operand:V4HI 2 "register_operand"           "  r,   r")
+		      (parallel [(match_operand:SI 3 "imm_0_1_operand"   "C00, C01")]))))
+	      (const_int 16)))
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (mult:DI
+		(sign_extend:DI
+		  (vec_select:SI
+		    (match_dup 1)
+		      (parallel [(const_int 1)])))
+		(sign_extend:DI
+		  (vec_select:HI
+		    (match_dup 2)
+		      (parallel [(match_operand:SI 4 "imm_2_3_operand"   "C02, C03")]))))
+	      (const_int 16)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   smmwb\t%0, %1, %2
+   smmwt\t%0, %1, %2"
+[(set_attr "type" "simd")])
+
+;; SMMWB.u, SMMWT.u
+(define_expand "smmwb_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smmwt_round"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "register_operand" "")
+   (match_operand:V2HI 2 "register_operand" "")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "smmw_round_internal"
+  [(set (match_operand:SI 0 "register_operand"                          "=  r,   r")
+	(truncate:SI
+	  (lshiftrt:DI
+	    (unspec:DI
+	      [(mult:DI
+		 (sign_extend:DI (match_operand:SI 1 "register_operand" "   r,   r"))
+		 (sign_extend:DI
+		   (vec_select:HI
+		     (match_operand:V2HI 2 "register_operand"           "   r,   r")
+		     (parallel [(match_operand:SI 3 "imm_0_1_operand"   " C00, C01")]))))]
+	      UNSPEC_ROUND)
+	    (const_int 16))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+   smmwb.u\t%0, %1, %2
+   smmwt.u\t%0, %1, %2"
+[(set_attr "type" "simd")])
+
+(define_expand "smmwb64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_smmw64_round_internal (operands[0], operands[1], operands[2],
+					GEN_INT (0), GEN_INT (2)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "smmwt64_round"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_smmw64_round_internal (operands[0], operands[1], operands[2],
+					GEN_INT (1), GEN_INT (3)));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "smmw64_round_internal"
+  [(set (match_operand:V2SI 0 "register_operand"                       "=r,    r")
+	(vec_concat:V2SI
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI
+	        [(mult:DI
+		  (sign_extend:DI
+		    (vec_select:SI
+		      (match_operand:V2SI 1 "register_operand"           "  r,   r")
+		      (parallel [(const_int 0)])))
+		  (sign_extend:DI
+		    (vec_select:HI
+		      (match_operand:V4HI 2 "register_operand"           "  r,   r")
+		      (parallel [(match_operand:SI 3 "imm_0_1_operand"   "C00, C01")]))))]
+	        UNSPEC_ROUND)
+	      (const_int 16)))
+	  (truncate:SI
+	    (lshiftrt:DI
+	      (unspec:DI
+		[(mult:DI
+		  (sign_extend:DI
+		    (vec_select:SI
+		      (match_dup 1)
+		      (parallel [(const_int 1)])))
+		  (sign_extend:DI
+		    (vec_select:HI
+		      (match_dup 2)
+		      (parallel [(match_operand:SI 4 "imm_2_3_operand"   "C02, C03")]))))]
+	        UNSPEC_ROUND)
+	      (const_int 16)))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   smmwb.u\t%0, %1, %2
+   smmwt.u\t%0, %1, %2"
+[(set_attr "type" "simd")])
+
+;; SMSLDA, SMSLXDA
+;; rv32p smslda
+(define_insn "smslda1"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(minus:DI
+	  (minus:DI
+	    (match_operand:DI 1 "register_operand"                         " 0")
+	    (sign_extend:DI
+	      (mult:SI
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 2 "register_operand" " r")
+				  (parallel [(const_int 1)])))
+		(sign_extend:SI (vec_select:HI
+				  (match_operand:V2HI 3 "register_operand" " r")
+				  (parallel [(const_int 1)]))))))
+	  (sign_extend:DI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 0)])))))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "smslda\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; rv64p smslda
+(define_insn "smslda64"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(minus:DI
+	  (minus:DI
+	    (match_operand:DI 1 "register_operand"                           " 0")
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 3 "register_operand" " r")
+				    (parallel [(const_int 0)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 1)])))))))
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 2)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 3)]))))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smslda\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; rv32p smslxda
+(define_insn "smslxda1"
+  [(set (match_operand:DI 0 "register_operand"                               "=r")
+	(minus:DI
+	  (minus:DI
+	    (match_operand:DI 1 "register_operand"                           " 0")
+	      (sign_extend:DI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V2HI 2 "register_operand" " r")
+				    (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V2HI 3 "register_operand" " r")
+				    (parallel [(const_int 0)]))))))
+	  (sign_extend:DI
+	    (mult:SI
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:SI (vec_select:HI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "smslxda\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; rv64p smslxda
+(define_insn "smslxda64"
+  [(set (match_operand:DI 0 "register_operand"                             "=r")
+	(minus:DI
+	  (minus:DI
+	    (match_operand:DI 1 "register_operand"                           " 0")
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 0)])))
+		  (sign_extend:SI (vec_select:HI
+				    (match_operand:V4HI 3 "register_operand" " r")
+				    (parallel [(const_int 1)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 0)])))))))
+	    (sign_extend:DI
+	      (minus:SI
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 3)]))))
+		(mult:SI
+		  (sign_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)])))
+		  (sign_extend:SI (vec_select:HI (match_dup 3) (parallel [(const_int 2)]))))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "smslxda\t%0, %2, %3"
+  [(set_attr "type" "dsp64")])
+
+;; SMSR64, UMSR64
+(define_insn "v<su>msr64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(minus:DI
+	  (minus:DI
+	  (match_operand:DI 1 "register_operand"    " 0")
+	    (mult:DI
+	      (any_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 2 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (any_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 3 "register_operand" " r")
+		  (parallel [(const_int 0)])))))
+	    (mult:DI
+	      (any_extend:DI
+		(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	      (any_extend:DI
+		(vec_select:SI (match_dup 3) (parallel [(const_int 1)]))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "<su>msr64\t%0, %2, %3"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; SMUL 8|16, SMULX 8|16, UMUL 8|16, UMULX 8|16
+;; SMUL8
+(define_insn "smul8"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_SMUL8))]
+  "TARGET_ZPSF"
+  "smul8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; SMULX8
+(define_insn "smulx8"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_SMULX8))]
+  "TARGET_ZPSF"
+  "smulx8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; UMUL8
+(define_insn "umul8"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_UMUL8))]
+  "TARGET_ZPSF"
+  "umul8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; UMULX8
+(define_insn "umulx8"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_UMULX8))]
+  "TARGET_ZPSF"
+  "umulx8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; S|U MUL16
+(define_insn "<su>mul16"
+  [(set (match_operand:V2SI 0 "register_operand"                             "=r")
+	(mult:V2SI (any_extend:V2SI (match_operand:V2HI 1 "register_operand" "%r"))
+		   (any_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "<su>mul16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V2SI")])
+
+(define_insn "smul16_64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_SMUL16))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "smul16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "DI")])
+
+(define_insn "umul16_64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_UMUL16))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "umul16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "DI")])
+
+;; S|U MULX16
+(define_insn "<su>mulx16"
+  [(set (match_operand:V2SI 0 "register_operand"         "=r")
+	(vec_merge:V2SI
+	  (vec_duplicate:V2SI
+	    (mult:SI
+	      (any_extend:SI
+		(vec_select:HI
+		  (match_operand:V2HI 1 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (any_extend:SI
+		(vec_select:HI
+		  (match_operand:V2HI 2 "register_operand" " r")
+		  (parallel [(const_int 1)])))))
+	  (vec_duplicate:V2SI
+	    (mult:SI
+	      (any_extend:SI
+		(vec_select:HI
+		  (match_dup 1)
+		  (parallel [(const_int 1)])))
+	      (any_extend:SI
+		(vec_select:HI
+		  (match_dup 2)
+		  (parallel [(const_int 0)])))))
+	  (const_int 1)))]
+  "TARGET_ZPSF && !TARGET_64BIT"
+  "<su>mulx16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V2SI")])
+
+;; RV64P
+(define_insn "smulx16_64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_SMULX16))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "smulx16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "DI")])
+
+(define_insn "umulx16_64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:SI 1 "register_operand" " r")
+		    (match_operand:SI 2 "register_operand" " r")]
+		    UNSPEC_UMULX16))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "umulx16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "DI")])
+
+;; RVP SHIFT
+;; SRA[I] 8|16|32, SRL[I] 8|16|32, SLL[I] 8|16|32
+;; SRA32, SRL32, SLL32
+(define_insn "<rvp_optab>v2si3"
+  [(set (match_operand:V2SI 0 "register_operand"                 "=  r, r")
+	(any_shift:V2SI (match_operand:V2SI 1 "register_operand" "   r, r")
+			(match_operand:SI   2  "rimm5u_operand"  " u05, r")))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   <rvp_insn>i32\t%0, %1, %2
+   <rvp_insn>32\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "V2SI,  V2SI")])
+
+(define_expand "<shift><mode>3"
+  [(set (match_operand:VHI 0 "register_operand"                "")
+	(any_shift:VHI (match_operand:VHI 1 "register_operand" "")
+		       (match_operand:SI   2 "rimm4u_operand"  "")))]
+  "TARGET_ZPN"
+{
+  if (operands[2] == const0_rtx)
+    {
+      emit_move_insn (operands[0], operands[1]);
+      DONE;
+    }
+})
+
+(define_insn "*riscv_lshr<mode>3"
+  [(set (match_operand:VHI 0 "register_operand"               "=  r, r")
+	(lshiftrt:VHI (match_operand:VHI 1 "register_operand" "   r, r")
+		      (match_operand:SI 2  "rimm4u_operand"   " u04, r")))]
+  "TARGET_ZPN"
+  "@
+   srli16\t%0, %1, %2
+   srl16\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "*riscv_ashl<mode>3"
+  [(set (match_operand:VHI 0 "register_operand"             "=  r, r")
+	(ashift:VHI (match_operand:VHI 1 "register_operand" "   r, r")
+		    (match_operand:SI 2  "rimm4u_operand"   " u04, r")))]
+  "TARGET_ZPN"
+  "@
+   slli16\t%0, %1, %2
+   sll16\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "*riscv_ashr<mode>3"
+  [(set (match_operand:VHI 0 "register_operand"               "=   r, r")
+	(ashiftrt:VHI (match_operand:VHI 1 "register_operand" "    r, r")
+		      (match_operand:SI 2  "rimm4u_operand"   " u04, r")))]
+  "TARGET_ZPN"
+  "@
+   srai16\t%0, %1, %2
+   sra16\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_expand "<shift><mode>3"
+  [(set (match_operand:VQI 0 "register_operand"                "")
+	(any_shift:VQI (match_operand:VQI 1 "register_operand" "")
+			(match_operand:SI 2 "rimm3u_operand" "")))]
+  "TARGET_ZPN"
+{
+  if (operands[2] == const0_rtx)
+    {
+      emit_move_insn (operands[0], operands[1]);
+      DONE;
+    }
+})
+
+(define_insn "*riscv_ashr<mode>3"
+  [(set (match_operand:VQI 0 "register_operand"               "=  r, r")
+	(ashiftrt:VQI (match_operand:VQI 1 "register_operand" "   r, r")
+		       (match_operand:SI 2 "rimm3u_operand"   " u03, r")))]
+  "TARGET_ZPN"
+  "@
+   srai8\t%0, %1, %2
+   sra8\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "*riscv_lshr<mode>3"
+  [(set (match_operand:VQI 0 "register_operand"               "=  r, r")
+	(lshiftrt:VQI (match_operand:VQI 1 "register_operand" "   r, r")
+		       (match_operand:SI 2 "rimm3u_operand"   " u03, r")))]
+  "TARGET_ZPN"
+  "@
+   srli8\t%0, %1, %2
+   srl8\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "*riscv_ashl<mode>3"
+  [(set (match_operand:VQI 0 "register_operand"             "=  r, r")
+	(ashift:VQI (match_operand:VQI 1 "register_operand" "   r, r")
+		     (match_operand:SI 2   "rimm3u_operand" " u03, r")))]
+  "TARGET_ZPN"
+  "@
+   slli8\t%0, %1, %2
+   sll8\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+;; SRA[I] 8|16|32 .u
+(define_insn "sra8_round<mode>"
+  [(set (match_operand:VQI 0 "register_operand"                            "=  r, r")
+	(unspec:VQI [(ashiftrt:VQI (match_operand:VQI 1 "register_operand" "   r, r")
+				   (match_operand:SI 2  "rimm3u_operand"   " u03, r"))]
+		      UNSPEC_ROUND))]
+  "TARGET_ZPN"
+  "@
+   srai8.u\t%0, %1, %2
+   sra8.u\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "sra16_round<mode>"
+  [(set (match_operand:VHI 0 "register_operand"                            "=  r, r")
+	(unspec:VHI [(ashiftrt:VHI (match_operand:VHI 1 "register_operand" "   r, r")
+				   (match_operand:SI 2  "rimm4u_operand"   " u04, r"))]
+		     UNSPEC_ROUND))]
+  "TARGET_ZPN"
+  "@
+   srai16.u\t%0, %1, %2
+   sra16.u\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "sra32_round"
+  [(set (match_operand:V2SI 0 "register_operand"                              "=  r, r")
+	(unspec:V2SI [(ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "   r, r")
+				     (match_operand:SI 2   "rimm5u_operand"   " u05, r"))]
+		       UNSPEC_ROUND))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   srai32.u\t%0, %1, %2
+   sra32.u\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "V2SI,  V2SI")])
+
+;; SRL[I] 8|16|32 .u
+(define_insn "srl8_round<mode>"
+  [(set (match_operand:VQI 0 "register_operand"                            "=  r, r")
+	(unspec:VQI [(lshiftrt:VQI (match_operand:VQI 1 "register_operand" "   r, r")
+				   (match_operand:SI 2  "rimm3u_operand"   " u03, r"))]
+		      UNSPEC_ROUND))]
+  "TARGET_ZPN"
+  "@
+   srli8.u\t%0, %1, %2
+   srl8.u\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "srl16_round<mode>"
+  [(set (match_operand:VHI 0 "register_operand"                            "=  r, r")
+	(unspec:VHI [(lshiftrt:VHI (match_operand:VHI 1 "register_operand" "   r, r")
+				   (match_operand:SI 2  "rimm4u_operand"   " u04, r"))]
+		     UNSPEC_ROUND))]
+  "TARGET_ZPN"
+  "@
+   srli16.u\t%0, %1, %2
+   srl16.u\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "<MODE>, <MODE>")])
+
+(define_insn "srl32_round"
+  [(set (match_operand:V2SI 0 "register_operand"                              "=  r, r")
+	(unspec:V2SI [(lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "   r, r")
+				     (match_operand:SI 2   "rimm5u_operand"   " u05, r"))]
+		       UNSPEC_ROUND))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   srli32.u\t%0, %1, %2
+   srl32.u\t%0, %1, %2"
+  [(set_attr "type" "simd, simd")
+   (set_attr "mode" "V2SI,  V2SI")])
+
+(define_insn "sraiw_u"
+  [(set (match_operand:SI 0 "register_operand"             "=  r")
+	(unspec:SI [(match_operand:SI 1 "register_operand" "   r")
+		    (match_operand:SI 2 "imm5u_operand"    " u05")]
+		    UNSPEC_ROUND64))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "sraiw.u\t%0, %1, %2"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "DI")])
+
+(define_insn "sraiu"
+  [(set (match_operand:SI 0 "register_operand"                          "=  r, r")
+	(unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" "   r, r")
+				 (match_operand:SI 2 "rimm5u_operand"   " u05, r"))]
+		    UNSPEC_ROUND))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "@
+   srai.u\t%0, %1, %2
+   sra.u\t%0, %1, %2"
+  [(set_attr "type"   "simd")
+   (set_attr "mode"   "SI")])
+
+(define_insn "sraiu64"
+  [(set (match_operand:DI 0 "register_operand"                          "=  r, r")
+	(unspec:DI [(ashiftrt:DI (match_operand:DI 1 "register_operand" "   r, r")
+				 (match_operand:DI 2 "rimm6u_operand"   " u06, r"))]
+		    UNSPEC_ROUND))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   srai.u\t%0, %1, %2
+   sra.u\t%0, %1, %2"
+  [(set_attr "type"   "simd")
+   (set_attr "mode"   "DI")])
+
+;; STAS 16|32
+(define_expand "stas<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_stas<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "stas<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "stas<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+;; STAS16 in RV64P
+(define_expand "stas16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_stas16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "stas16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (minus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				     (parallel [(const_int 0)]))
+		      (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				     (parallel [(const_int 0)])))
+	    (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+		     (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+	  (vec_concat:V2HI
+	    (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		      (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+	    (plus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+		      (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "stas16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; STSA 16|32
+(define_expand "stsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_stsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "stsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "stsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+(define_expand "stsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_stsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "stsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (plus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				    (parallel [(const_int 0)]))
+		     (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				    (parallel [(const_int 0)])))
+	    (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+		      (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+	  (vec_concat:V2HI
+	    (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+		     (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+	    (minus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+		       (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "stsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; SUNPKD810, ZUNPKD810
+(define_insn "<zs>unpkd810_imp"
+  [(set (match_operand:V2HI 0 "register_operand"                     "=r")
+	(vec_merge:V2HI
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_operand:V4QI 1 "register_operand"             " r")
+		(parallel [(const_int 1)]))))
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_dup 1)
+		(parallel [(const_int 0)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "<zs>unpkd810\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V2HI")])
+
+;; SUNPKD810 in RV32P
+(define_expand "sunpkd810"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_sunpkd810_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "zunpkd810"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_zunpkd810_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+;; ZUNPKD810 and SUNPKD810 in RV32P
+(define_insn "<zs>unpkd810_64"
+  [(set (match_operand:V4HI 0 "register_operand"                    "=r")
+	(vec_select:V4HI
+	  (any_extend:V8HI (match_operand:V8QI 1 "register_operand" "r"))
+	  (parallel [(const_int 0) (const_int 1)
+		     (const_int 4) (const_int 5)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "<zs>unpkd810\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V4HI")])
+
+;; SUNPKD820, ZUNPKD820
+(define_insn "<zs>unpkd820_imp"
+  [(set (match_operand:V2HI 0 "register_operand"                     "=r")
+	(vec_merge:V2HI
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_operand:V4QI 1 "register_operand"             " r")
+		(parallel [(const_int 2)]))))
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_dup 1)
+		(parallel [(const_int 0)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "<zs>unpkd820\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V2HI")])
+
+;; ZUNPKD820 RV32P
+(define_expand "zunpkd820"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_zunpkd820_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+;; SUNPKD820 RV32P
+(define_expand "sunpkd820"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_sunpkd820_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+;; SUNPKD820, ZUNPKD820 in RV64P
+(define_insn "<zs>unpkd820_64"
+  [(set (match_operand:V4HI 0 "register_operand"                    "=r")
+	(vec_select:V4HI
+	  (any_extend:V8HI (match_operand:V8QI 1 "register_operand" "r"))
+	  (parallel [(const_int 0) (const_int 2)
+		     (const_int 4) (const_int 6)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "<zs>unpkd820\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V4HI")])
+
+;; SUNPKD830, ZUNPKD830
+;; RV32P
+(define_insn "<zs>unpkd830_imp"
+  [(set (match_operand:V2HI 0 "register_operand"                     "=r")
+	(vec_merge:V2HI
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_operand:V4QI 1 "register_operand"             " r")
+		(parallel [(const_int 3)]))))
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_dup 1)
+		(parallel [(const_int 0)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "<zs>unpkd830\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V2HI")])
+
+(define_expand "sunpkd830"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_sunpkd830_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "zunpkd830"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_zunpkd830_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+;; RV64P
+(define_insn "<zs>unpkd830_64"
+  [(set (match_operand:V4HI 0 "register_operand"                    "=r")
+	(vec_select:V4HI
+	  (any_extend:V8HI (match_operand:V8QI 1 "register_operand" "r"))
+	  (parallel [(const_int 0) (const_int 3)
+		     (const_int 4) (const_int 7)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "<zs>unpkd830\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V4HI")])
+
+;; SUNPKD831, ZUNPKD831
+;; RV32P
+(define_expand "sunpkd831"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_sunpkd831_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "zunpkd831"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_zunpkd831_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "<zs>unpkd831_imp"
+  [(set (match_operand:V2HI 0 "register_operand"                     "=r")
+	(vec_merge:V2HI
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_operand:V4QI 1 "register_operand"             " r")
+		(parallel [(const_int 3)]))))
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_dup 1)
+		(parallel [(const_int 1)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "<zs>unpkd831\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V2HI")])
+
+;; RV64P
+(define_insn "<zs>unpkd831_64"
+  [(set (match_operand:V4HI 0 "register_operand"                    "=r")
+	(vec_select:V4HI
+	  (any_extend:V8HI (match_operand:V8QI 1 "register_operand" "r"))
+	  (parallel [(const_int 1) (const_int 3)
+		     (const_int 5) (const_int 7)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "<zs>unpkd831\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V4HI")])
+
+;; SUNPKD832, ZUNPKD832
+;; RV32P
+(define_expand "sunpkd832"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_sunpkd832_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_expand "zunpkd832"
+  [(match_operand:V2HI 0 "register_operand")
+   (match_operand:V4QI 1 "register_operand")]
+  "TARGET_ZPN && !TARGET_64BIT"
+{
+  emit_insn (gen_zunpkd832_imp (operands[0], operands[1]));
+  DONE;
+}
+[(set_attr "type" "dsp")])
+
+(define_insn "<zs>unpkd832_imp"
+  [(set (match_operand:V2HI 0 "register_operand"                     "=r")
+	(vec_merge:V2HI
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_operand:V4QI 1 "register_operand"             " r")
+		(parallel [(const_int 3)]))))
+	  (vec_duplicate:V2HI
+	    (any_extend:HI
+	      (vec_select:QI
+		(match_dup 1)
+		(parallel [(const_int 2)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN && !TARGET_64BIT"
+  "<zs>unpkd832\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V2HI")])
+
+;; RV64P
+(define_insn "<zs>unpkd832_64"
+  [(set (match_operand:V4HI 0 "register_operand"                    "=r")
+	(vec_select:V4HI
+	  (any_extend:V8HI (match_operand:V8QI 1 "register_operand" "r"))
+	  (parallel [(const_int 2) (const_int 3)
+		     (const_int 6) (const_int 7)])))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "<zs>unpkd832\t%0, %1"
+  [(set_attr "type" "dsp")
+   (set_attr "mode"  "V4HI")])
+
+;; SWAP8
+(define_insn "bswap8"
+  [(set (match_operand:V4QI 0 "register_operand" "=r")
+	(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "r")] UNSPEC_BSWAP))]
+  "TARGET_ZPN"
+  { return TARGET_ZBPBO ? "rev8.h\t%0, %1" : "swap8\t%0, %1"; }
+  [(set_attr "type"  "dsp")
+   (set_attr "mode"  "V4QI")])
+
+(define_insn "bswap8_64"
+  [(set (match_operand:V8QI 0 "register_operand" "=r")
+	(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "r")] UNSPEC_BSWAP))]
+  "TARGET_ZPN"
+   { return TARGET_ZBPBO ? "rev8.h\t%0, %1" : "swap8\t%0, %1"; }
+  [(set_attr "type"  "dsp")
+   (set_attr "mode"  "V8QI")])
+
+;; UCLIP8|16|32
+(define_insn "uclip8<mode>"
+  [(set (match_operand:VQI 0 "register_operand"               "=  r")
+	(unspec:VQI [(match_operand:VQI 1 "register_operand"  "   r")
+		     (match_operand:SI 2 "imm3u_operand"      " u03")]
+		     UNSPEC_UCLIP))]
+  "TARGET_ZPN"
+  "uclip8\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "uclip16<mode>"
+  [(set (match_operand:VHI 0 "register_operand"               "=   r")
+	(unspec:VHI [(match_operand:VHI 1 "register_operand"  "    r")
+		      (match_operand:SI 2 "imm4u_operand"     " u04")]
+		     UNSPEC_UCLIP))]
+  "TARGET_ZPN"
+  "uclip16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "uclip32<VD_SI:mode><X:mode>"
+  [(set (match_operand:VD_SI 0 "register_operand" "=r")
+	(unspec:VD_SI [(match_operand:VD_SI 1 "register_operand" "r")
+		       (match_operand:X 2 "immediate_operand" "i")] UNSPEC_UCLIP_OV))]
+  "TARGET_ZPN"
+  "uclip32\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<VD_SI:MODE>")])
+
+;; UCMPLE8|16
+(define_insn "ucmple<mode>"
+  [(set (match_operand:VQIHI 0 "register_operand"                          "=r")
+	(unspec:VQIHI [(leu:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
+				  (match_operand:VQIHI 2 "register_operand" " r"))]
+		       UNSPEC_VEC_COMPARE))]
+  "TARGET_ZPN"
+  "ucmple<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "<MODE>")])
+
+;; UCMPLT8|16
+(define_insn "ucmplt<mode>"
+  [(set (match_operand:VQIHI 0 "register_operand"                          "=r")
+	(unspec:VQIHI [(ltu:VQIHI (match_operand:VQIHI 1 "register_operand" " r")
+				  (match_operand:VQIHI 2 "register_operand" " r"))]
+		       UNSPEC_VEC_COMPARE))]
+  "TARGET_ZPN"
+  "ucmplt<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "SI")])
+
+;; RV64P ukmar64
+(define_insn "vukmar64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(us_plus:DI (match_operand:DI 1 "register_operand"    " 0")
+	  (plus:DI
+	    (mult:DI
+	      (zero_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 2 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (zero_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 3 "register_operand" " r")
+		  (parallel [(const_int 0)]))))
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 3) (parallel [(const_int 1)])))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "ukmar64\t%0, %2, %3"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; RV64P ukmsr64
+(define_insn "vukmsr64"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(us_minus:DI
+	  (minus:DI
+	    (match_operand:DI 1 "register_operand"    " 0")
+	    (mult:DI
+	      (zero_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 2 "register_operand" " r")
+		  (parallel [(const_int 0)])))
+	      (zero_extend:DI
+		(vec_select:SI
+		  (match_operand:V2SI 3 "register_operand" " r")
+		  (parallel [(const_int 0)])))))
+	    (mult:DI
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
+	      (sign_extend:DI
+		(vec_select:SI (match_dup 3) (parallel [(const_int 1)]))))))]
+  "TARGET_ZPSF && TARGET_64BIT"
+  "ukmsr64\t%0, %2, %3"
+  [(set_attr "type" "dsp64")
+   (set_attr "mode" "DI")])
+
+;; UKSTAS 16|32
+(define_expand "ukstas<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_ukstas<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukstas<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (us_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (us_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "ukstas<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+;; RV64P ukstas16
+(define_expand "ukstas16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_ukstas16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukstas16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (us_minus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+					(parallel [(const_int 0)]))
+			 (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+					(parallel [(const_int 0)])))
+	    (us_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+	  (vec_concat:V2HI
+	    (us_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+	    (us_plus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "ukstas16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; UKSTSA 16|32
+;; ukstsav2si for ukstsa16
+;; ukstsav2si for ukstsa32
+(define_expand "ukstsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_ukstsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukstsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"         "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (us_minus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 1 "register_operand" " r")
+		(parallel [(const_int 0)]))
+	      (vec_select:<VNHALF>
+		(match_operand:VSHI 2 "register_operand" " r")
+		(parallel [(const_int 0)]))))
+	  (vec_duplicate:VSHI
+	    (us_plus:<VNHALF>
+	      (vec_select:<VNHALF>
+		(match_dup 1)
+		(parallel [(const_int 1)]))
+	      (vec_select:<VNHALF>
+		(match_dup 2)
+		(parallel [(const_int 1)]))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "ukstsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+;; RV64P ukstsa16
+(define_expand "ukstsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_ukstsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "ukstsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (us_plus:HI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+				       (parallel [(const_int 0)]))
+			(vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+				       (parallel [(const_int 0)])))
+	    (us_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
+			 (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+	  (vec_concat:V2HI
+	    (us_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
+			(vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
+	    (us_minus:HI  (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
+			  (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "ukstsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; URSTAS 16|32
+(define_expand "urstas<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_urstas<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urstas<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+		(minus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 0)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 1)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 1)))]
+  "TARGET_ZPN"
+  "urstas<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+;; urstas16 in RV64P
+(define_expand "urstas16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_urstas16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urstas16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 0)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "urstas16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; URSTSA 16|32
+(define_expand "urstsa<mode>"
+  [(match_operand:VSHI 0 "register_operand" "")
+   (match_operand:VSHI 1 "register_operand" "")
+   (match_operand:VSHI 2 "register_operand" "")]
+  "TARGET_ZPN"
+{
+  emit_insn (gen_urstsa<mode>_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urstsa<mode>_le"
+  [(set (match_operand:VSHI 0 "register_operand"           "=r")
+	(vec_merge:VSHI
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+	        (minus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 1 "register_operand" " r")
+		      (parallel [(const_int 0)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_operand:VSHI 2 "register_operand" " r")
+		      (parallel [(const_int 0)]))))
+		(const_int 1))))
+	  (vec_duplicate:VSHI
+	    (truncate:<VNHALF>
+	      (lshiftrt:<VSH_EXT>
+		(plus:<VSH_EXT>
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 1)
+		      (parallel [(const_int 1)])))
+		  (zero_extend:<VSH_EXT>
+		    (vec_select:<VNHALF>
+		      (match_dup 2)
+		      (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (const_int 2)))]
+  "TARGET_ZPN"
+  "urstsa<bits>\t%0, %1, %2"
+  [(set_attr "type" "simd")]
+)
+
+;; urstsa16 in RV64P
+(define_expand "urstsa16_64"
+  [(match_operand:V4HI 0 "register_operand" "")
+   (match_operand:V4HI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_urstsa16_64_le (operands[0], operands[1], operands[2]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "urstsa16_64_le"
+  [(set (match_operand:V4HI 0 "register_operand"         "=r")
+	(vec_concat:V4HI
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" " r")
+						 (parallel [(const_int 0)])))
+		  (zero_extend:SI (vec_select:HI (match_operand:V4HI 2 "register_operand" " r")
+						  (parallel [(const_int 0)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
+		(const_int 1))))
+	  (vec_concat:V2HI
+	    (truncate:HI
+	      (lshiftrt:SI
+		(plus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 2)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))))
+		(const_int 1)))
+	    (truncate:HI
+	      (lshiftrt:SI
+		(minus:SI
+		  (zero_extend:SI (vec_select:HI (match_dup 1) (parallel [(const_int 3)])))
+		  (zero_extend:SI (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
+		(const_int 1))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "urstsa16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; WEXTI, WEXT
+(define_insn "wext"
+  [(set (match_operand:SI 0 "register_operand"     "=r,  r")
+	(truncate:SI
+	  (ashiftrt:DI
+	    (match_operand:DI 1 "register_operand" " r,  r")
+	    (match_operand:SI 2 "rimm5u_operand"   " r,u05"))))]
+  "TARGET_ZPSF && !TARGET_ZBPBO && !TARGET_64BIT"
+  "@
+   wext\t%0, %1, %2
+   wexti\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_insn "wext64"
+  [(set (match_operand:DI 0 "register_operand"     "=r,  r")
+	(sign_extend:DI
+	  (truncate:SI
+	    (ashiftrt:DI
+	      (match_operand:DI 1 "register_operand" " r,  r")
+	      (match_operand:SI 2 "rimm5u_operand"   " r,u05")))))]
+  "TARGET_ZPSF && !TARGET_ZBPBO && TARGET_64BIT"
+  "@
+   wext\t%0, %1, %2
+   wexti\t%0, %1, %2"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "DI")])
+
+;; KDMBB16, KDMBT16, KDMTT16
+(define_insn "kdmbb16"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "r")
+		      (match_operand:V4HI 2 "register_operand" "r")] UNSPEC_KDMBB16))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kdmbb16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_insn "kdmbt16"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "r")
+		      (match_operand:V4HI 2 "register_operand" "r")] UNSPEC_KDMBT16))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kdmbt16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_insn "kdmtt16"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "r")
+		      (match_operand:V4HI 2 "register_operand" "r")] UNSPEC_KDMTT16))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kdmtt16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; KDMABB16, KDMABT16, KDMATT16
+(define_expand "kdmabb16"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_vkdma_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), GEN_INT (0), GEN_INT (2),
+				 GEN_INT (2), operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kdmabt16"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_vkdma_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), GEN_INT (1), GEN_INT (2),
+				 GEN_INT (3), operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kdmatt16"
+  [(match_operand:V2SI 0 "register_operand" "")
+   (match_operand:V2SI 1 "register_operand" "")
+   (match_operand:V4HI 2 "register_operand" "")
+   (match_operand:V4HI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_vkdma_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (1), GEN_INT (1), GEN_INT (3),
+				 GEN_INT (3), operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "vkdma_internal"
+  [(set (match_operand:V2SI 0 "register_operand"                      "=   r,   r,   r,   r")
+	(ss_plus:V2SI
+	  (vec_concat:V2SI
+	    (ashift:SI
+	      (mult:SI
+		(sign_extend:SI
+		  (vec_select:HI
+		    (match_operand:V4HI 1 "register_operand"          "   r,   r,   r,   r")
+		    (parallel [(match_operand:SI 3 "imm_0_1_operand"  " C00, C00, C01, C01")])))
+		(sign_extend:SI
+		  (vec_select:HI
+		    (match_operand:V4HI 2 "register_operand"          "   r,   r,   r,   r")
+		    (parallel [(match_operand:SI 4 "imm_0_1_operand"  " C00, C01, C01, C00")]))))
+	      (const_int 1))
+	    (ashift:SI
+	      (mult:SI
+		(sign_extend:SI
+		  (vec_select:HI
+		    (match_dup 1)
+		    (parallel [(match_operand:SI 5 "imm_2_3_operand"  " C02, C02, C03, C03")])))
+		(sign_extend:SI
+		  (vec_select:HI
+		    (match_dup 2)
+		    (parallel [(match_operand:SI 6 "imm_2_3_operand"  " C02, C03, C03, C02")]))))
+	      (const_int 1)))
+	  (match_operand:V2SI 7 "register_operand"                    "   0,   0,   0,   0")))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+   kdmabb16\t%0, %1, %2
+   kdmabt16\t%0, %1, %2
+   kdmatt16\t%0, %1, %2
+   kdmabt16\t%0, %2, %1"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V2SI")])
+
+;; KHMBB16, KHMBT16, KHMTT16
+(define_insn "khmbb16"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "r")
+		      (match_operand:V4HI 2 "register_operand" "r")] UNSPEC_KHMBB16))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "khmbb16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_insn "khmbt16"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "r")
+		      (match_operand:V4HI 2 "register_operand" "r")] UNSPEC_KHMBT16))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "khmbt16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+(define_insn "khmtt16"
+  [(set (match_operand:V4HI 0 "register_operand" "=r")
+	(unspec:V4HI [(match_operand:V4HI 1 "register_operand" "r")
+		      (match_operand:V4HI 2 "register_operand" "r")] UNSPEC_KHMTT16))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "khmtt16\t%0, %1, %2"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "V4HI")])
+
+;; KMABB32, KMABT32, KMATT32
+(define_expand "kmabb32"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V2SI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kma32_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), GEN_INT (0),
+				 operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmabt32"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V2SI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kma32_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (0), GEN_INT (1),
+				 operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_expand "kmatt32"
+  [(match_operand:DI 0 "register_operand" "")
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:V2SI 2 "register_operand" "")
+   (match_operand:V2SI 3 "register_operand" "")]
+  "TARGET_ZPN && TARGET_64BIT"
+{
+  emit_insn (gen_kma32_internal (operands[0], operands[2], operands[3],
+				 GEN_INT (1), GEN_INT (1),
+				 operands[1]));
+  DONE;
+}
+[(set_attr "type" "simd")])
+
+(define_insn "kma32_internal"
+  [(set (match_operand:DI 0 "register_operand"                   "=   r,   r,   r,   r")
+	(ss_plus:DI
+	  (mult:DI
+	    (sign_extend:DI
+	      (vec_select:SI
+		(match_operand:V2SI 1 "register_operand"         "   r,   r,   r,   r")
+	        (parallel [(match_operand:SI 3 "imm_0_1_operand" " C00, C00, C01, C01")])))
+	    (sign_extend:DI
+	      (vec_select:SI
+	        (match_operand:V2SI 2 "register_operand"         "   r,   r,   r,   r")
+	        (parallel [(match_operand:SI 4 "imm_0_1_operand" " C00, C01, C01, C00")]))))
+	  (match_operand:DI 5 "register_operand"                 "   0,   0,   0,   0")))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "@
+  kmabb32\t%0, %1, %2
+  kmabt32\t%0, %1, %2
+  kmatt32\t%0, %1, %2
+  kmabt32\t%0, %2, %1"
+  [(set_attr "type" "simd")
+   (set_attr "mode" "DI")])
+
+;; KMADA32, KMAXDA32
+(define_insn "kmada32"
+  [(set (match_operand:DI 0 "register_operand"                           "=r")
+	(ss_plus:DI
+	  (match_operand:DI 1 "register_operand"                         " 0")
+	  (ss_plus:DI
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 3 "register_operand" " r")
+				(parallel [(const_int 1)]))))
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 3)
+				(parallel [(const_int 0)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmada32\t%0, %2, %3"
+  [(set_attr "type" "dsp")])
+
+(define_insn "kmaxda32"
+  [(set (match_operand:DI 0 "register_operand"                           "=r")
+	(ss_plus:DI
+	  (match_operand:DI 1 "register_operand"                         " 0")
+	  (ss_plus:DI
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmaxda32\t%0, %2, %3"
+  [(set_attr "type" "dsp")])
+
+;; KMDA32, KMXDA32
+(define_insn "kmda32"
+  [(set (match_operand:DI 0 "register_operand"                         "=r")
+	(ss_plus:DI
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 1 "register_operand" "r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 2 "register_operand" "r")
+			      (parallel [(const_int 1)]))))
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 2)
+			      (parallel [(const_int 0)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmda32\t%0, %1, %2"
+  [(set_attr "type" "dsp")])
+
+(define_insn "kmxda32"
+  [(set (match_operand:DI 0 "register_operand"                        "=r")
+	(ss_plus:DI
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 1 "register_operand" "r")
+			      (parallel [(const_int 1)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_operand:V2SI 2 "register_operand" "r")
+			      (parallel [(const_int 0)]))))
+	  (mult:DI
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 1)
+			      (parallel [(const_int 0)])))
+	    (sign_extend:DI (vec_select:SI
+			      (match_dup 2)
+			      (parallel [(const_int 1)]))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmxda32\t%0, %1, %2"
+  [(set_attr "type" "dsp")])
+
+;; KMADS32, KMADRS32, KMAXDS32
+(define_insn "kmads32"
+  [(set (match_operand:DI 0 "register_operand"                           "=r")
+	(ss_plus:DI
+	  (match_operand:DI 1 "register_operand"                         " 0")
+	  (ss_minus:DI
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 3 "register_operand" " r")
+				(parallel [(const_int 1)]))))
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 3)
+				(parallel [(const_int 0)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmads32\t%0, %2, %3"
+  [(set_attr "type" "dsp")])
+
+(define_insn "kmadrs32"
+  [(set (match_operand:DI 0 "register_operand"                           "=r")
+	(ss_plus:DI
+	  (match_operand:DI 1 "register_operand"                         " 0")
+	  (ss_minus:DI
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 2 "register_operand" " r")
+				(parallel [(const_int 0)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 2)
+				(parallel [(const_int 1)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmadrs32\t%0, %2, %3"
+  [(set_attr "type" "dsp")])
+
+(define_insn "kmaxds32"
+  [(set (match_operand:DI 0 "register_operand"                           "=r")
+	(ss_plus:DI
+	  (match_operand:DI 1 "register_operand"                         " 0")
+	  (ss_minus:DI
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmaxds32\t%0, %2, %3"
+  [(set_attr "type" "dsp")])
+
+;; KMSDA32, KMSXDA32
+(define_insn "kmsda32"
+  [(set (match_operand:DI 0 "register_operand"                           "=r")
+	(ss_minus:DI
+	  (match_operand:DI 1 "register_operand"                         " 0")
+	  (ss_minus:DI
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 3 "register_operand" " r")
+				(parallel [(const_int 1)]))))
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 3)
+				(parallel [(const_int 0)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmsda32\t%0, %2, %3"
+  [(set_attr "type" "dsp")])
+
+(define_insn "kmsxda32"
+  [(set (match_operand:DI 0 "register_operand"                           "=r")
+	(ss_minus:DI
+	  (match_operand:DI 1 "register_operand"                         " 0")
+	  (ss_minus:DI
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 2 "register_operand" " r")
+				(parallel [(const_int 1)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_operand:V2SI 3 "register_operand" " r")
+				(parallel [(const_int 0)]))))
+	    (mult:DI
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 2)
+				(parallel [(const_int 0)])))
+	      (sign_extend:DI (vec_select:SI
+				(match_dup 3)
+				(parallel [(const_int 1)])))))))]
+  "TARGET_ZPN && TARGET_64BIT"
+  "kmsxda32\t%0, %2, %3"
+  [(set_attr "type" "dsp")])
+
+;; rev
+(define_expand "rev<mode>"
+  [(match_operand:X 0 "register_operand")
+   (match_operand:X 1 "register_operand")]
+  "TARGET_ZBPBO"
+{
+  emit_insn (gen_rev<mode>_internal (operands[0], operands[1]));
+  DONE;
+})
+
+(define_insn "revsi_internal"
+  [(set (match_operand:SI 0 "register_operand"             "=r")
+	(unspec:SI [(match_operand:SI 1 "register_operand" " r")
+		    (const_int 31)] UNSPEC_BITREV))]
+  "TARGET_ZBPBO && !TARGET_64BIT"
+  "rev\t%0, %1"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "SI")])
+
+(define_insn "revdi_internal"
+  [(set (match_operand:DI 0 "register_operand"             "=r")
+	(unspec:DI [(match_operand:DI 1 "register_operand" " r")
+		    (const_int 63)] UNSPEC_BITREV))]
+  "TARGET_ZBPBO && TARGET_64BIT"
+  "rev\t%0, %1"
+  [(set_attr "type"   "dsp")
+   (set_attr "mode"   "DI")])
+
+;; fsr, fsri, fsrw
+(define_insn "fsrw"
+  [(set (match_operand:SI 0 "register_operand"     "=r")
+	(unspec: SI [(match_operand:SI 1 "register_operand" "r")
+		(match_operand:SI 2 "register_operand" "r")
+		(match_operand:SI 3 "register_operand" "r")] UNSPEC_FSRW))]
+  "TARGET_ZBPBO && TARGET_64BIT"
+  "fsrw\t%0,%1,%2,%3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_expand "fsr"
+  [(match_operand:SI 0 "register_operand" "  =r, r")
+   (match_operand:SI 1 "register_operand" "r, r")
+   (match_operand:SI 2 "arith_operand" "r, I")
+   (match_operand:SI 3 "register_operand" "r, r")]
+   "TARGET_ZBPBO && !TARGET_64BIT"
+  {
+    unsigned HOST_WIDE_INT shamt;
+    if (CONST_INT_P (operands[2]))
+      {
+        shamt = INTVAL (operands[2]) & 63;
+        if (shamt == 32)
+		  {
+            emit_move_insn (operands[0], operands[1]);
+            DONE;
+          }
+        shamt = shamt > 32 ? shamt - 32 : shamt;
+        operands[2] = GEN_INT(shamt);
+        emit_insn (gen_fsri_rvp (operands[0], operands[1],
+                       operands[2], operands[3]));
+      }
+	else
+	  {
+		emit_insn (gen_fsr_rvp (operands[0], operands[1], operands[2], operands[3]));
+	  }
+	DONE;
+  })
+
+(define_insn "fsr_rvp"
+  [(set (match_operand:SI 0 "register_operand"     "=r")
+	(unspec: SI [(match_operand:SI 1 "register_operand" "")
+		(match_operand:SI 2 "register_operand" "")
+		(match_operand:SI 3 "register_operand" "")] UNSPEC_FSR))]
+  "TARGET_ZBPBO && !TARGET_64BIT"
+  "fsr\t%0,%1,%2,%3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+(define_insn "fsri_rvp"
+  [(set (match_operand:SI 0 "register_operand"     "=r")
+	(truncate: SI
+	  (ior:DI
+	    (ashiftrt:DI
+	      (match_operand:SI 1 "register_operand" " r")
+	      (match_operand:SI 2 "fsr_shamt_imm"   " u05"))
+	    (lshiftrt:DI
+	      (match_operand:SI 3 "register_operand" " r")
+	      (minus:SI (const_int 32) (match_dup 2))))))]
+  "TARGET_ZBPBO && !TARGET_64BIT"
+  "fsri\t%0,%1,%2,%3"
+  [(set_attr "type" "dsp")
+   (set_attr "mode" "SI")])
+
+;; move pattern
+(define_expand "mov<mode>"
+  [(set (match_operand:VPMOVE 0 "")
+	(match_operand:VPMOVE 1 ""))]
+  "TARGET_ZPN"
+{
+  if (riscv_legitimize_move (<MODE>mode, operands[0], operands[1]))
+    DONE;
+})
+
+(define_insn "*mov<mode>_internal"
+  [(set (match_operand:VPMOVE 0 "nonimmediate_operand" "=r,r,r, m,  *f,*f,*r,*m")
+	(match_operand:VPMOVE 1 "move_operand"         " r,T,m,rJ,*r*J,*m,*f,*f"))]
+  "(register_operand (operands[0], <MODE>mode)
+    || reg_or_0_operand (operands[1], <MODE>mode))
+   && TARGET_ZPN"
+  { return riscv_output_move (operands[0], operands[1]); }
+  [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore")
+   (set_attr "mode" "<MODE>")])
+
+(define_expand "movv2si"
+  [(set (match_operand:V2SI 0 "")
+	(match_operand:V2SI 1 ""))]
+  "TARGET_64BIT && TARGET_ZPN "
+{
+  if (riscv_legitimize_move (V2SImode, operands[0], operands[1]))
+    DONE;
+})
+
+(define_insn "*movv2si_64bit"
+  [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,r, m,  *f,*f,*r,*f,*m")
+	(match_operand:V2SI 1 "move_operand"         " r,T,m,rJ,*r*J,*m,*f,*f,*f"))]
+  "TARGET_64BIT && TARGET_ZPN
+   && (register_operand (operands[0], V2SImode)
+       || reg_or_0_operand (operands[1], V2SImode))"
+  { return riscv_output_move (operands[0], operands[1]); }
+  [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore")
+   (set_attr "mode" "V2SI")])
diff --git a/gcc/config/riscv/rvp_intrinsic.h b/gcc/config/riscv/rvp_intrinsic.h
new file mode 100644
index 000000000000..09369f60abab
--- /dev/null
+++ b/gcc/config/riscv/rvp_intrinsic.h
@@ -0,0 +1,747 @@
+/* Builtin definitions for P extension
+   Copyright (C) 2021 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#ifndef _RISCV_RVP_INTRINSIC_H
+#define _RISCV_RVP_INTRINSIC_H
+
+#if !defined (__riscv_zpn)
+#error "Packed SIMD intrinsics require the rvp extension."
+#endif
+
+#include <stdint.h>
+
+typedef signed char int8x4_t __attribute ((vector_size(4)));
+typedef signed char int8x8_t __attribute ((vector_size(8)));
+typedef short int16x2_t __attribute ((vector_size(4)));
+typedef short int16x4_t __attribute__((vector_size (8)));
+typedef int int32x2_t __attribute__((vector_size(8)));
+typedef unsigned char uint8x4_t __attribute__ ((vector_size (4)));
+typedef unsigned char uint8x8_t __attribute__ ((vector_size (8)));
+typedef unsigned short uint16x2_t __attribute__ ((vector_size (4)));
+typedef unsigned short uint16x4_t __attribute__((vector_size (8)));
+typedef unsigned int uint32x2_t __attribute__((vector_size(8)));
+
+#if __riscv_xlen == 32
+typedef int32_t intXLEN_t;
+typedef uint32_t uintXLEN_t;
+typedef int32_t int32xN_t;
+typedef uint32_t uint32xN_t;
+typedef uint16x2_t uint16xN_t;
+typedef int16x2_t int16xN_t;
+typedef uint8x4_t uint8xN_t;
+typedef int8x4_t int8xN_t;
+#else
+typedef int64_t intXLEN_t;
+typedef uint64_t uintXLEN_t;
+typedef int32x2_t int32xN_t;
+typedef uint32x2_t uint32xN_t;
+typedef uint16x4_t uint16xN_t;
+typedef int16x4_t int16xN_t;
+typedef uint8x8_t uint8xN_t;
+typedef int8x8_t int8xN_t;
+#endif
+
+#define RVP_INTRINSIC_PREFIX __rv_
+#define RVP_INTRINSIC_VECTOR_PREFIX __rv_v_
+
+#define RVP_ARGUMENT_LIST(_0, _1, _2, _3, _4, _5, ...) _5
+#define RVP_N_ARG(...) RVP_ARGUMENT_LIST(_, ## __VA_ARGS__, 4, 3, 2, 1, 0)
+
+#define RVP_VAR0(...) 
+#define RVP_VAR1(type1) a
+#define RVP_VAR2(type1, type2) RVP_VAR1(type1), b
+#define RVP_VAR3(type1, type2, type3) RVP_VAR2(type1, type2), c
+#define RVP_VAR4(type1, type2, type3, type4) RVP_VAR3(type1, type2, type3), d
+
+#define RVP_ARG0(...) 
+#define RVP_ARG1(type1) type1 a
+#define RVP_ARG2(type1, type2) RVP_ARG1(type1), type2 b
+#define RVP_ARG3(type1, type2, type3) RVP_ARG2(type1, type2), type3 c
+#define RVP_ARG4(type1, type2, type3, type4) RVP_ARG3(type1, type2, type3), type4 d
+
+#define RVP_CONCAT_IMPL(x,y)  x ## y
+#define RVP_CONCAT(x, y) RVP_CONCAT_IMPL(x, y)
+#define RVP_EXPAND_ARGS(...) RVP_CONCAT(RVP_ARG, RVP_N_ARG(__VA_ARGS__)) (__VA_ARGS__)
+#define RVP_EXPAND_VARS(...) RVP_CONCAT(RVP_VAR, RVP_N_ARG(__VA_ARGS__)) (__VA_ARGS__)
+
+#if __riscv_xlen == 32
+#define RVP_VECTOR_BUILTIN_PREFIX __builtin_riscv_v_
+#else
+#define RVP_VECTOR_BUILTIN_PREFIX __builtin_riscv_v64_
+#endif
+
+#define CREATE_RVP_INTRINSIC(return_type, name, ...)\
+  DIRECT_CREATE_RVP_INTRINSIC (return_type, name, name, __rv_,\
+      __builtin_riscv_, RVP_EXPAND_ARGS, RVP_EXPAND_VARS, __VA_ARGS__)
+
+#define CREATE_RVP_INTRINSIC_ALIAS(return_type, name, internal_name, ...)\
+  DIRECT_CREATE_RVP_INTRINSIC (return_type, name, internal_name, __rv_,\
+      __builtin_riscv_, RVP_EXPAND_ARGS, RVP_EXPAND_VARS, __VA_ARGS__)
+
+/* RVP_N_ARG() expands to 0 in c89 */
+#define CREATE_RVP_INTRINSIC_EMPTY_ARGS(return_type, name, ...)\
+  DIRECT_CREATE_RVP_INTRINSIC (return_type, name, name, \
+    RVP_INTRINSIC_PREFIX, __builtin_riscv_, RVP_ARG0, RVP_VAR0, __VA_ARGS__)
+
+#define CREATE_RVP_INTRINSIC_VECTOR(return_type, name, ...)\
+  DIRECT_CREATE_RVP_INTRINSIC (return_type, name, name, \
+    RVP_INTRINSIC_VECTOR_PREFIX, RVP_VECTOR_BUILTIN_PREFIX, \
+    RVP_EXPAND_ARGS, RVP_EXPAND_VARS, __VA_ARGS__)
+
+#define DIRECT_CREATE_RVP_INTRINSIC(return_type, name, internal_name, intrisic_prefix,\
+      builtin_prefix, arg_expand_macro, var_expand_macro, ...)\
+  __extension__ extern __inline __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) \
+  return_type RVP_CONCAT(intrisic_prefix, name(arg_expand_macro(__VA_ARGS__))) { \
+    return RVP_CONCAT(builtin_prefix, internal_name) (var_expand_macro(__VA_ARGS__)); \
+  }
+
+/* ZPN */
+CREATE_RVP_INTRINSIC (uintXLEN_t, add8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, add16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, ave, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, bitrev, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_EMPTY_ARGS (void, clrov)
+CREATE_RVP_INTRINSIC (uintXLEN_t, clrs8, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, clrs16, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, clrs32, intXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, clz8, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, clz16, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, clz32, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, cmpeq8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, cmpeq16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, cras16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, crsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, insb, uintXLEN_t, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kabs8, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kabs16, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, kabsw, int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kadd8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kadd16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, kaddh, int16_t, int16_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kcras16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kcrsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, kdmbb, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, kdmbt, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, kdmtt, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, v_kdmbb, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int32_t, v_kdmbt, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int32_t, v_kdmtt, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int32_t, kdmabb, int32_t, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, kdmabt, int32_t, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, kdmatt, int32_t, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, khm8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, khmx8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, khm16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, khmx16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, khmbb, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, khmbt, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, khmtt, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, v_khmbb, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int32_t, v_khmbt, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int32_t, v_khmtt, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmabb, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmabt, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmatt, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmada, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmaxda, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmads, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmadrs, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmaxds, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmda, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmxda, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmac, intXLEN_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmac_u, intXLEN_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawb, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawb_u, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawb2, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawb2_u, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawt, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawt_u, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawt2, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmawt2_u, intXLEN_t, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmsb, intXLEN_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmsb_u, intXLEN_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmwb2, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmwb2_u, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmwt2, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmmwt2_u, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmsda, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kmsxda, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, ksllw, int32_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ksll8, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ksll16, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kslra8, uintXLEN_t, const int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kslra8_u, uintXLEN_t, const int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kslra16, uintXLEN_t, const int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kslra16_u, uintXLEN_t, const int32_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kslraw, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kslraw_u, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kstas16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, kstsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ksub8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ksub16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, ksubh, int16_t, int16_t)
+CREATE_RVP_INTRINSIC (int32_t, ksubw, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kwmmul, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, kwmmul_u, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, maddr32, int32_t, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (int32_t, msubr32, int32_t, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, pbsad, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, pbsada, uintXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, pkbt16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, pkbb16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, pktb16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, pktt16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, radd8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, radd16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, raddw, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, rcras16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, rcrsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC_EMPTY_ARGS (uintXLEN_t, rdov)
+CREATE_RVP_INTRINSIC (uintXLEN_t, rstas16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, rstsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, rsub8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, rsub16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, rsubw, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sclip8, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sclip16, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, sclip32, intXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, scmple8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, scmple16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, scmplt8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, scmplt16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sll8, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sll16, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smaqa, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smaqa_su, intXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, smax8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, smax16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smbb16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smbt16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smtt16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smds, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smdrs, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smxds, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, smin8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, smin16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smmul, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smmul_u, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smmwb, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smmwb_u, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smmwt, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, smmwt_u, intXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, sra_u, intXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sra8, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sra8_u, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sra16, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sra16_u, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, srl8, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, srl8_u, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, srl16, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, srl16_u, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, stas16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, stsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sub8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sub16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sunpkd810, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sunpkd820, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sunpkd830, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sunpkd831, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, sunpkd832, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, swap8, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, uclip8, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, uclip16, uintXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, uclip32, intXLEN_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ucmplt8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ucmple8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ucmplt16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ucmple16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ukadd8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ukadd16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint32_t, ukaddh, uint16_t, uint16_t)
+CREATE_RVP_INTRINSIC (uint32_t, ukaddw, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int32_t, kaddw, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ukcras16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ukcrsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ukstas16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ukstsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, uksub8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, uksub16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint32_t, uksubh, uint16_t, uint16_t)
+CREATE_RVP_INTRINSIC (uint32_t, uksubw, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, umaqa, uintXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, umax8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, umax16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, umin8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, umin16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, uradd8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, uradd16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint32_t, uraddw, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, urcras16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, urcrsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, urstas16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, urstsa16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ursub8, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, ursub16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint32_t, ursubw, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, zunpkd810, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, zunpkd820, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, zunpkd830, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, zunpkd831, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, zunpkd832, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int32_t, v_kdmabb, int32_t, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int32_t, v_kdmabt, int32_t, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int32_t, v_kdmatt, int32_t, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, uadd8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, sadd8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, uadd16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sadd16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, clrs8, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, clrs16, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, clz8, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, clz16, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, scmpeq8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, ucmpeq8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, scmpeq16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ucmpeq16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ucras16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, scras16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ucrsa16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, scrsa16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, kabs8, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kabs16, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, kadd8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kadd16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kcras16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kcrsa16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, khm8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, khmx8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, khm16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, khmx16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmabb, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmabt, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmatt, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmada, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmaxda, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmads, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmadrs, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmaxds, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmda, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmxda, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawb, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawb_u, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawb2, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawb2_u, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawt, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawt_u, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawt2, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmawt2_u, int32xN_t, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmwb2, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmwb2_u, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmwt2, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmmwt2_u, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmsda, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, kmsxda, int32xN_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, ksll8, int8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, ksll16, int16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, kslra8, int8xN_t, int32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, kslra8_u, int8xN_t, int32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kslra16, int16xN_t, int32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kslra16_u, int16xN_t, int32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kstas16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, kstsa16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, ksub8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, ksub16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uintXLEN_t, pbsad, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uintXLEN_t, pbsada, uintXLEN_t, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, pkbt16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, pkbb16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, pktb16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, pktt16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, radd8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, radd16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, rcras16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, rcrsa16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, rstas16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, rstsa16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, rsub8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, rsub16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, sclip8, int8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sclip16, int16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, scmple8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, scmple16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, scmplt8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, scmplt16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, sll8, uint8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, sll16, uint16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smaqa, int32xN_t, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smaqa_su, int32xN_t, int8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, smax8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, smax16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smbb16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smbt16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smtt16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smds, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smdrs, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smxds, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, smin8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, smin16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smmwb, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smmwb_u, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smmwt, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32xN_t, smmwt_u, int32xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, sra8, int8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, sra8_u, int8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sra16, int16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sra16_u, int16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, srl8, uint8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, srl8_u, uint8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, srl16, uint16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, srl16_u, uint16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ustas16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sstas16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ustsa16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sstsa16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, usub8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int8xN_t, ssub8, int8xN_t, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, usub16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, ssub16, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sunpkd810, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sunpkd820, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sunpkd830, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sunpkd831, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int16xN_t, sunpkd832, int8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, swap8, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, uclip8, int8xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, uclip16, int16xN_t, const uint32_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, ucmplt8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, ucmple8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ucmplt16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ucmple16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, ukadd8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ukadd16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ukcras16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ukcrsa16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ukstas16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ukstsa16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, uksub8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, uksub16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint32xN_t, umaqa, uint32xN_t, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, umax8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, umax16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, umin8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, umin16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, uradd8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, uradd16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, urcras16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, urcrsa16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, urstas16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, urstsa16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint8xN_t, ursub8, uint8xN_t, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, ursub16, uint16xN_t, uint16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, zunpkd810, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, zunpkd820, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, zunpkd830, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, zunpkd831, uint8xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (uint16xN_t, zunpkd832, uint8xN_t)
+/* alias */
+__extension__ extern __inline __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+uintXLEN_t __rv_swap16 (uintXLEN_t a) {
+  return __builtin_riscv_pkbt16 (a, a);
+}
+__extension__ extern __inline __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+uint16xN_t __rv_v_swap16 (uint16xN_t a) {
+  return RVP_CONCAT(RVP_VECTOR_BUILTIN_PREFIX, pkbt16) (a, a);
+}
+
+/* ZPN64 ONLY */
+#if __riscv_xlen == 64
+CREATE_RVP_INTRINSIC (int32_t, sraw_u, int32_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kabs32, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kadd32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kcras32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kcrsa32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kdmabb16, int32x2_t, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kdmabt16, int32x2_t, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kdmatt16, int32x2_t, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kdmbb16, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kdmbt16, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kdmtt16, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_khmbb16, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_khmbt16, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_khmtt16, int16x4_t, int16x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kmmac, int32x2_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kmmac_u, int32x2_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kmmsb, int32x2_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kmmsb_u, int32x2_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_ksll32, int32x2_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kslra32, int32x2_t, int32_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kslra32_u, int32x2_t, int32_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kstas32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kstsa32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_ksub32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kwmmul, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_kwmmul_u, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_radd32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_rcras32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_rcrsa32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_rstas32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_rstsa32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_rsub32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_sadd32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_sclip32, int32x2_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_scras32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_scrsa32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_smax32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_smin32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_smmul, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_smmul_u, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_sra32, int32x2_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_sra32_u, int32x2_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_sstas32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_sstsa32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_ssub32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, khmbb16, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, khmbt16, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, khmtt16, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmabb32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmabt32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmatt32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmadrs32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmads32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmaxda32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmaxds32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmda32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmsda32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmsxda32, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmxda32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smbb32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smbt32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smtt32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smdrs32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smds32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smxds32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmabb32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmabt32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmadrs32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmads32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmatt32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmaxda32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmaxds32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmda32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmsda32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmsxda32, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmxda32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smbb32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smbt32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smdrs32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smds32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smtt32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smxds32, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_clrs32, int32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_clz32, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_pkbb32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_pkbt32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_pktb32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_pktt32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_sll32, uint32x2_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_srl32, uint32x2_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_srl32_u, uint32x2_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_uadd32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_uclip32, int32x2_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ucras32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ucrsa32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ukadd32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ukcras32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ukcrsa32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ukstas32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ukstsa32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_uksub32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_umax32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_umin32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_uradd32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_urcras32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_urcrsa32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_urstas32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_urstsa32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ursub32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ustas32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_ustsa32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_usub32, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint64_t, add32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, cras32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, crsa32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, kabs32, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kadd32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kcras32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kcrsa32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kdmabb16, int64_t, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, kdmabt16, int64_t, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, kdmatt16, int64_t, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, kdmbb16, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, kdmbt16, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, kdmtt16, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, ksll32, int64_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int64_t, kslra32, int64_t, int32_t)
+CREATE_RVP_INTRINSIC (int64_t, kslra32_u, int64_t, int32_t)
+CREATE_RVP_INTRINSIC (int64_t, kstas32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kstsa32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, ksub32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (uint64_t, pkbb32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, pkbt32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, pktb32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, pktt32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, radd32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, rcras32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, rcrsa32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, rstas32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, rstsa32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, rsub32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, sll32, int64_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int64_t, smax32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smin32, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, sra32, int64_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int64_t, sra32_u, int64_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int64_t, srl32, int64_t, const uint32_t)
+CREATE_RVP_INTRINSIC (int64_t, srl32_u, int64_t, const uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, stas32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, stsa32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, sub32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukadd32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukcras32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukcrsa32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukstas32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukstsa32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, uksub32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, umax32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, umin32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, uradd32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, urcras32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, urcrsa32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, urstas32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, urstsa32, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ursub32, uint64_t, uint64_t)
+#endif
+
+#if defined(__riscv_zpsf)
+
+#if !defined(__riscv_zbpbo)
+/* wext/wexti are forbidden with using zbpbo subextension */
+CREATE_RVP_INTRINSIC (intXLEN_t, wext, uint64_t, const uint32_t)
+#endif
+
+CREATE_RVP_INTRINSIC (int16x4_t, v_smul8, int8x4_t, int8x4_t)
+CREATE_RVP_INTRINSIC (int16x4_t, v_smulx8, int8x4_t, int8x4_t)
+CREATE_RVP_INTRINSIC (int32x2_t, v_smulx16, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC (int64_t, kadd64, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, kmar64, int64_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, kmsr64, int64_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, ksub64, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, mulsr64, int32_t, int32_t)
+CREATE_RVP_INTRINSIC (int64_t, radd64, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, rsub64, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (int64_t, smal, int64_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smalbb, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smalbt, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smalda, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smaldrs, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smalds, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smaltt, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smalxda, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smalxds, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smar64, int64_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smslda, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smslxda, int64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (int64_t, smsr64, int64_t, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (uint16x4_t, v_umul8, uint8x4_t, uint8x4_t)
+CREATE_RVP_INTRINSIC (uint16x4_t, v_umulx8, uint8x4_t, uint8x4_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_umul16, uint16x2_t, uint16x2_t)
+CREATE_RVP_INTRINSIC (uint32x2_t, v_umulx16, uint16x2_t, uint16x2_t)
+CREATE_RVP_INTRINSIC (uint64_t, mulr64, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int64_t, smul16, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, smul8, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (int64_t, smulx16, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, smulx8, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukadd64, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukmar64, uint64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint64_t, ukmsr64, uint64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint64_t, uksub64, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, umar64, uint64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint64_t, umsr64, uint64_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC (uint64_t, umul16, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, umul8, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, umulx16, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, umulx8, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC (uint64_t, uradd64, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, ursub64, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC_VECTOR (int32x2_t, smul16, int16x2_t, int16x2_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smal, int64_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smalbb, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smalbt, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smalda, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smaldrs, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smalds, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smaltt, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smalxda, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smalxds, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smslda, int64_t, int16xN_t, int16xN_t)
+CREATE_RVP_INTRINSIC_VECTOR (int64_t, smslxda, int64_t, int16xN_t, int16xN_t)
+#if __riscv_xlen == 32
+CREATE_RVP_INTRINSIC (int64_t, sadd64, int64_t, int64_t)
+CREATE_RVP_INTRINSIC (uint64_t, uadd64, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (uint64_t, usub64, uint64_t, uint64_t)
+CREATE_RVP_INTRINSIC (int64_t, ssub64, int64_t, int64_t)
+#else
+CREATE_RVP_INTRINSIC (int64_t, v_kmar64, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_kmsr64, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smar64, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (int64_t, v_smsr64, int64_t, int32x2_t, int32x2_t)
+CREATE_RVP_INTRINSIC (uint64_t, v_ukmar64, uint64_t, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint64_t, v_ukmsr64, uint64_t, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint64_t, v_umar64, uint64_t, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC (uint64_t, v_umsr64, uint64_t, uint32x2_t, uint32x2_t)
+CREATE_RVP_INTRINSIC_ALIAS (int64_t, kmada32, kmar64, int64_t, int64_t, int64_t)
+CREATE_RVP_INTRINSIC_ALIAS (int64_t, v_kmada32, v_kmar64, int64_t, int32x2_t, int32x2_t)
+#endif
+#endif // END OF ZPSF
+
+#if defined(__riscv_zbpbo)
+CREATE_RVP_INTRINSIC (uintXLEN_t, rev, uintXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, max, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (intXLEN_t, min, intXLEN_t, intXLEN_t)
+CREATE_RVP_INTRINSIC (uintXLEN_t, cmix, uintXLEN_t, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC_ALIAS (uintXLEN_t, rev8h, swap8, uintXLEN_t)
+__extension__ extern __inline __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+uint8xN_t __rv_v_rev8h (uint8xN_t a) {
+  return RVP_CONCAT (RVP_VECTOR_BUILTIN_PREFIX, swap8) (a);
+}
+
+#if __riscv_xlen == 32
+CREATE_RVP_INTRINSIC (uint32_t, fsr, uint32_t, const uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC_ALIAS (uint32_t, clz, clz32, uint32_t)
+CREATE_RVP_INTRINSIC_ALIAS (uintXLEN_t, pack, pktt16, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC_ALIAS (uintXLEN_t, packu, pkbb16, uintXLEN_t, uintXLEN_t)
+#else
+CREATE_RVP_INTRINSIC (uint32_t, fsrw, uint32_t, uint32_t, uint32_t)
+CREATE_RVP_INTRINSIC_ALIAS (uintXLEN_t, pack, pktt32, uintXLEN_t, uintXLEN_t)
+CREATE_RVP_INTRINSIC_ALIAS (uintXLEN_t, packu, pkbb32, uintXLEN_t, uintXLEN_t)
+#endif
+
+#endif // END OF __riscv_zbpbo
+#endif // END OF _RISCV_RVP_INTRINSIC_H
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add16.c
new file mode 100644
index 000000000000..8f716ef323f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add16.c
@@ -0,0 +1,27 @@
+/* add16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dda (uint32_t ra, uint32_t rb)
+{
+  return __rv_add16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ddau_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_uadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t ddas_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_sadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add64.c
new file mode 100644
index 000000000000..9fe7e174ea0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add64.c
@@ -0,0 +1,21 @@
+/* add64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t ddas (int64_t ra, int64_t rb)
+{
+  return __rv_sadd64 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint64_t ddau (uint64_t ra, uint64_t rb)
+{
+  return __rv_uadd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add8.c
new file mode 100644
index 000000000000..0c885b007edf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add8.c
@@ -0,0 +1,27 @@
+/* add8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dda (uint32_t ra, uint32_t rb)
+{
+  return __rv_add8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t ddau_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_uadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t ddas_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_sadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ave.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ave.c
new file mode 100644
index 000000000000..7a44534b602b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ave.c
@@ -0,0 +1,16 @@
+/* ave also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ave instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t eva (int32_t ra, int32_t rb)
+{
+  return __rv_ave (ra, rb);
+}
+
+/* { dg-final { scan-assembler-times "ave" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-bitrev.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-bitrev.c
new file mode 100644
index 000000000000..a49b1815af7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-bitrev.c
@@ -0,0 +1,15 @@
+/* bitrev also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for bitrev instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t vertib (uint32_t ra, uint32_t rb)
+{
+  return __rv_bitrev (ra, rb);
+}
+/* { dg-final { scan-assembler-times "bitrev" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq16.c
new file mode 100644
index 000000000000..5a9ca134a3f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq16.c
@@ -0,0 +1,27 @@
+/* cmpeq16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t qepmc (uint32_t ra, uint32_t rb)
+{
+  return __rv_cmpeq16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t qepmcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scmpeq16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t qepmcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucmpeq16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq8.c
new file mode 100644
index 000000000000..fb94d91386f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq8.c
@@ -0,0 +1,27 @@
+/* cmpeq8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t qepmc (uint32_t ra, uint32_t rb)
+{
+  return __rv_cmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t qepmcs_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_scmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t qepmcu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ucmpeq8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-count.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-count.c
new file mode 100644
index 000000000000..bb31693df292
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-count.c
@@ -0,0 +1,64 @@
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a) {
+  return __rv_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo1(uintXLEN_t a) {
+  return __rv_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a) {
+  return __rv_clrs32 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a) {
+  return __rv_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo4(uintXLEN_t a) {
+  return __rv_clz16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo5(uintXLEN_t a) {
+  return __rv_clz32 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo6(int8xN_t a) {
+  return __rv_v_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(int16xN_t a) {
+  return __rv_v_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo9(uint8xN_t a) {
+  return __rv_v_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo10(uint16xN_t a) {
+  return __rv_v_clz16 (a);
+}
+
+/* { dg-final { scan-assembler-times "clrs8" 2 } } */
+/* { dg-final { scan-assembler-times "clrs16" 2 } } */
+/* { dg-final { scan-assembler-times "clrs32" 1 } } */
+/* { dg-final { scan-assembler-times "clz8" 2 } } */
+/* { dg-final { scan-assembler-times "clz16" 2 } } */
+/* { dg-final { scan-assembler-times "clz32" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cras16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cras16.c
new file mode 100644
index 000000000000..96fa46f46fa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cras16.c
@@ -0,0 +1,27 @@
+/* cras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t sarc (uint32_t ra, uint32_t rb)
+{
+  return __rv_cras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t sarcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t sarcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cras16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-crsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-crsa16.c
new file mode 100644
index 000000000000..6c61da3423bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-crsa16.c
@@ -0,0 +1,27 @@
+/* crsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t asrc (uint32_t ra, uint32_t rb)
+{
+  return __rv_crsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t asrcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t asrcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "crsa16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-insb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-insb.c
new file mode 100644
index 000000000000..a320dd8ba142
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-insb.c
@@ -0,0 +1,15 @@
+/* insb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for insb instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bsni (uint32_t ra, uint32_t rb)
+{
+  return __rv_insb (ra, rb, 1);
+}
+/* { dg-final { scan-assembler-times "insb" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-kmar64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-kmar64.c
new file mode 100644
index 000000000000..5c13f44fa089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-kmar64.c
@@ -0,0 +1,17 @@
+/* kmar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmar64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t ramk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmar64 (rd, ra, rb);
+}
+
+/* { dg-final { scan-assembler-times "kmar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mfb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mfb.c
new file mode 100644
index 000000000000..d789d76e422d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mfb.c
@@ -0,0 +1,41 @@
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+intXLEN_t foo(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+intXLEN_t foo1(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_umaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo3(int32xN_t t, int8xN_t a, int8xN_t b) {
+  return __rv_v_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo4(int32xN_t t, int8xN_t a, uint8xN_t b) {
+  return __rv_v_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo5(uint32xN_t t, uint8xN_t a, uint8xN_t b) {
+  return __rv_v_umaqa (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaqa.su" 2 } } */
+/* { dg-final { scan-assembler-times "smaqa" 4 } } */
+/* { dg-final { scan-assembler-times "umaqa" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mul32.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mul32.c
new file mode 100644
index 000000000000..b7236a4742e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mul32.c
@@ -0,0 +1,22 @@
+/* This is a test program for maddr32, msubr32 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t madd (int32_t ra, int32_t rb, int32_t rc)
+{
+  return __rv_maddr32 (ra, rb, rc);
+}
+
+static __attribute__ ((noinline))
+int32_t msub (int32_t ra, int32_t rb, int32_t rc)
+{
+  return __rv_msubr32 (ra, rb, rc);
+}
+
+/* { dg-final { scan-assembler-times "msubr32" 1 } } */
+/* { dg-final { scan-assembler-times "maddr32" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsad.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsad.c
new file mode 100644
index 000000000000..3bd85099a7ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsad.c
@@ -0,0 +1,15 @@
+/* pbsad also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pbsad instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dasbp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pbsad (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pbsad" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsada.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsada.c
new file mode 100644
index 000000000000..bee02a4a7453
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsada.c
@@ -0,0 +1,15 @@
+/* pbsada also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pbsada instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t adasbp (uint32_t ra, uint32_t rb, uint32_t rc)
+{
+  return __rv_pbsada (ra, rb, rc);
+}
+/* { dg-final { scan-assembler-times "pbsada" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbb16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbb16.c
new file mode 100644
index 000000000000..e9bfc6eab57e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbb16.c
@@ -0,0 +1,21 @@
+/* pkbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbb16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bbkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pkbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t bbkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pkbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbt16.c
new file mode 100644
index 000000000000..3c894641a4a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbt16.c
@@ -0,0 +1,21 @@
+/* pkbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tbkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pkbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t tbkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pkbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktb16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktb16.c
new file mode 100644
index 000000000000..67f9e8d1c724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktb16.c
@@ -0,0 +1,21 @@
+/* pktb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktb16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t btkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pktb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t btkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pktb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktt16.c
new file mode 100644
index 000000000000..bcfacf164ac4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktt16.c
@@ -0,0 +1,21 @@
+/* pktt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ttkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pktt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ttkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pktt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd16.c
new file mode 100644
index 000000000000..f1291380f4ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd16.c
@@ -0,0 +1,21 @@
+/* radd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddar (uint32_t ra, uint32_t rb)
+{
+  return __rv_radd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t ddar_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_radd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd64.c
new file mode 100644
index 000000000000..7cc82573eb71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd64.c
@@ -0,0 +1,15 @@
+/* radd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t ddar (int64_t ra, int64_t rb)
+{
+  return __rv_radd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd8.c
new file mode 100644
index 000000000000..b0702a8b9d03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd8.c
@@ -0,0 +1,21 @@
+/* radd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddar (uint32_t ra, uint32_t rb)
+{
+  return __rv_radd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t ddar_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_radd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-raddw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-raddw.c
new file mode 100644
index 000000000000..339f9f1d1bae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-raddw.c
@@ -0,0 +1,15 @@
+/* raddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for raddw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t wddar (int32_t ra, int32_t rb)
+{
+  return __rv_raddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "raddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcras16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcras16.c
new file mode 100644
index 000000000000..12890d10d2c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcras16.c
@@ -0,0 +1,21 @@
+/* rcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcras16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t sarcr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t sarcr_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_rcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcrsa16.c
new file mode 100644
index 000000000000..6f0e8b601609
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcrsa16.c
@@ -0,0 +1,21 @@
+/* rcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcrsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t asrcr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t asrcr_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_rcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub16.c
new file mode 100644
index 000000000000..5dfeb1c26fb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub16.c
@@ -0,0 +1,21 @@
+/* rsub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rsub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t busr_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_rsub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub64.c
new file mode 100644
index 000000000000..91a0b62f7a13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub64.c
@@ -0,0 +1,15 @@
+/* rsub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t busr (int64_t ra, int64_t rb)
+{
+  return __rv_rsub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub8.c
new file mode 100644
index 000000000000..6bdb2f9845dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub8.c
@@ -0,0 +1,21 @@
+/* rsub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rsub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t busr_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_rsub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsubw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsubw.c
new file mode 100644
index 000000000000..aef6d0c2b7f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsubw.c
@@ -0,0 +1,15 @@
+/* rsubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsubw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t wbusr (int32_t ra, int32_t rb)
+{
+  return __rv_rsubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sclip8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sclip8.c
new file mode 100644
index 000000000000..62a1399257a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sclip8.c
@@ -0,0 +1,21 @@
+/* sclip8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t pilcs (int32_t ra)
+{
+  return __rv_sclip8 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+int8x4_t pilcs_v (int8x4_t ra)
+{
+  return __rv_v_sclip8 (ra, 3);
+}
+/* { dg-final { scan-assembler-times "sclip8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple16.c
new file mode 100644
index 000000000000..e9938af48c08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple16.c
@@ -0,0 +1,21 @@
+/* scmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t elpmcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple8.c
new file mode 100644
index 000000000000..9348df366007
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple8.c
@@ -0,0 +1,21 @@
+/* scmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t elpmcs_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_scmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt16.c
new file mode 100644
index 000000000000..7a307cbe4735
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt16.c
@@ -0,0 +1,21 @@
+/* scmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t tlpmcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt8.c
new file mode 100644
index 000000000000..4b3ba41f530f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt8.c
@@ -0,0 +1,21 @@
+/* scmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t tlpmcs_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_scmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll16.c
new file mode 100644
index 000000000000..1e2533d55daf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll16.c
@@ -0,0 +1,21 @@
+/* sll16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lls (uint32_t ra, uint32_t rb)
+{
+  return __rv_sll16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t lls_v (uint16x2_t ra, uint32_t rb)
+{
+  return __rv_v_sll16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll8.c
new file mode 100644
index 000000000000..091fe3432157
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll8.c
@@ -0,0 +1,21 @@
+/* sll8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lls (uint32_t ra, uint32_t rb)
+{
+  return __rv_sll8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t lls_v (uint8x4_t ra, uint32_t rb)
+{
+  return __rv_v_sll8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smal.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smal.c
new file mode 100644
index 000000000000..7320da3157a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smal.c
@@ -0,0 +1,21 @@
+/* smal also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smal instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t lams (int64_t ra, uint32_t rb)
+{
+  return __rv_smal (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t lams_v (int64_t ra, int16x2_t rb)
+{
+  return __rv_v_smal (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smal" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalda.c
new file mode 100644
index 000000000000..c88764a3d893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalda.c
@@ -0,0 +1,22 @@
+/* smalda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smaldrs.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smaldrs.c
new file mode 100644
index 000000000000..43b1c7b8013a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smaldrs.c
@@ -0,0 +1,22 @@
+/* smaldrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smaldrs instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t srdlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smaldrs (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t srdlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smaldrs (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaldrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalds.c
new file mode 100644
index 000000000000..c64a910a8b11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalds.c
@@ -0,0 +1,22 @@
+/* smalds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t sdlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxda.c
new file mode 100644
index 000000000000..089f94dd5178
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxda.c
@@ -0,0 +1,22 @@
+/* smalxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adxlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalxda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalxda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxds.c
new file mode 100644
index 000000000000..d8b99073c3cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxds.c
@@ -0,0 +1,22 @@
+/* smalxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t sdxlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalxds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalxds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smar64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smar64.c
new file mode 100644
index 000000000000..7e907ef721ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smar64.c
@@ -0,0 +1,19 @@
+/* smar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smar64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O2" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+int64_t rams (int64_t t, int32_t a, int32_t b)
+{
+  return __rv_smar64 (t, a, b);
+}
+
+int64_t test_autogen(int64_t t, int32_t a, int32_t b) {
+    return t + (int64_t)a * (int64_t)b;
+}
+
+/* { dg-final { scan-assembler-times "smar64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smax16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smax16.c
new file mode 100644
index 000000000000..cbaf0ce8a6ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smax16.c
@@ -0,0 +1,21 @@
+/* smax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t xams (uint32_t ra, uint32_t rb)
+{
+  return __rv_smax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t xams_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbb.c
new file mode 100644
index 000000000000..03ef38603d06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbb.c
@@ -0,0 +1,20 @@
+/* This is a test program for smbb instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t bbms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int bbms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbb16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbt.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbt.c
new file mode 100644
index 000000000000..bd958da9f13a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbt.c
@@ -0,0 +1,20 @@
+/* This is a test program for smbt instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t tbms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t tbms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smdrs.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smdrs.c
new file mode 100644
index 000000000000..eb2b02d331aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smdrs.c
@@ -0,0 +1,21 @@
+/* smdrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smdrs instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t srdms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smdrs (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t srdms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smdrs (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smdrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smds.c
new file mode 100644
index 000000000000..61b58e938f24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smds.c
@@ -0,0 +1,21 @@
+/* smds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t sdms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t sdms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smin16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smin16.c
new file mode 100644
index 000000000000..eaecf26d4f1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smin16.c
@@ -0,0 +1,21 @@
+/* smin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t nims (uint32_t ra, uint32_t rb)
+{
+  return __rv_smin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t nims_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmul.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmul.c
new file mode 100644
index 000000000000..8e8b62b2600e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmul.c
@@ -0,0 +1,14 @@
+/* This is a test program for smmul instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t lumms (int32_t ra, int32_t rb)
+{
+  return __rv_smmul (ra, rb);
+}
+/* { dg-final { scan-assembler-times "mulh" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmulu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmulu.c
new file mode 100644
index 000000000000..09771c6f61ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmulu.c
@@ -0,0 +1,14 @@
+/* This is a test program for smmul.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t u_lumms (int32_t ra, int32_t rb)
+{
+  return __rv_smmul_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmul.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwb.c
new file mode 100644
index 000000000000..28cde8686c53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwb.c
@@ -0,0 +1,21 @@
+/* smmwb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwb instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t bwmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t bwmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwbu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwbu.c
new file mode 100644
index 000000000000..1d36dbbf03b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwbu.c
@@ -0,0 +1,20 @@
+/* This is a test program for smmwb.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t u_bwmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwb_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t u_bwmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwb_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwt.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwt.c
new file mode 100644
index 000000000000..47d5d19ffb7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwt.c
@@ -0,0 +1,21 @@
+/* smmwt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwt instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t twmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t twmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwtu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwtu.c
new file mode 100644
index 000000000000..9ac2464cefc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwtu.c
@@ -0,0 +1,20 @@
+/* This is a test program for smmwt.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t u_twmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwt_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t u_twmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwt_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslda.c
new file mode 100644
index 000000000000..0d49c7cb08ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslda.c
@@ -0,0 +1,21 @@
+/* smslda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adlsms (int64_t rt, uint32_t ra, uint32_t rb)
+{
+  return __rv_smslda (rt, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adlsms_v (int64_t rt, int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smslda (rt, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smslda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslxda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslxda.c
new file mode 100644
index 000000000000..a5d3a457e69e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslxda.c
@@ -0,0 +1,21 @@
+/* smslxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslxda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adxlsms (int64_t rt, uint32_t ra, uint32_t rb)
+{
+  return __rv_smslxda (rt, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlsms_v (int64_t rt, int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smslxda (rt, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smslxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smsr64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smsr64.c
new file mode 100644
index 000000000000..66d0869a2800
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smsr64.c
@@ -0,0 +1,19 @@
+/* smsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smsr64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O2" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+int64_t rsms (int64_t t, int a, int b)
+{
+  return __rv_smsr64 (t, a, b);
+}
+
+int64_t test_autogen(int64_t t, int32_t a, int32_t b) {
+  return t - (int64_t)a * (int64_t)b;
+}
+
+/* { dg-final { scan-assembler-times "smsr64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smtt.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smtt.c
new file mode 100644
index 000000000000..a5ccf2727466
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smtt.c
@@ -0,0 +1,20 @@
+/* This is a test program for smtt instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t ttms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t ttms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smtt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul16.c
new file mode 100644
index 000000000000..f3166094c4ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul16.c
@@ -0,0 +1,21 @@
+/* smul16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smul16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smul16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t lums_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smul16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smul16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul8.c
new file mode 100644
index 000000000000..1e167edc844b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul8.c
@@ -0,0 +1,21 @@
+/* smul8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smul8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smul8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t lums_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_smul8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smul8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx16.c
new file mode 100644
index 000000000000..f27a4df56bf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx16.c
@@ -0,0 +1,21 @@
+/* smulx16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smulx16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smulx16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t xlums_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smulx16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smulx16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx8.c
new file mode 100644
index 000000000000..5fceea0541e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx8.c
@@ -0,0 +1,21 @@
+/* smulx8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smulx8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smulx8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t xlums_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_smulx8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smulx8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smxds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smxds.c
new file mode 100644
index 000000000000..ac787d929e11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smxds.c
@@ -0,0 +1,21 @@
+/* smxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smxds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t sdxms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smxds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t sdxms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smxds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16.c
new file mode 100644
index 000000000000..5b25b3ab3be6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16.c
@@ -0,0 +1,21 @@
+/* sra16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t ars_v (int16x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16u.c
new file mode 100644
index 000000000000..e3d871839860
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for sra16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u61ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t u61ars_v (int16x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8.c
new file mode 100644
index 000000000000..acf3bc380767
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8.c
@@ -0,0 +1,21 @@
+/* sra8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t ars_v (int8x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8u.c
new file mode 100644
index 000000000000..f32b8d6a7f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8u.c
@@ -0,0 +1,20 @@
+/* This is a test program for sra8.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u8ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra8_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t u8ars_v (int8x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra8_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra8.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16.c
new file mode 100644
index 000000000000..b4bbb2e4fb4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16.c
@@ -0,0 +1,20 @@
+/* This is a test program for srai16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t iars (uint32_t ra)
+{
+  return __rv_sra16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x2_t iars_v (int16x2_t ra)
+{
+  return __rv_v_sra16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16u.c
new file mode 100644
index 000000000000..8ff72c1e7bea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for srai16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u61iars (uint32_t ra)
+{
+  return __rv_sra16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x2_t u61iars_v (int16x2_t ra)
+{
+  return __rv_v_sra16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sraiu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sraiu.c
new file mode 100644
index 000000000000..712ce0448f4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sraiu.c
@@ -0,0 +1,14 @@
+/* This is a test program for srai.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int uiars (int ra)
+{
+  return __rv_sra_u (ra, 8);
+}
+/* { dg-final { scan-assembler-times "srai.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srau.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srau.c
new file mode 100644
index 000000000000..22c931105386
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srau.c
@@ -0,0 +1,14 @@
+/* This is a test program for sra.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int uars (int ra, uint32_t rb)
+{
+  return __rv_sra_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16.c
new file mode 100644
index 000000000000..9ed1ee3eeafa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16.c
@@ -0,0 +1,21 @@
+/* srl16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t lrs_v (uint16x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16u.c
new file mode 100644
index 000000000000..5275d229ae47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for srl16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u_61lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t u_61lrs_v (uint16x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8.c
new file mode 100644
index 000000000000..556f98d396a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8.c
@@ -0,0 +1,21 @@
+/* srl8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t lrs_v (uint8x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8u.c
new file mode 100644
index 000000000000..344db2c1a9d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8u.c
@@ -0,0 +1,20 @@
+/* This is a test program for srl8.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u_8lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl8_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t u_8lrs_v (uint8x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl8_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl8.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16.c
new file mode 100644
index 000000000000..23c0dfcae6cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16.c
@@ -0,0 +1,20 @@
+/* This is a test program for srli16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ilrs (uint32_t ra)
+{
+  return __rv_srl16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ilrs_v (uint16x2_t ra)
+{
+  return __rv_v_srl16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16u.c
new file mode 100644
index 000000000000..9b95bfd8d962
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for sril16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u_61ilrs (uint32_t ra)
+{
+  return __rv_srl16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t u_61ilrs_v (uint16x2_t ra)
+{
+  return __rv_v_srl16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stas16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stas16.c
new file mode 100644
index 000000000000..93a5b68b5087
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stas16.c
@@ -0,0 +1,70 @@
+/* stas16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stas16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo9(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo11(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstas16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stas16" 12 } } */
+/* { dg-final { scan-assembler-times "rstas16" 4 } } */
+/* { dg-final { scan-assembler-times "urstas16" 2 } } */
+/* { dg-final { scan-assembler-times "kstas16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstas16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stsa16.c
new file mode 100644
index 000000000000..8fc3a9073977
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stsa16.c
@@ -0,0 +1,70 @@
+/* stsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo9(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo11(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstsa16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stsa16" 12 } } */
+/* { dg-final { scan-assembler-times "rstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "urstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "kstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub16.c
new file mode 100644
index 000000000000..740650a1a585
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub16.c
@@ -0,0 +1,27 @@
+/* sub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bus (uint32_t ra, uint32_t rb)
+{
+  return __rv_sub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t busu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_usub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t buss_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_ssub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub64.c
new file mode 100644
index 000000000000..a99174b0f630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub64.c
@@ -0,0 +1,21 @@
+/* sub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t buss (int64_t ra, int64_t rb)
+{
+  return __rv_ssub64 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint64_t busu (uint64_t ra, uint64_t rb)
+{
+  return __rv_usub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub8.c
new file mode 100644
index 000000000000..5e40e86d0227
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub8.c
@@ -0,0 +1,27 @@
+/* sub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bus (uint32_t ra, uint32_t rb)
+{
+  return __rv_sub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t busu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_usub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t buss_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_ssub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd810.c
new file mode 100644
index 000000000000..d1475b13fab9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd810.c
@@ -0,0 +1,21 @@
+/* sunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd810 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd820.c
new file mode 100644
index 000000000000..481d5507fd6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd820.c
@@ -0,0 +1,21 @@
+/* sunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd820 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd830.c
new file mode 100644
index 000000000000..90f1b80ad899
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd830.c
@@ -0,0 +1,21 @@
+/* sunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd830 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd831.c
new file mode 100644
index 000000000000..cae3ece3e948
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd831.c
@@ -0,0 +1,21 @@
+/* sunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd831 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd832.c
new file mode 100644
index 000000000000..6a138fd6a1a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd832.c
@@ -0,0 +1,21 @@
+/* sunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd832 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-swap8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-swap8.c
new file mode 100644
index 000000000000..53760554de42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-swap8.c
@@ -0,0 +1,15 @@
+/* swap8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for wsbh instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t paws (uint32_t a)
+{
+  return __rv_swap8 (a);
+}
+/* { dg-final { scan-assembler-times "swap8" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uclip8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uclip8.c
new file mode 100644
index 000000000000..2afc1624fd0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uclip8.c
@@ -0,0 +1,21 @@
+/* uclip8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t pilcu (uint32_t ra)
+{
+  return __rv_uclip8 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t pilcu_v (int8x4_t ra)
+{
+  return __rv_v_uclip8 (ra, 3);
+}
+/* { dg-final { scan-assembler-times "uclip8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple16.c
new file mode 100644
index 000000000000..087ed5a78920
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple16.c
@@ -0,0 +1,21 @@
+/* ucmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t elpmcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple8.c
new file mode 100644
index 000000000000..2e36728f2e5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple8.c
@@ -0,0 +1,21 @@
+/* ucmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t elpmcu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ucmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt16.c
new file mode 100644
index 000000000000..baaa1fc3ed52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt16.c
@@ -0,0 +1,21 @@
+/* ucmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t tlpmcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt8.c
new file mode 100644
index 000000000000..bef1f1a80afd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt8.c
@@ -0,0 +1,21 @@
+/* ucmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t tlpmcu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ucmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umar64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umar64.c
new file mode 100644
index 000000000000..1a8c09cdf4cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umar64.c
@@ -0,0 +1,19 @@
+/* umar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umar64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+uint64_t ramu (uint64_t t,unsigned int a,unsigned int b)
+{
+  return __rv_umar64 (t, a, b);
+}
+
+uint64_t test_autogen(uint64_t t, uint32_t a, uint32_t b) {
+  return t + (uint64_t)a * (uint64_t)b;
+}
+
+/* { dg-final { scan-assembler-times "umar64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umax16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umax16.c
new file mode 100644
index 000000000000..f71fc727d3a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umax16.c
@@ -0,0 +1,21 @@
+/* umax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t xamu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t xamu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umin16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umin16.c
new file mode 100644
index 000000000000..54cb57aa218d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umin16.c
@@ -0,0 +1,21 @@
+/* umin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t nimu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t nimu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umsr64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umsr64.c
new file mode 100644
index 000000000000..ea2130c64f45
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umsr64.c
@@ -0,0 +1,19 @@
+/* umsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umsr64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+uint64_t rsmu (uint64_t t, unsigned int a, unsigned int b)
+{
+  return __rv_umsr64 (t, a, b);
+}
+
+uint64_t test_autogen(uint64_t t, uint32_t a, uint32_t b) {
+  return t - (uint64_t)a * (uint64_t)b;
+}
+
+/* { dg-final { scan-assembler-times "umsr64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul16.c
new file mode 100644
index 000000000000..f41e7c2347c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul16.c
@@ -0,0 +1,21 @@
+/* umul16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umul16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umul16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t lumu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umul16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umul16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul8.c
new file mode 100644
index 000000000000..bf8ac795ceae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul8.c
@@ -0,0 +1,21 @@
+/* umul8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umul8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umul8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t lumu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_umul8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umul8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx16.c
new file mode 100644
index 000000000000..0398ed3c5b88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx16.c
@@ -0,0 +1,21 @@
+/* umulx16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umulx16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umulx16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t xlumu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umulx16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umulx16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx8.c
new file mode 100644
index 000000000000..447bb13ea57a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx8.c
@@ -0,0 +1,21 @@
+/* umulx8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umulx8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umulx8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t xlumu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_umulx8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umulx8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd16.c
new file mode 100644
index 000000000000..5e015527033a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd16.c
@@ -0,0 +1,21 @@
+/* uradd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uradd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ddaru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_uradd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd64.c
new file mode 100644
index 000000000000..6abb4a57a6dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd64.c
@@ -0,0 +1,15 @@
+/* uradd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd8.c
new file mode 100644
index 000000000000..19536d11941e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd8.c
@@ -0,0 +1,21 @@
+/* uradd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uradd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t ddaru_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_uradd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uraddw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uraddw.c
new file mode 100644
index 000000000000..40680db9e0a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uraddw.c
@@ -0,0 +1,15 @@
+/* uraddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uraddw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t wddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uraddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uraddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcras16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcras16.c
new file mode 100644
index 000000000000..7995e3e4cb56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcras16.c
@@ -0,0 +1,21 @@
+/* urcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcras16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t sarcru (uint32_t ra, uint32_t rb)
+{
+  return __rv_urcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t sarcru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_urcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcrsa16.c
new file mode 100644
index 000000000000..9fae75c5e031
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcrsa16.c
@@ -0,0 +1,21 @@
+/* urcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcrsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t asrcru (uint32_t ra, uint32_t rb)
+{
+  return __rv_urcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t asrcru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_urcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub16.c
new file mode 100644
index 000000000000..1edc0fdf23ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub16.c
@@ -0,0 +1,21 @@
+/* ursub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busru (uint32_t ra, uint32_t rb)
+{
+  return __rv_ursub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t busru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ursub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub64.c
new file mode 100644
index 000000000000..44691be66492
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub64.c
@@ -0,0 +1,15 @@
+/* ursub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub8.c
new file mode 100644
index 000000000000..da5a26336c7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub8.c
@@ -0,0 +1,21 @@
+/* ursub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busru (uint32_t ra, uint32_t rb)
+{
+  return __rv_ursub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t busru_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ursub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursubw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursubw.c
new file mode 100644
index 000000000000..a306cadf95db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursubw.c
@@ -0,0 +1,15 @@
+/* ursubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursubw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t wbusru (unsigned int ra,unsigned int rb)
+{
+  return __rv_ursubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-wext.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-wext.c
new file mode 100644
index 000000000000..dc5cc8e83665
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-wext.c
@@ -0,0 +1,15 @@
+/* wext also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for wext instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t txew (int64_t ra, uint32_t rb)
+{
+  return __rv_wext (ra, rb);
+}
+/* { dg-final { scan-assembler-times "wext" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zbpbo.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zbpbo.c
new file mode 100644
index 000000000000..66bfba7f4df9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zbpbo.c
@@ -0,0 +1,115 @@
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zbpbo_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t foo (uint32_t a)
+{
+  return __rv_clz (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2 (uintXLEN_t a, uintXLEN_t b, uintXLEN_t c)
+{
+  return __rv_cmix (a, b, c);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo3(uint32_t a, uint32_t b, uint32_t c)
+{
+  return __rv_fsr (a, b, c);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo4(uint32_t a, uint32_t b)
+{
+  return __rv_fsr (a, 1, b);
+}
+
+static __attribute__ ((noinline))
+int32_t foo5(int32_t a, int32_t b)
+{
+  return __rv_max (a, b);
+}
+
+static __attribute__ ((noinline))
+int32_t foo6(int32_t a, int32_t b)
+{
+  return __rv_min (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo7(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_pack (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_packu (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo9(uintXLEN_t a)
+{
+  return __rv_rev (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a)
+{
+  return __rv_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo11(uint8xN_t a)
+{
+  return __rv_v_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo12(uintXLEN_t a)
+{
+  return __rv_swap8 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo13(uint8xN_t a)
+{
+  return __rv_v_swap8 (a);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo14 (uint32_t ra, uint32_t rb)
+{
+  return __rv_pkbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo15 (uint32_t ra, uint32_t rb)
+{
+  return __rv_pktt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo18 (uint32_t a)
+{
+  return __rv_clz32 (a);
+}
+/* { dg-final { scan-assembler-times "rev8.h" 4 } } */
+/* { dg-final { scan-assembler-times "rev" 5 } } */
+/* { dg-final { scan-assembler-times "pack" 4 } } */
+/* { dg-final { scan-assembler-times "packu" 2 } } */
+/* { dg-final { scan-assembler-times "min" 1 } } */
+/* { dg-final { scan-assembler-times "max" 1 } } */
+/* { dg-final { scan-assembler-times "fsr" 2 } } */
+/* { dg-final { scan-assembler-times "fsri" 1 } } */
+/* { dg-final { scan-assembler-times "cmix" 1 } } */
+/* { dg-final { scan-assembler-times "clz" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
+/* { dg-final { scan-assembler-times "maxw" 0 } } */
+/* { dg-final { scan-assembler-times "minw" 0 } } */
+/* { dg-final { scan-assembler-times "clz32" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd810.c
new file mode 100644
index 000000000000..f3b98d96214f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd810.c
@@ -0,0 +1,21 @@
+/* zunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd810 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd820.c
new file mode 100644
index 000000000000..6faade029280
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd820.c
@@ -0,0 +1,21 @@
+/* zunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd820 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd830.c
new file mode 100644
index 000000000000..cd4f65fa6d66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd830.c
@@ -0,0 +1,21 @@
+/* zunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd830 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd831.c
new file mode 100644
index 000000000000..a95be4bd451c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd831.c
@@ -0,0 +1,21 @@
+/* zunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd831 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd832.c
new file mode 100644
index 000000000000..147a40d32420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd832.c
@@ -0,0 +1,21 @@
+/* zunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd832 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/rvp32.exp b/gcc/testsuite/gcc.target/riscv/rvp32_scan/rvp32.exp
new file mode 100644
index 000000000000..13aa2dd52ca8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/rvp32.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2017-2020 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv32*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add16.c
new file mode 100644
index 000000000000..a9830bb27e4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add16.c
@@ -0,0 +1,25 @@
+/* add16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dda (uint64_t ra, uint64_t rb)
+{
+  return __rv_add16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ddau_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_uadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ddas_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_sadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add32.c
new file mode 100644
index 000000000000..834d4635c415
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add32.c
@@ -0,0 +1,25 @@
+/* add32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dda (uint64_t ra, uint64_t rb)
+{
+  return __rv_add32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ddau_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_uadd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ddas_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_sadd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add8.c
new file mode 100644
index 000000000000..628b2fd97fc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add8.c
@@ -0,0 +1,25 @@
+/* add8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dda (uint64_t ra, uint64_t rb)
+{
+  return __rv_add8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t ddau_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_uadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t ddas_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_sadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-bitrev.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-bitrev.c
new file mode 100644
index 000000000000..76d535df3113
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-bitrev.c
@@ -0,0 +1,21 @@
+/* bitrev also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for bitrev instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t vertib (uint64_t ra, uint32_t rb)
+{
+  return __rv_bitrev (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint64_t ivertib (uint64_t ra)
+{
+  return __rv_bitrev (ra, 3);
+}
+
+/* { dg-final { scan-assembler-times "bitrev" 3 } } */
+/* { dg-final { scan-assembler-times "bitrevi" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq16.c
new file mode 100644
index 000000000000..67b1b14620de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq16.c
@@ -0,0 +1,23 @@
+/* cmpeq16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t qepmc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cmpeq16 (ra, rb);
+}
+static __attribute__ ((noinline))
+uint16x4_t qepmcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scmpeq16 (ra, rb);
+}
+static __attribute__ ((noinline))
+uint16x4_t qepmcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucmpeq16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq8.c
new file mode 100644
index 000000000000..77385b95cd40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq8.c
@@ -0,0 +1,25 @@
+/* cmpeq8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t qepmc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t qepmcs_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_scmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t qepmcu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ucmpeq8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-count.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-count.c
new file mode 100644
index 000000000000..3027afa752f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-count.c
@@ -0,0 +1,72 @@
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a) {
+  return __rv_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo1(uintXLEN_t a) {
+  return __rv_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a) {
+  return __rv_clrs32 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a) {
+  return __rv_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo4(uintXLEN_t a) {
+  return __rv_clz16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo5(uintXLEN_t a) {
+  return __rv_clz32 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo6(int8xN_t a) {
+  return __rv_v_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(int16xN_t a) {
+  return __rv_v_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t foo8(int32x2_t a) {
+  return __rv_v_clrs32 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo9(uint8xN_t a) {
+  return __rv_v_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo10(uint16xN_t a) {
+  return __rv_v_clz16 (a);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t foo11(uint32x2_t a) {
+  return __rv_v_clz32 (a);
+}
+
+/* { dg-final { scan-assembler-times "clrs8" 2 } } */
+/* { dg-final { scan-assembler-times "clrs16" 2 } } */
+/* { dg-final { scan-assembler-times "clrs32" 2 } } */
+/* { dg-final { scan-assembler-times "clz8" 2 } } */
+/* { dg-final { scan-assembler-times "clz16" 2 } } */
+/* { dg-final { scan-assembler-times "clz32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras16.c
new file mode 100644
index 000000000000..af89a5edf420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras16.c
@@ -0,0 +1,25 @@
+/* cras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t sarcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sarcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cras16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras32.c
new file mode 100644
index 000000000000..01cfbb00beab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras32.c
@@ -0,0 +1,25 @@
+/* cras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t sarcu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ucras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sarcs_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_scras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cras32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa16.c
new file mode 100644
index 000000000000..8b2e963b459b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa16.c
@@ -0,0 +1,25 @@
+/* crsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrc (uint64_t ra, uint64_t rb)
+{
+  return __rv_crsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t asrcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t asrcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "crsa16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa32.c
new file mode 100644
index 000000000000..e021878c9c11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa32.c
@@ -0,0 +1,25 @@
+/* crsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrc (uint64_t ra, uint64_t rb)
+{
+  return __rv_crsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t asrcu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ucrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t asrcs_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_scrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "crsa32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-insb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-insb.c
new file mode 100644
index 000000000000..e6c8622bf3e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-insb.c
@@ -0,0 +1,13 @@
+/* insb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for insb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bsni (uint64_t ra, uint32_t rb)
+{
+  return __rv_insb (ra, rb, 1);
+}
+/* { dg-final { scan-assembler-times "insb" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs16.c
new file mode 100644
index 000000000000..01c1c830ab43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs16.c
@@ -0,0 +1,19 @@
+/* kabs16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kabs16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sbak (uint64_t ra)
+{
+  return __rv_kabs16 (ra);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sbak_v (int16x4_t ra)
+{
+  return __rv_v_kabs16 (ra);
+}
+/* { dg-final { scan-assembler-times "kabs16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs32.c
new file mode 100644
index 000000000000..04320936fda0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs32.c
@@ -0,0 +1,19 @@
+/* kabs32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kabs32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sbak (uint64_t ra)
+{
+  return __rv_kabs32 (ra);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sbak_v (int32x2_t ra)
+{
+  return __rv_v_kabs32 (ra);
+}
+/* { dg-final { scan-assembler-times "kabs32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs8.c
new file mode 100644
index 000000000000..20c48d185f98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs8.c
@@ -0,0 +1,19 @@
+/* kabs8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kabs8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sbak (uint64_t ra)
+{
+  return __rv_kabs8 (ra);
+}
+
+static __attribute__ ((noinline))
+int8x8_t sbak_v (int8x8_t ra)
+{
+  return __rv_v_kabs8 (ra);
+}
+/* { dg-final { scan-assembler-times "kabs8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd16.c
new file mode 100644
index 000000000000..ad6a2bcdbf69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd16.c
@@ -0,0 +1,19 @@
+/* kadd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddak (uint64_t ra, uint64_t rb)
+{
+  return __rv_kadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ddak_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd32.c
new file mode 100644
index 000000000000..bb7179c25150
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd32.c
@@ -0,0 +1,19 @@
+/* kadd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kadd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddak (uint64_t ra, uint64_t rb)
+{
+  return __rv_kadd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ddak_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kadd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd64.c
new file mode 100644
index 000000000000..1a623aa7bfb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd64.c
@@ -0,0 +1,13 @@
+/* kadd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kadd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ddak (int64_t ra, int64_t rb)
+{
+  return __rv_kadd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd8.c
new file mode 100644
index 000000000000..e19d031e0dbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd8.c
@@ -0,0 +1,19 @@
+/* kadd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddak (uint64_t ra, uint64_t rb)
+{
+  return __rv_kadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t ddak_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_kadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddh.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddh.c
new file mode 100644
index 000000000000..86f78b475a30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddh.c
@@ -0,0 +1,13 @@
+/* kaddh also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kaddh instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t hddak (int16_t ra, int16_t rb)
+{
+  return __rv_kaddh (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kaddh" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddw.c
new file mode 100644
index 000000000000..af478c31fd52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddw.c
@@ -0,0 +1,13 @@
+/* kaddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kaddw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t wddak (int32_t ra, int32_t rb)
+{
+  return __rv_kaddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kaddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras16.c
new file mode 100644
index 000000000000..1be710547f06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras16.c
@@ -0,0 +1,19 @@
+/* kcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarc (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sarck_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras32.c
new file mode 100644
index 000000000000..d486d3e00d85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras32.c
@@ -0,0 +1,19 @@
+/* kcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarck (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sarck_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa16.c
new file mode 100644
index 000000000000..1d71c785ee05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa16.c
@@ -0,0 +1,19 @@
+/* kcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrck (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t asrck_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa32.c
new file mode 100644
index 000000000000..df14b0f23c07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa32.c
@@ -0,0 +1,19 @@
+/* kcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrck (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t asrck_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb.c
new file mode 100644
index 000000000000..d75c7bf6c681
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb.c
@@ -0,0 +1,19 @@
+/* kdmbb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t bbmdk (uint32_t ra, uint32_t rb)
+{
+  return __rv_kdmbb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t bbmdk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_kdmbb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb16.c
new file mode 100644
index 000000000000..6297b0546c61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb16.c
@@ -0,0 +1,19 @@
+/* kdmbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbmdk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kdmbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbmdk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kdmbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt.c
new file mode 100644
index 000000000000..ec4a20178469
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt.c
@@ -0,0 +1,19 @@
+/* kdmbt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t tbmdk (uint32_t ra, uint32_t rb)
+{
+  return __rv_kdmbt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t tbmdk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_kdmbt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt16.c
new file mode 100644
index 000000000000..7381827fb8cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt16.c
@@ -0,0 +1,19 @@
+/* kdmbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tbmdk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kdmbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbmdk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kdmbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt.c
new file mode 100644
index 000000000000..5ab7de8d178a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt.c
@@ -0,0 +1,19 @@
+/* kdmtt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmtt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t ttmdk (uint32_t ra, uint32_t rb)
+{
+  return __rv_kdmtt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t ttmdk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_kdmtt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmtt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt16.c
new file mode 100644
index 000000000000..76b1e9658685
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt16.c
@@ -0,0 +1,19 @@
+/* kdmtt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmtt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttmdk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kdmtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttmdk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kdmtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmtt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm16.c
new file mode 100644
index 000000000000..7201f0ec1445
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm16.c
@@ -0,0 +1,19 @@
+/* khm16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khm16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t mhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khm16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t mhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khm16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khm16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm8.c
new file mode 100644
index 000000000000..b08dccc3109d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm8.c
@@ -0,0 +1,19 @@
+/* khm8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khm8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t mhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khm8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t mhk_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_khm8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khm8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb.c
new file mode 100644
index 000000000000..1843eac684d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb.c
@@ -0,0 +1,19 @@
+/* khmbb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbmhk (uint32_t ra, uint32_t rb)
+{
+  return __rv_khmbb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t bbmhk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_khmbb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb16.c
new file mode 100644
index 000000000000..44dd26c0672c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb16.c
@@ -0,0 +1,19 @@
+/* khmbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt.c
new file mode 100644
index 000000000000..a261d96a422d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt.c
@@ -0,0 +1,19 @@
+/* khmbt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbmhk (uint32_t ra, uint32_t rb)
+{
+  return __rv_khmbt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t tbmhk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_khmbt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt16.c
new file mode 100644
index 000000000000..392a441b5160
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt16.c
@@ -0,0 +1,19 @@
+/* khmbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tbmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt.c
new file mode 100644
index 000000000000..89ca750ecd33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt.c
@@ -0,0 +1,19 @@
+/* khmtt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmtt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttmhk (uint32_t ra, uint32_t rb)
+{
+  return __rv_khmtt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ttmhk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_khmtt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmtt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt16.c
new file mode 100644
index 000000000000..9bd88f3c62ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt16.c
@@ -0,0 +1,19 @@
+/* khmtt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmtt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmtt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx16.c
new file mode 100644
index 000000000000..b008a164fd58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx16.c
@@ -0,0 +1,19 @@
+/* khmx16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmx16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmx16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t xmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmx16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmx16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx8.c
new file mode 100644
index 000000000000..e62427faa841
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx8.c
@@ -0,0 +1,19 @@
+/* khmx8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmx8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmx8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t xmhk_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_khmx8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmx8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb.c
new file mode 100644
index 000000000000..f3f93fbf6e81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb.c
@@ -0,0 +1,19 @@
+/* kmabb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabb (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmabb (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb32.c
new file mode 100644
index 000000000000..024a9918980b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb32.c
@@ -0,0 +1,19 @@
+/* kmabb32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabb32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabb32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t bbamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmabb32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabb32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt.c
new file mode 100644
index 000000000000..f8615b6f690b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt.c
@@ -0,0 +1,19 @@
+/* kmabt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabt (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmabt (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt32.c
new file mode 100644
index 000000000000..cc8ec0ad3c02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt32.c
@@ -0,0 +1,19 @@
+/* kmabt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabt32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t tbamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmabt32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada.c
new file mode 100644
index 000000000000..4f799af2712f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada.c
@@ -0,0 +1,19 @@
+/* kmada also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmada instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmada (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmada (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmada" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada32.c
new file mode 100644
index 000000000000..4eb0666ced5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada32.c
@@ -0,0 +1,19 @@
+/* kmada32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmada32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmada32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmada32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs.c
new file mode 100644
index 000000000000..952c20f9d744
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs.c
@@ -0,0 +1,19 @@
+/* kmadrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmadrs instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdamk (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmadrs (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t srdamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmadrs (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmadrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs32.c
new file mode 100644
index 000000000000..6a3ec8984d58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs32.c
@@ -0,0 +1,19 @@
+/* kmadrs32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmadrs32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmadrs32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t srdamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmadrs32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmadrs32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads.c
new file mode 100644
index 000000000000..06268364f2a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads.c
@@ -0,0 +1,19 @@
+/* kmads also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmads instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdamk (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmads (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmads (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmads" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads32.c
new file mode 100644
index 000000000000..f9b7dc9f05a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads32.c
@@ -0,0 +1,19 @@
+/* kmads32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmads32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmads32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmads32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmads32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmar64.c
new file mode 100644
index 000000000000..18029f74e618
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmar64.c
@@ -0,0 +1,19 @@
+/* kmar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ramk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmar64 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ramk2 (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmar64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt.c
new file mode 100644
index 000000000000..4d8fc8560133
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt.c
@@ -0,0 +1,19 @@
+/* kmatt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmatt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmatt (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmatt (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmatt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt32.c
new file mode 100644
index 000000000000..a6b94b60488b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt32.c
@@ -0,0 +1,19 @@
+/* kmatt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmatt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmatt32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ttamk_v (uint64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmatt32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmatt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda.c
new file mode 100644
index 000000000000..0e2dd29cb447
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda.c
@@ -0,0 +1,19 @@
+/* kmaxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxamk (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxda (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adxamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmaxda (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda32.c
new file mode 100644
index 000000000000..b10711907fc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda32.c
@@ -0,0 +1,19 @@
+/* kmaxda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxda32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmaxda32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds.c
new file mode 100644
index 000000000000..8437dba74bdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds.c
@@ -0,0 +1,19 @@
+/* kmaxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxds (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdxamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmaxds (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds32.c
new file mode 100644
index 000000000000..a9cabf284706
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds32.c
@@ -0,0 +1,19 @@
+/* kmaxds32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxds32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxds32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxamk_v (int32_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmaxds32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxds32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda.c
new file mode 100644
index 000000000000..6f940ace35ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda.c
@@ -0,0 +1,19 @@
+/* kmda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t admk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmda (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t admk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmda (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda32.c
new file mode 100644
index 000000000000..d98da686b74e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda32.c
@@ -0,0 +1,19 @@
+/* kmda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t admk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmda32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t admk_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmda32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmac.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmac.c
new file mode 100644
index 000000000000..1b6e273e598e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmac.c
@@ -0,0 +1,19 @@
+/* kmmac also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmac instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t cammk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmac (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t cammk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmac (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmac" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmacu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmacu.c
new file mode 100644
index 000000000000..e30ab4ff2831
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmacu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmacu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ucammk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmac_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ucammk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmac_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmac.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb.c
new file mode 100644
index 000000000000..93638e4f557b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb.c
@@ -0,0 +1,19 @@
+/* kmmawb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2.c
new file mode 100644
index 000000000000..3a58b2493c7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2.c
@@ -0,0 +1,19 @@
+/* kmmawb2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawb2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb2 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb2 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2u.c
new file mode 100644
index 000000000000..15cc4865b40f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawb2.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2bwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb2_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2bwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb2_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawbu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawbu.c
new file mode 100644
index 000000000000..6831352972ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawbu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawb.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ubwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ubwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt.c
new file mode 100644
index 000000000000..7bd36727d645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt.c
@@ -0,0 +1,19 @@
+/* kmmawt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2.c
new file mode 100644
index 000000000000..1defba2b55d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2.c
@@ -0,0 +1,19 @@
+/* kmmawt2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawt2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt2 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt2 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2u.c
new file mode 100644
index 000000000000..3cfab265307f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawt2.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2twammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt2_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2twammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt2_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawtu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawtu.c
new file mode 100644
index 000000000000..66b6e99d354b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawtu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawt.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t utwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t utwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsb.c
new file mode 100644
index 000000000000..7e979d796002
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsb.c
@@ -0,0 +1,19 @@
+/* kmmsb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmsb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bsmmk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmsb (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bsmmk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmsb (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmsb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsbu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsbu.c
new file mode 100644
index 000000000000..14ad33e444ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsbu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmsbu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ubsmmk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmsb_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bsmmk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmsb_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmsb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2.c
new file mode 100644
index 000000000000..fc5c4fc323b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2.c
@@ -0,0 +1,19 @@
+/* kmmwb2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmwb2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwmmk (int64_t ra, int64_t rb)
+{
+  return __rv_kmmwb2 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwb2 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwb2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2u.c
new file mode 100644
index 000000000000..bf689e1bcbf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmwb2u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2bwmmk (int64_t ra, int64_t rb)
+{
+  return __rv_kmmwb2_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2bwmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwb2_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwb2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2.c
new file mode 100644
index 000000000000..3ed4ce4c72e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2.c
@@ -0,0 +1,19 @@
+/* kmmwt2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmwt2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twmmk (int64_t ra, uint64_t rb)
+{
+  return __rv_kmmwt2 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwt2 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwt2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2u.c
new file mode 100644
index 000000000000..f5dafd50a4a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmwt2u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2twmmk (int64_t ra, uint64_t rb)
+{
+  return __rv_kmmwt2_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2twmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwt2_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwt2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda.c
new file mode 100644
index 000000000000..0dd7481cc704
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda.c
@@ -0,0 +1,19 @@
+/* kmsda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsda (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adsmk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmsda (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda32.c
new file mode 100644
index 000000000000..bd96a6f53024
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda32.c
@@ -0,0 +1,19 @@
+/* kmsda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsda32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adsmk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmsda32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsr64.c
new file mode 100644
index 000000000000..c83dbc666678
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsr64.c
@@ -0,0 +1,19 @@
+/* kmsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t rsmk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmsr64 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t rsmk2 (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsr64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda.c
new file mode 100644
index 000000000000..47a296608c1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda.c
@@ -0,0 +1,19 @@
+/* kmsxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsxda (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adxsmk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmsxda (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda32.c
new file mode 100644
index 000000000000..b4882d8d728d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda32.c
@@ -0,0 +1,19 @@
+/* kmsxda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsxda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsxda32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxsmk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmsxda32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsxda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda.c
new file mode 100644
index 000000000000..08a21cac0fb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda.c
@@ -0,0 +1,19 @@
+/* kmxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxmk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmxda (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adxmk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmxda (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda32.c
new file mode 100644
index 000000000000..bab80fbd1ed8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda32.c
@@ -0,0 +1,19 @@
+/* kmxda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmxda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxmk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmxda32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxmk_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmxda32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmxda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll.c
new file mode 100644
index 000000000000..3f89cbcc3496
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll.c
@@ -0,0 +1,12 @@
+/* This is a test program for ksll instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t llsk (int32_t ra, uint32_t rb)
+{
+  return __rv_ksllw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksllw" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll16.c
new file mode 100644
index 000000000000..e4ca36910f80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll16.c
@@ -0,0 +1,19 @@
+/* ksll16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksll16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t llsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_ksll16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t llsk_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_ksll16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksll16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll32.c
new file mode 100644
index 000000000000..e957ffc64679
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll32.c
@@ -0,0 +1,19 @@
+/* ksll32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksll32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t llsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_ksll32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t llsk_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_ksll32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksll32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslli.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslli.c
new file mode 100644
index 000000000000..bfc82eecdad7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslli.c
@@ -0,0 +1,12 @@
+/* This is a test program for kslli instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t illsk (int32_t ra)
+{
+  return __rv_ksllw (ra, 8);
+}
+/* { dg-final { scan-assembler-times "kslliw" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16.c
new file mode 100644
index 000000000000..909d083c4da2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16.c
@@ -0,0 +1,19 @@
+/* kslra16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslra16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t arlsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_kslra16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t arlsk_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_kslra16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16u.c
new file mode 100644
index 000000000000..032274fb8864
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kslra16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u61arlsk (uint64_t ra, int32_t rb)
+{
+  return __rv_kslra16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t u61arlsk_v (int16x4_t ra, int32_t rb)
+{
+  return __rv_v_kslra16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32.c
new file mode 100644
index 000000000000..48002dd69367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32.c
@@ -0,0 +1,19 @@
+/* kslra32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslra32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t arlsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_kslra32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t arlsk_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_kslra32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32u.c
new file mode 100644
index 000000000000..df034d0b9e99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kslra32.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23arlsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_kslra32_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u23arlsk_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_kslra32_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslraw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslraw.c
new file mode 100644
index 000000000000..5df586c2b122
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslraw.c
@@ -0,0 +1,13 @@
+/* kslraw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslraw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t warlsk (int32_t ra, int32_t rb)
+{
+  return __rv_kslraw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslraw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslrawu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslrawu.c
new file mode 100644
index 000000000000..5df586c2b122
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslrawu.c
@@ -0,0 +1,13 @@
+/* kslraw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslraw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t warlsk (int32_t ra, int32_t rb)
+{
+  return __rv_kslraw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslraw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub16.c
new file mode 100644
index 000000000000..14714b70a071
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub16.c
@@ -0,0 +1,19 @@
+/* ksub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busk (uint64_t ra, uint64_t rb)
+{
+  return __rv_ksub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t busk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_ksub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub32.c
new file mode 100644
index 000000000000..e1af892ac8fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub32.c
@@ -0,0 +1,19 @@
+/* ksub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busk (uint64_t ra, uint64_t rb)
+{
+  return __rv_ksub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t busk_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_ksub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub64.c
new file mode 100644
index 000000000000..a0896cdf556f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub64.c
@@ -0,0 +1,13 @@
+/* ksub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t busk (int64_t ra, int64_t rb)
+{
+  return __rv_ksub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub8.c
new file mode 100644
index 000000000000..673230074fdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub8.c
@@ -0,0 +1,19 @@
+/* ksub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busk (uint64_t ra, uint64_t rb)
+{
+  return __rv_ksub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t busk_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_ksub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubh.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubh.c
new file mode 100644
index 000000000000..d16040937610
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubh.c
@@ -0,0 +1,13 @@
+/* ksubh also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksubh instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t hbusk (int16_t ra, int16_t rb)
+{
+  return __rv_ksubh (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksubh" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubw.c
new file mode 100644
index 000000000000..af07ce051560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubw.c
@@ -0,0 +1,13 @@
+/* ksubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksubw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int wbusk (int ra, int rb)
+{
+  return __rv_ksubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmul.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmul.c
new file mode 100644
index 000000000000..085c4b9ad850
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmul.c
@@ -0,0 +1,13 @@
+/* kwmmul also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kwmmul instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t lummwk (int64_t ra, int64_t rb)
+{
+  return __rv_kwmmul (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kwmmul" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmulu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmulu.c
new file mode 100644
index 000000000000..27635b6d3ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmulu.c
@@ -0,0 +1,12 @@
+/* This is a test program for kwmmulu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ulummwk (int64_t ra, int64_t rb)
+{
+  return __rv_kwmmul_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kwmmul.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-mfb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-mfb.c
new file mode 100644
index 000000000000..570f6c36e76e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-mfb.c
@@ -0,0 +1,39 @@
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+intXLEN_t foo(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+intXLEN_t foo1(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_umaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo3(int32xN_t t, int8xN_t a, int8xN_t b) {
+  return __rv_v_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo4(int32xN_t t, int8xN_t a, uint8xN_t b) {
+  return __rv_v_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo5(uint32xN_t t, uint8xN_t a, uint8xN_t b) {
+  return __rv_v_umaqa (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaqa.su" 2 } } */
+/* { dg-final { scan-assembler-times "smaqa" 4 } } */
+/* { dg-final { scan-assembler-times "umaqa" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbb16.c
new file mode 100644
index 000000000000..56ad57db596d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbb16.c
@@ -0,0 +1,19 @@
+/* pkbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pkbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t bbkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pkbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbt16.c
new file mode 100644
index 000000000000..3cbedf648400
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbt16.c
@@ -0,0 +1,19 @@
+/* pkbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tbkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pkbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t tbkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pkbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktb16.c
new file mode 100644
index 000000000000..5cc4c83a64f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktb16.c
@@ -0,0 +1,19 @@
+/* pktb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t btkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pktb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t btkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pktb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktt16.c
new file mode 100644
index 000000000000..637d2793b7ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktt16.c
@@ -0,0 +1,19 @@
+/* pktt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pktt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ttkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pktt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd16.c
new file mode 100644
index 000000000000..2e3131d2387b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd16.c
@@ -0,0 +1,19 @@
+/* radd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddar (uint64_t ra, uint64_t rb)
+{
+  return __rv_radd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ddar_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_radd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd32.c
new file mode 100644
index 000000000000..6443f7546c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd32.c
@@ -0,0 +1,19 @@
+/* radd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddar (uint64_t ra, uint64_t rb)
+{
+  return __rv_radd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ddar_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_radd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd64.c
new file mode 100644
index 000000000000..7adc8bb1b202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd64.c
@@ -0,0 +1,13 @@
+/* radd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ddar (int64_t ra, int64_t rb)
+{
+  return __rv_radd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd8.c
new file mode 100644
index 000000000000..c717ed8be8b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd8.c
@@ -0,0 +1,19 @@
+/* radd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddar (uint64_t ra, uint64_t rb)
+{
+  return __rv_radd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t ddar_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_radd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-raddw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-raddw.c
new file mode 100644
index 000000000000..f9ffea056c81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-raddw.c
@@ -0,0 +1,13 @@
+/* raddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for raddw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t wddar (int32_t ra, int32_t rb)
+{
+  return __rv_raddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "raddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras16.c
new file mode 100644
index 000000000000..a43231a4d9b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras16.c
@@ -0,0 +1,19 @@
+/* rcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sarcr_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_rcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras32.c
new file mode 100644
index 000000000000..44ce8ae58871
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras32.c
@@ -0,0 +1,19 @@
+/* rcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sarcr_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_rcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa16.c
new file mode 100644
index 000000000000..f16d22d67891
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa16.c
@@ -0,0 +1,19 @@
+/* rcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcrsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t asrcr_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_rcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa32.c
new file mode 100644
index 000000000000..f41b1ed0eccf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa32.c
@@ -0,0 +1,19 @@
+/* rcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t asrcr_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_rcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub16.c
new file mode 100644
index 000000000000..697bfb427f72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub16.c
@@ -0,0 +1,19 @@
+/* rsub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rsub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t busr_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_rsub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub32.c
new file mode 100644
index 000000000000..8a93bf505ee9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub32.c
@@ -0,0 +1,19 @@
+/* rsub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rsub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t busr_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_rsub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub64.c
new file mode 100644
index 000000000000..bb65b1a943c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub64.c
@@ -0,0 +1,13 @@
+/* rsub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t busr (int64_t ra, int64_t rb)
+{
+  return __rv_rsub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub8.c
new file mode 100644
index 000000000000..1912f277ce90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub8.c
@@ -0,0 +1,19 @@
+/* rsub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rsub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t busr_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_rsub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsubw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsubw.c
new file mode 100644
index 000000000000..d765587c44ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsubw.c
@@ -0,0 +1,13 @@
+/* rsubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsubw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t wbusr (int32_t ra, int32_t rb)
+{
+  return __rv_rsubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip16.c
new file mode 100644
index 000000000000..7829336cfe92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip16.c
@@ -0,0 +1,19 @@
+/* sclip16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sclip16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t pilcs (int64_t ra)
+{
+  return __rv_sclip16 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+int16x4_t pilcs_v (int16x4_t ra)
+{
+  return __rv_v_sclip16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "sclip16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip32.c
new file mode 100644
index 000000000000..cc933ce3439a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip32.c
@@ -0,0 +1,13 @@
+/* sclip32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t pilcs (int64_t ra)
+{
+  return __rv_sclip32 (ra, 5);
+}
+/* { dg-final { scan-assembler-times "sclip32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple16.c
new file mode 100644
index 000000000000..dd47b483537d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple16.c
@@ -0,0 +1,19 @@
+/* scmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t elpmcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple8.c
new file mode 100644
index 000000000000..e44b17d15771
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple8.c
@@ -0,0 +1,19 @@
+/* scmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t elpmcs_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_scmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt16.c
new file mode 100644
index 000000000000..571e4a2218c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt16.c
@@ -0,0 +1,19 @@
+/* scmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t tlpmcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt8.c
new file mode 100644
index 000000000000..0f5e19fcc3b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt8.c
@@ -0,0 +1,19 @@
+/* scmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t tlpmcs_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_scmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll16.c
new file mode 100644
index 000000000000..585abfa46a25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll16.c
@@ -0,0 +1,19 @@
+/* sll16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lls (uint64_t ra, uint32_t rb)
+{
+  return __rv_sll16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t lls_v (uint16x4_t ra, uint32_t rb)
+{
+  return __rv_v_sll16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll32.c
new file mode 100644
index 000000000000..3717363b65db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll32.c
@@ -0,0 +1,19 @@
+/* sll32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lls (uint64_t ra, uint32_t rb)
+{
+  return __rv_sll32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t lls_v (uint32x2_t ra, uint32_t rb)
+{
+  return __rv_v_sll32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-slli32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-slli32.c
new file mode 100644
index 000000000000..a3782665191f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-slli32.c
@@ -0,0 +1,18 @@
+/* This is a test program for slli32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ills (uint64_t ra)
+{
+  return __rv_sll32 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ills_v (uint32x2_t ra)
+{
+  return __rv_v_sll32 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "slli32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smal.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smal.c
new file mode 100644
index 000000000000..a7dbe833c48b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smal.c
@@ -0,0 +1,19 @@
+/* smal also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smal instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t lams (int64_t ra, int64_t rb)
+{
+  return __rv_smal (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t lams_v (int64_t ra, int16x4_t rb)
+{
+  return __rv_v_smal (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smal" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbb.c
new file mode 100644
index 000000000000..0096799d3fd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbb.c
@@ -0,0 +1,20 @@
+/* smalbb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bblams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalbb (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t bblams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalbb (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalbb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbt.c
new file mode 100644
index 000000000000..3eb27a76102d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbt.c
@@ -0,0 +1,20 @@
+/* smalbt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tblams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalbt (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t tblams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalbt (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalbt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalda.c
new file mode 100644
index 000000000000..261c33d6924e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalda.c
@@ -0,0 +1,20 @@
+/* smalda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaldrs.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaldrs.c
new file mode 100644
index 000000000000..1efd5d33b0eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaldrs.c
@@ -0,0 +1,20 @@
+/* smaldrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smaldrs instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smaldrs (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t srdlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smaldrs (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaldrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalds.c
new file mode 100644
index 000000000000..35393e049e57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalds.c
@@ -0,0 +1,20 @@
+/* smalds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaltt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaltt.c
new file mode 100644
index 000000000000..8250a84ce878
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaltt.c
@@ -0,0 +1,20 @@
+/* smaltt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smaltt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smaltt (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t ttlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smaltt (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaltt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxda.c
new file mode 100644
index 000000000000..0991fc915f91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxda.c
@@ -0,0 +1,20 @@
+/* smalxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalxda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalxda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxds.c
new file mode 100644
index 000000000000..8f9e7e2b32e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxds.c
@@ -0,0 +1,20 @@
+/* smalxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalxds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalxds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smar64.c
new file mode 100644
index 000000000000..dee5c01adf8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smar64.c
@@ -0,0 +1,13 @@
+/* smar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t rams (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_smar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax16.c
new file mode 100644
index 000000000000..1cf0575444de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax16.c
@@ -0,0 +1,19 @@
+/* smax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xams (uint64_t ra, uint64_t rb)
+{
+  return __rv_smax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t xams_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax32.c
new file mode 100644
index 000000000000..fed71e33e59b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax32.c
@@ -0,0 +1,19 @@
+/* smax32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xams (uint64_t ra, uint64_t rb)
+{
+  return __rv_smax32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t xams_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smax32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax8.c
new file mode 100644
index 000000000000..4173151c666f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax8.c
@@ -0,0 +1,19 @@
+/* smax8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xams (uint64_t ra, uint64_t rb)
+{
+  return __rv_smax8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t xams_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_smax8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb.c
new file mode 100644
index 000000000000..72e603d70af9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb.c
@@ -0,0 +1,18 @@
+/* This is a test program for smbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbb16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb32.c
new file mode 100644
index 000000000000..c3749f03454d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb32.c
@@ -0,0 +1,19 @@
+/* smbb32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smbb32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbb32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t bbms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smbb32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbb32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt.c
new file mode 100644
index 000000000000..899eb98b80ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt.c
@@ -0,0 +1,18 @@
+/* This is a test program for smbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt32.c
new file mode 100644
index 000000000000..821d97c494bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt32.c
@@ -0,0 +1,19 @@
+/* smbt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smbt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbt32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t tbms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smbt32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs.c
new file mode 100644
index 000000000000..1908e9645cb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs.c
@@ -0,0 +1,19 @@
+/* smdrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smdrs instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smdrs (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t srdms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smdrs (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smdrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs32.c
new file mode 100644
index 000000000000..e4fd8fd6fb57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs32.c
@@ -0,0 +1,19 @@
+/* smdrs32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smdrs32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smdrs32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t srdms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smdrs32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smdrs32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds.c
new file mode 100644
index 000000000000..4ced3400bbaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds.c
@@ -0,0 +1,19 @@
+/* smds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds32.c
new file mode 100644
index 000000000000..c14e265ba80b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds32.c
@@ -0,0 +1,19 @@
+/* smds32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smds32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smds32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smds32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smds32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin16.c
new file mode 100644
index 000000000000..7466c61a8d50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin16.c
@@ -0,0 +1,19 @@
+/* smin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nims (uint64_t ra, uint64_t rb)
+{
+  return __rv_smin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t nims_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin32.c
new file mode 100644
index 000000000000..52560fd6565b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin32.c
@@ -0,0 +1,19 @@
+/* smin32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nims (uint64_t ra, uint64_t rb)
+{
+  return __rv_smin32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t nims_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smin32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin8.c
new file mode 100644
index 000000000000..55c5c4712dfd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin8.c
@@ -0,0 +1,19 @@
+/* smin8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nims (uint64_t ra, uint64_t rb)
+{
+  return __rv_smin8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t nims_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_smin8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmul.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmul.c
new file mode 100644
index 000000000000..b65a3d3e9c65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmul.c
@@ -0,0 +1,13 @@
+/* smmul also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmul instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t lumms (int64_t ra, int64_t rb)
+{
+  return __rv_smmul (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmul" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmulu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmulu.c
new file mode 100644
index 000000000000..539883b33b68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmulu.c
@@ -0,0 +1,12 @@
+/* This is a test program for smmul.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u_lumms (int64_t ra, int64_t rb)
+{
+  return __rv_smmul_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmul.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwb.c
new file mode 100644
index 000000000000..6385c1976339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwb.c
@@ -0,0 +1,19 @@
+/* smmwb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwbu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwbu.c
new file mode 100644
index 000000000000..a5f69059d6f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwbu.c
@@ -0,0 +1,18 @@
+/* This is a test program for smmwbu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ubwmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwb_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ubwmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwb_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwt.c
new file mode 100644
index 000000000000..dc470241e550
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwt.c
@@ -0,0 +1,19 @@
+/* smmwt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwtu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwtu.c
new file mode 100644
index 000000000000..da0aedd609c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwtu.c
@@ -0,0 +1,18 @@
+/* This is a test program for smmwtu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t utwmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwt_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t utwmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwt_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslda.c
new file mode 100644
index 000000000000..484116863ed2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslda.c
@@ -0,0 +1,20 @@
+/* smslda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adlsms (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smslda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adlsms_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smslda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smslda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslxda.c
new file mode 100644
index 000000000000..32b946e13eca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslxda.c
@@ -0,0 +1,20 @@
+/* smslxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxlsms (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smslxda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlsms_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smslxda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smslxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smsr64.c
new file mode 100644
index 000000000000..9b60a892a4d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smsr64.c
@@ -0,0 +1,13 @@
+/* smsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t rsms (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_smsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt.c
new file mode 100644
index 000000000000..5bfafdf336dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt.c
@@ -0,0 +1,18 @@
+/* This is a test program for smtt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smtt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt32.c
new file mode 100644
index 000000000000..9bf98d31f6d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt32.c
@@ -0,0 +1,19 @@
+/* smtt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smtt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smtt32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ttms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smtt32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smtt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smulx.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smulx.c
new file mode 100644
index 000000000000..03a42888cd97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smulx.c
@@ -0,0 +1,57 @@
+/* smtt32 also appears on filename, so scan-assembler-times plus 1 */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zprv_zpsf -mabi=lp64d -O0" } */#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttms (uint32_t a, uint32_t b)
+{
+  return __rv_smul8 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ttms_v (int8x4_t a, int8x4_t b)
+{
+  return __rv_v_smul8 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint64_t ttmsx (uint32_t a, uint32_t b)
+{
+  return __rv_smulx8 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ttmsx_v (int8x4_t a, int8x4_t b)
+{
+  return __rv_v_smulx8 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint64_t ttms2 (uint32_t a, uint32_t b)
+{
+  return __rv_smul16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttms_v2 (int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smul16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint64_t xttms2 (uint32_t a, uint32_t b)
+{
+  return __rv_smulx16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttmsx_v2 (int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smulx16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "smul8" 2 } } */
+/* { dg-final { scan-assembler-times "smulx8" 2 } } */
+/* { dg-final { scan-assembler-times "smul16" 2 } } */
+/* { dg-final { scan-assembler-times "smulx16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds.c
new file mode 100644
index 000000000000..d9c9a6eaf690
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds.c
@@ -0,0 +1,19 @@
+/* smxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smxds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smxds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdxms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smxds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds32.c
new file mode 100644
index 000000000000..caccefe116d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds32.c
@@ -0,0 +1,19 @@
+/* smxds32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smxds32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smxds32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smxds32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smxds32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16.c
new file mode 100644
index 000000000000..7e98cd27525f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16.c
@@ -0,0 +1,19 @@
+/* sra16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ars_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16u.c
new file mode 100644
index 000000000000..be4490a4cdcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for sra16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u61ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t u61ars_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32.c
new file mode 100644
index 000000000000..56112451613a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32.c
@@ -0,0 +1,19 @@
+/* sra32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ars_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32u.c
new file mode 100644
index 000000000000..a40dbe37c955
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for sra32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra32_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u23ars_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra32_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16.c
new file mode 100644
index 000000000000..5c92f64832e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t iars (uint64_t ra)
+{
+  return __rv_sra16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x4_t iars_v (int16x4_t ra)
+{
+  return __rv_v_sra16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16u.c
new file mode 100644
index 000000000000..fe2a374d91f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u61iars (uint64_t ra)
+{
+  return __rv_sra16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x4_t u61iars_v (int16x4_t ra)
+{
+  return __rv_v_sra16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32.c
new file mode 100644
index 000000000000..e5654c9fd8bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t iars (uint64_t ra)
+{
+  return __rv_sra32 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int32x2_t iars_v (int32x2_t ra)
+{
+  return __rv_v_sra32 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32u.c
new file mode 100644
index 000000000000..26ec45373b6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23iars (uint64_t ra)
+{
+  return __rv_sra32_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u23iars_v (int32x2_t ra)
+{
+  return __rv_v_sra32_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sraiu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sraiu.c
new file mode 100644
index 000000000000..c037f7bddb7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sraiu.c
@@ -0,0 +1,12 @@
+/* This is a test program for srai.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t uiars (int64_t ra)
+{
+  return __rv_sra_u (ra, 8);
+}
+/* { dg-final { scan-assembler-times "srai.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srau.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srau.c
new file mode 100644
index 000000000000..f5df3067bc66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srau.c
@@ -0,0 +1,12 @@
+/* This is a test program for sra.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t uars (int64_t ra, uint32_t rb)
+{
+  return __rv_sra_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16.c
new file mode 100644
index 000000000000..8cbce03f4762
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16.c
@@ -0,0 +1,19 @@
+/* srl16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t lrs_v (uint16x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16u.c
new file mode 100644
index 000000000000..84f83af3241a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srl16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u_61lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t u_61lrs_v (uint16x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32.c
new file mode 100644
index 000000000000..fc3301e5ff72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32.c
@@ -0,0 +1,19 @@
+/* srl32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t lrs_v (uint32x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32u.c
new file mode 100644
index 000000000000..b2cdcdcb956d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srl32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl32_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t u23lrs_v (uint32x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl32_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16.c
new file mode 100644
index 000000000000..8adef29a0c2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16.c
@@ -0,0 +1,18 @@
+/* This is a test program for srli16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ilrs (uint64_t ra)
+{
+  return __rv_srl16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ilrs_v (uint16x4_t ra)
+{
+  return __rv_v_srl16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16u.c
new file mode 100644
index 000000000000..41753750bc33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for sril16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u_61ilrs (uint64_t ra)
+{
+  return __rv_srl16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t u_61ilrs_v (uint16x4_t ra)
+{
+  return __rv_v_srl16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32.c
new file mode 100644
index 000000000000..6c495f1b55a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32.c
@@ -0,0 +1,18 @@
+/* This is a test program for srli32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ilrs (uint64_t ra)
+{
+  return __rv_srl32 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ilrs_v (uint32x2_t ra)
+{
+  return __rv_v_srl32 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32u.c
new file mode 100644
index 000000000000..f35af1d7e975
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srli32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23ilrs (uint64_t ra)
+{
+  return __rv_srl32_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t u23ilrs_v (uint32x2_t ra)
+{
+  return __rv_v_srl32_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas16.c
new file mode 100644
index 000000000000..a8ce6e864707
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas16.c
@@ -0,0 +1,68 @@
+/* stas16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stas16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo21(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo31(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo8(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo9(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstas16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stas16" 12 } } */
+/* { dg-final { scan-assembler-times "rstas16" 4 } } */
+/* { dg-final { scan-assembler-times "urstas16" 2 } } */
+/* { dg-final { scan-assembler-times "kstas16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstas16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas32.c
new file mode 100644
index 000000000000..f105833d7206
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas32.c
@@ -0,0 +1,70 @@
+/* stas32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stas32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+typedef uint32x2_t uint32xN_t;
+typedef int32x2_t int32xN_t;
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo4(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ustas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo5(int32xN_t a, int32xN_t b) {
+  return __rv_v_sstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo6(int32xN_t a, int32xN_t b) {
+  return __rv_v_rstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo7(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_urstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo9(int32xN_t a, int32xN_t b) {
+  return __rv_v_kstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo11(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ukstas32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stas32" 12 } } */
+/* { dg-final { scan-assembler-times "rstas32" 4 } } */
+/* { dg-final { scan-assembler-times "urstas32" 2 } } */
+/* { dg-final { scan-assembler-times "kstas32" 4 } } */
+/* { dg-final { scan-assembler-times "ukstas32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa16.c
new file mode 100644
index 000000000000..f9d470df58f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa16.c
@@ -0,0 +1,68 @@
+/* stsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo9(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo11(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstsa16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stsa16" 12 } } */
+/* { dg-final { scan-assembler-times "rstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "urstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "kstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa32.c
new file mode 100644
index 000000000000..98a32e6d64bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa32.c
@@ -0,0 +1,70 @@
+/* stsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+typedef uint32x2_t uint32xN_t;
+typedef int32x2_t int32xN_t;
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo4(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ustsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo5(int32xN_t a, int32xN_t b) {
+  return __rv_v_sstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo6(int32xN_t a, int32xN_t b) {
+  return __rv_v_rstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo7(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_urstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo9(int32xN_t a, int32xN_t b) {
+  return __rv_v_kstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo11(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ukstsa32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stsa32" 12 } } */
+/* { dg-final { scan-assembler-times "rstsa32" 4 } } */
+/* { dg-final { scan-assembler-times "urstsa32" 2 } } */
+/* { dg-final { scan-assembler-times "kstsa32" 4 } } */
+/* { dg-final { scan-assembler-times "ukstsa32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub16.c
new file mode 100644
index 000000000000..f52ad51e9bf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub16.c
@@ -0,0 +1,25 @@
+/* sub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bus (uint64_t ra, uint64_t rb)
+{
+  return __rv_sub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t busu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_usub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t buss_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_ssub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub32.c
new file mode 100644
index 000000000000..1bef6603149e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub32.c
@@ -0,0 +1,25 @@
+/* sub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bus (uint64_t ra, uint64_t rb)
+{
+  return __rv_sub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t busu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_usub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t buss_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_ssub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub8.c
new file mode 100644
index 000000000000..b05bd891388f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub8.c
@@ -0,0 +1,25 @@
+/* sub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bus (uint64_t ra, uint64_t rb)
+{
+  return __rv_sub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t busu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_usub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t buss_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_ssub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd810.c
new file mode 100644
index 000000000000..27e2703ba20a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd810.c
@@ -0,0 +1,19 @@
+/* sunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd810 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd820.c
new file mode 100644
index 000000000000..fb017348a77c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd820.c
@@ -0,0 +1,19 @@
+/* sunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd820 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd830.c
new file mode 100644
index 000000000000..2814b8d30b0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd830.c
@@ -0,0 +1,19 @@
+/* sunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd830 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd831.c
new file mode 100644
index 000000000000..905c2a951389
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd831.c
@@ -0,0 +1,19 @@
+/* sunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd831 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd832.c
new file mode 100644
index 000000000000..bf4bcddb5ae3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd832.c
@@ -0,0 +1,19 @@
+/* sunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd832 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-swap16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-swap16.c
new file mode 100644
index 000000000000..4004b815a2c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-swap16.c
@@ -0,0 +1,17 @@
+/* This is a test program for swap16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t paws (uint64_t a)
+{
+  return __rv_swap16 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t paws_v (uint16x4_t a)
+{
+  return __rv_v_swap16 (a);
+}
+/* { dg-final { scan-assembler-times "pkbt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip16.c
new file mode 100644
index 000000000000..05d0a0c50b31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip16.c
@@ -0,0 +1,19 @@
+/* uclip16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uclip16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t pilcu (uint64_t ra)
+{
+  return __rv_uclip16 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t pilcu_v (int16x4_t ra)
+{
+  return __rv_v_uclip16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "uclip16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip32.c
new file mode 100644
index 000000000000..ef4e5693d6a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip32.c
@@ -0,0 +1,13 @@
+/* uclip32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t pilcu (int64_t ra)
+{
+  return __rv_uclip32 (ra, 5);
+}
+/* { dg-final { scan-assembler-times "uclip32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple16.c
new file mode 100644
index 000000000000..673aa4150532
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple16.c
@@ -0,0 +1,19 @@
+/* ucmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t elpmcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple8.c
new file mode 100644
index 000000000000..f4d4a98ad579
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple8.c
@@ -0,0 +1,19 @@
+/* ucmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t elpmcu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ucmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt16.c
new file mode 100644
index 000000000000..ca4c8db5b7f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt16.c
@@ -0,0 +1,19 @@
+/* ucmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t tlpmcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt8.c
new file mode 100644
index 000000000000..b3d35c26b4ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt8.c
@@ -0,0 +1,19 @@
+/* ucmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t tlpmcu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ucmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd16.c
new file mode 100644
index 000000000000..17480ec10e3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd16.c
@@ -0,0 +1,19 @@
+/* ukadd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ddaku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ukadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd32.c
new file mode 100644
index 000000000000..92d442be68c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd32.c
@@ -0,0 +1,19 @@
+/* ukadd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukadd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ddaku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ukadd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd64.c
new file mode 100644
index 000000000000..52353505cb98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd64.c
@@ -0,0 +1,13 @@
+/* ukadd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukadd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd8.c
new file mode 100644
index 000000000000..0942254f4eca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd8.c
@@ -0,0 +1,19 @@
+/* ukadd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t ddaku_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ukadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukaddh.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukaddh.c
new file mode 100644
index 000000000000..dde05aa8d89e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukaddh.c
@@ -0,0 +1,13 @@
+/* ukaddh also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukaddh instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint32_t hddak (uint16_t ra, uint16_t rb)
+{
+  return __rv_ukaddh (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukaddh" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukaddw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukaddw.c
new file mode 100644
index 000000000000..12928e650d7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukaddw.c
@@ -0,0 +1,13 @@
+/* ukaddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukaddw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t wddak (int32_t ra, int32_t rb)
+{
+  return __rv_ukaddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukaddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras16.c
new file mode 100644
index 000000000000..0ae424e61d92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras16.c
@@ -0,0 +1,19 @@
+/* ukcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t sarcku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ukcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras32.c
new file mode 100644
index 000000000000..0ace36560768
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras32.c
@@ -0,0 +1,19 @@
+/* ukcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t sarcku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ukcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa16.c
new file mode 100644
index 000000000000..fdee2d00d893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa16.c
@@ -0,0 +1,19 @@
+/* ukcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t asrcku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ukcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa32.c
new file mode 100644
index 000000000000..5cb7b2e73f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa32.c
@@ -0,0 +1,19 @@
+/* ukcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t asrcku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ukcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmar64.c
new file mode 100644
index 000000000000..603ae68c78ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmar64.c
@@ -0,0 +1,13 @@
+/* ukmar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukmar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ramku (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_ukmar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukmar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmsr64.c
new file mode 100644
index 000000000000..ff56edec0e5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmsr64.c
@@ -0,0 +1,13 @@
+/* ukmsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukmsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t rsmku (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_ukmsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukmsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub16.c
new file mode 100644
index 000000000000..05b9605f6b97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub16.c
@@ -0,0 +1,19 @@
+/* uksub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t busku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_uksub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub32.c
new file mode 100644
index 000000000000..27a112f655c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub32.c
@@ -0,0 +1,19 @@
+/* uksub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uksub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t busku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_uksub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub64.c
new file mode 100644
index 000000000000..59f9736f7b53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub64.c
@@ -0,0 +1,13 @@
+/* uksub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uksub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub8.c
new file mode 100644
index 000000000000..1b7f4d6d6d72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub8.c
@@ -0,0 +1,19 @@
+/* uksub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t busku_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_uksub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksubh.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksubh.c
new file mode 100644
index 000000000000..b2cb629a9bda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksubh.c
@@ -0,0 +1,13 @@
+/* uksubh also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uksubh instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint32_t hbusk (uint16_t ra, uint16_t rb)
+{
+  return __rv_uksubh (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksubh" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksubw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksubw.c
new file mode 100644
index 000000000000..f9021cf00795
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksubw.c
@@ -0,0 +1,13 @@
+/* uksubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uksubw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint32_t hbusk (uint32_t ra, uint32_t rb)
+{
+  return __rv_uksubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umar64.c
new file mode 100644
index 000000000000..d057cec333c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umar64.c
@@ -0,0 +1,13 @@
+/* umar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ramu (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_umar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "umar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax16.c
new file mode 100644
index 000000000000..a6ee2feffa9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax16.c
@@ -0,0 +1,19 @@
+/* umax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xamu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t xamu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_umax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax32.c
new file mode 100644
index 000000000000..f8aa8688e5ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax32.c
@@ -0,0 +1,19 @@
+/* umax32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xamu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umax32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t xamu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_umax32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax8.c
new file mode 100644
index 000000000000..f0ab97956a46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax8.c
@@ -0,0 +1,19 @@
+/* umax8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xamu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umax8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t xamu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_umax8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin16.c
new file mode 100644
index 000000000000..90429268ea98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin16.c
@@ -0,0 +1,19 @@
+/* umin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nimu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t nimu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_umin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin32.c
new file mode 100644
index 000000000000..908f0b2541f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin32.c
@@ -0,0 +1,19 @@
+/* umin32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nimu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umin32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t nimu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_umin32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin8.c
new file mode 100644
index 000000000000..93c22d612a2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin8.c
@@ -0,0 +1,19 @@
+/* umin8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nimu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umin8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t nimu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_umin8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umsr64.c
new file mode 100644
index 000000000000..262f636b7360
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umsr64.c
@@ -0,0 +1,13 @@
+/* umsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t rsmu (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_umsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "umsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd16.c
new file mode 100644
index 000000000000..e363f07d8f24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd16.c
@@ -0,0 +1,19 @@
+/* uradd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ddaru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_uradd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd32.c
new file mode 100644
index 000000000000..e6fe41fbc9da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd32.c
@@ -0,0 +1,19 @@
+/* uradd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ddaru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_uradd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd64.c
new file mode 100644
index 000000000000..7adc8bb1b202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd64.c
@@ -0,0 +1,13 @@
+/* radd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ddar (int64_t ra, int64_t rb)
+{
+  return __rv_radd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd8.c
new file mode 100644
index 000000000000..846fae2c049a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd8.c
@@ -0,0 +1,19 @@
+/* uradd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t ddaru_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_uradd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uraddw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uraddw.c
new file mode 100644
index 000000000000..90359456fa2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uraddw.c
@@ -0,0 +1,13 @@
+/* uraddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uraddw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t wddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uraddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uraddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras16.c
new file mode 100644
index 000000000000..8f699528deeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras16.c
@@ -0,0 +1,19 @@
+/* urcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t sarcru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_urcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras32.c
new file mode 100644
index 000000000000..7b7ac9b7281f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras32.c
@@ -0,0 +1,19 @@
+/* urcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t sarcru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_urcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa16.c
new file mode 100644
index 000000000000..fc82fa3ed6dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa16.c
@@ -0,0 +1,19 @@
+/* urcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcrsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t asrcru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_urcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa32.c
new file mode 100644
index 000000000000..078c2f93c82d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa32.c
@@ -0,0 +1,19 @@
+/* urcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t asrcru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_urcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub16.c
new file mode 100644
index 000000000000..07ad516a08c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub16.c
@@ -0,0 +1,19 @@
+/* ursub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t busru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ursub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub32.c
new file mode 100644
index 000000000000..e76640c3aa00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub32.c
@@ -0,0 +1,19 @@
+/* ursub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t busru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ursub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub64.c
new file mode 100644
index 000000000000..63596eab8021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub64.c
@@ -0,0 +1,13 @@
+/* ursub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub8.c
new file mode 100644
index 000000000000..79bdd1ce4e50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub8.c
@@ -0,0 +1,19 @@
+/* ursub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t busru_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ursub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursubw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursubw.c
new file mode 100644
index 000000000000..8e45b8c2b9fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursubw.c
@@ -0,0 +1,13 @@
+/* ursubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursubw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint32_t wbusru (uint32_t ra, uint32_t rb)
+{
+  return __rv_ursubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-wext.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-wext.c
new file mode 100644
index 000000000000..8ecff709e4d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-wext.c
@@ -0,0 +1,13 @@
+/* wext also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for wext instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t txew (uint64_t ra, uint32_t rb)
+{
+  return __rv_wext (ra, rb);
+}
+/* { dg-final { scan-assembler-times "wext" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zbpbo.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zbpbo.c
new file mode 100644
index 000000000000..3190ed8004d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zbpbo.c
@@ -0,0 +1,80 @@
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zbpbo_zpn_zpsf -mabi=lp64d -O0" } */#include <rvp_intrinsic.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2 (uintXLEN_t a, uintXLEN_t b, uintXLEN_t c)
+{
+  return __rv_cmix (a, b, c);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo3(uint32_t a, uint32_t b, uint32_t c)
+{
+  return __rv_fsrw (a, b, c);
+}
+
+static __attribute__ ((noinline))
+int32_t foo5(int32_t a, int32_t b)
+{
+  return __rv_max (a, b);
+}
+
+static __attribute__ ((noinline))
+int32_t foo6(int32_t a, int32_t b)
+{
+  return __rv_min (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo7(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_pack (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_packu (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo9(uintXLEN_t a)
+{
+  return __rv_rev (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a)
+{
+  return __rv_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo11(uint8xN_t a)
+{
+  return __rv_v_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo12(uintXLEN_t a)
+{
+  return __rv_swap8 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo13(uint8xN_t a)
+{
+  return __rv_v_swap8 (a);
+}
+
+/* { dg-final { scan-assembler-times "rev8.h" 4 } } */
+/* { dg-final { scan-assembler-times "rev" 5 } } */
+/* { dg-final { scan-assembler-times "pack" 2 } } */
+/* { dg-final { scan-assembler-times "packu" 1 } } */
+/* { dg-final { scan-assembler-times "fsrw" 1 } } */
+/* { dg-final { scan-assembler-times "min" 1 } } */
+/* { dg-final { scan-assembler-times "max" 1 } } */
+/* { dg-final { scan-assembler-times "cmix" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
+/* { dg-final { scan-assembler-times "maxw" 0 } } */
+/* { dg-final { scan-assembler-times "minw" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd810.c
new file mode 100644
index 000000000000..90db21e60810
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd810.c
@@ -0,0 +1,19 @@
+/* zunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd810 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd820.c
new file mode 100644
index 000000000000..ad09ee48935e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd820.c
@@ -0,0 +1,19 @@
+/* zunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd820 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd830.c
new file mode 100644
index 000000000000..47a2adee0df8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd830.c
@@ -0,0 +1,19 @@
+/* zunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd830 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd831.c
new file mode 100644
index 000000000000..b287a6760600
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd831.c
@@ -0,0 +1,19 @@
+/* zunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd831 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd832.c
new file mode 100644
index 000000000000..ffd109ee40f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd832.c
@@ -0,0 +1,19 @@
+/* zunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd832 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/rvp64.exp b/gcc/testsuite/gcc.target/riscv/rvp64_scan/rvp64.exp
new file mode 100644
index 000000000000..6e7aecba3c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/rvp64.exp
@@ -0,0 +1,42 @@
+
+# Copyright (C) 2017-2020 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
\ No newline at end of file