From da54bacbc6dbef0d3e024b9a28436c0862befde7 Mon Sep 17 00:00:00 2001
From: Lin Sinan <sinan@isrc.iscas.ac.cn>
Date: Sun, 31 Oct 2021 15:06:25 +0200
Subject: [PATCH] [testcases] add testcases

---
 .../riscv/rvp32_scan/builtin-rvp-add16.c      |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-add64.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-add8.c       |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-ave.c        |  16 +++
 .../riscv/rvp32_scan/builtin-rvp-bitrev.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-cmpeq16.c    |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-cmpeq8.c     |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-count.c      |  64 ++++++++++
 .../riscv/rvp32_scan/builtin-rvp-cras16.c     |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-crsa16.c     |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-insb.c       |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-kmar64.c     |  17 +++
 .../riscv/rvp32_scan/builtin-rvp-mfb.c        |  41 +++++++
 .../riscv/rvp32_scan/builtin-rvp-pbsad.c      |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-pbsada.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-pkbb16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-pkbt16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-pktb16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-pktt16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-radd16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-radd64.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-radd8.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-raddw.c      |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-rcras16.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-rcrsa16.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-rsub16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-rsub64.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-rsub8.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-rsubw.c      |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-sclip8.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-scmple16.c   |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-scmple8.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-scmplt16.c   |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-scmplt8.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sll16.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sll8.c       |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smal.c       |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smalda.c     |  22 ++++
 .../riscv/rvp32_scan/builtin-rvp-smaldrs.c    |  22 ++++
 .../riscv/rvp32_scan/builtin-rvp-smalds.c     |  22 ++++
 .../riscv/rvp32_scan/builtin-rvp-smalxda.c    |  22 ++++
 .../riscv/rvp32_scan/builtin-rvp-smalxds.c    |  22 ++++
 .../riscv/rvp32_scan/builtin-rvp-smar64.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-smax16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smbb.c       |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-smbt.c       |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-smdrs.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smds.c       |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smin16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smmul.c      |  14 +++
 .../riscv/rvp32_scan/builtin-rvp-smmulu.c     |  14 +++
 .../riscv/rvp32_scan/builtin-rvp-smmwb.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smmwbu.c     |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-smmwt.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smmwtu.c     |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-smslda.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smslxda.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smsr64.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-smtt.c       |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-smul16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smul8.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smulx16.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smulx8.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-smxds.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sra16.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sra16u.c     |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-sra8.c       |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sra8u.c      |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-srai16.c     |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-srai16u.c    |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-sraiu.c      |  14 +++
 .../riscv/rvp32_scan/builtin-rvp-srau.c       |  14 +++
 .../riscv/rvp32_scan/builtin-rvp-srl16.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-srl16u.c     |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-srl8.c       |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-srl8u.c      |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-srli16.c     |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-srli16u.c    |  20 +++
 .../riscv/rvp32_scan/builtin-rvp-stas16.c     |  70 +++++++++++
 .../riscv/rvp32_scan/builtin-rvp-stsa16.c     |  70 +++++++++++
 .../riscv/rvp32_scan/builtin-rvp-sub16.c      |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-sub64.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sub8.c       |  27 ++++
 .../riscv/rvp32_scan/builtin-rvp-sunpkd810.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sunpkd820.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sunpkd830.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sunpkd831.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-sunpkd832.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-swap8.c      |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-uclip8.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-ucmple16.c   |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-ucmple8.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-ucmplt16.c   |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-ucmplt8.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-umar64.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-umax16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-umin16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-umsr64.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-umul16.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-umul8.c      |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-umulx16.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-umulx8.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-uradd16.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-uradd64.c    |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-uradd8.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-uraddw.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-urcras16.c   |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-urcrsa16.c   |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-ursub16.c    |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-ursub64.c    |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-ursub8.c     |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-ursubw.c     |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-wext.c       |  15 +++
 .../riscv/rvp32_scan/builtin-rvp-zbpbo.c      | 115 ++++++++++++++++++
 .../riscv/rvp32_scan/builtin-rvp-zunpkd810.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-zunpkd820.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-zunpkd830.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-zunpkd831.c  |  21 ++++
 .../riscv/rvp32_scan/builtin-rvp-zunpkd832.c  |  21 ++++
 .../gcc.target/riscv/rvp32_scan/rvp32.exp     |  41 +++++++
 .../riscv/rvp64_scan/builtin-rvp64-add16.c    |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-add32.c    |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-add8.c     |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-bitrev.c   |  21 ++++
 .../riscv/rvp64_scan/builtin-rvp64-cmpeq16.c  |  23 ++++
 .../riscv/rvp64_scan/builtin-rvp64-cmpeq8.c   |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-count.c    |  72 +++++++++++
 .../riscv/rvp64_scan/builtin-rvp64-cras16.c   |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-cras32.c   |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-crsa16.c   |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-crsa32.c   |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-insb.c     |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-kabs16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kabs32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kabs8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kadd16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kadd32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kadd64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-kadd8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kaddh.c    |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-kaddw.c    |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-kcras16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kcras32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kcrsa16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kcrsa32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kdmbb.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kdmbb16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kdmbt.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kdmbt16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kdmtt.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kdmtt16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khm16.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khm8.c     |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmbb.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmbb16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmbt.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmbt16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmtt.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmtt16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmx16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-khmx8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmabb.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmabb32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmabt.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmabt32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmada.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmada32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmadrs.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmadrs32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmads.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmads32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmar64.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmatt.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmatt32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmaxda.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmaxda32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmaxds.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmaxds32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmda.c     |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmda32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmac.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmacu.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawb.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawb2.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawb2u.c |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawbu.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawt.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawt2.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawt2u.c |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmawtu.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmsb.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmsbu.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmwb2.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmwb2u.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmwt2.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmmwt2u.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmsda.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmsda32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmsr64.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmsxda.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmsxda32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmxda.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kmxda32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ksll.c     |  12 ++
 .../riscv/rvp64_scan/builtin-rvp64-ksll16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ksll32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kslli.c    |  12 ++
 .../riscv/rvp64_scan/builtin-rvp64-kslra16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kslra16u.c |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kslra32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-kslra32u.c |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-kslraw.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-kslrawu.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-ksub16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ksub32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ksub64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-ksub8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ksubh.c    |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-ksubw.c    |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-kwmmul.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-kwmmulu.c  |  12 ++
 .../riscv/rvp64_scan/builtin-rvp64-mfb.c      |  39 ++++++
 .../riscv/rvp64_scan/builtin-rvp64-pkbb16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-pkbt16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-pktb16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-pktt16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-radd16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-radd32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-radd64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-radd8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-raddw.c    |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-rcras16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-rcras32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-rcrsa16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-rcrsa32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-rsub16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-rsub32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-rsub64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-rsub8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-rsubw.c    |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-sclip16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-sclip32.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-scmple16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-scmple8.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-scmplt16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-scmplt8.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-sll16.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-sll32.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-slli32.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-smal.c     |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smalbb.c   |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smalbt.c   |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smalda.c   |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smaldrs.c  |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smalds.c   |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smaltt.c   |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smalxda.c  |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smalxds.c  |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smar64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-smax16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smax32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smax8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smbb.c     |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-smbb32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smbt.c     |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-smbt32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smdrs.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smdrs32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smds.c     |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smds32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smin16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smin32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smin8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smmul.c    |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-smmulu.c   |  12 ++
 .../riscv/rvp64_scan/builtin-rvp64-smmwb.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smmwbu.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-smmwt.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smmwtu.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-smslda.c   |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smslxda.c  |  20 +++
 .../riscv/rvp64_scan/builtin-rvp64-smsr64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-smtt.c     |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-smtt32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smulx.c    |  57 +++++++++
 .../riscv/rvp64_scan/builtin-rvp64-smxds.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-smxds32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-sra16.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-sra16u.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-sra32.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-sra32u.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srai16.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srai16u.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srai32.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srai32u.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-sraiu.c    |  12 ++
 .../riscv/rvp64_scan/builtin-rvp64-srau.c     |  12 ++
 .../riscv/rvp64_scan/builtin-rvp64-srl16.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-srl16u.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srl32.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-srl32u.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srli16.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srli16u.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srli32.c   |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-srli32u.c  |  18 +++
 .../riscv/rvp64_scan/builtin-rvp64-stas16.c   |  68 +++++++++++
 .../riscv/rvp64_scan/builtin-rvp64-stas32.c   |  70 +++++++++++
 .../riscv/rvp64_scan/builtin-rvp64-stsa16.c   |  68 +++++++++++
 .../riscv/rvp64_scan/builtin-rvp64-stsa32.c   |  70 +++++++++++
 .../riscv/rvp64_scan/builtin-rvp64-sub16.c    |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-sub32.c    |  25 ++++
 .../riscv/rvp64_scan/builtin-rvp64-sub8.c     |  25 ++++
 .../rvp64_scan/builtin-rvp64-sunpkd810.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-sunpkd820.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-sunpkd830.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-sunpkd831.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-sunpkd832.c      |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-swap16.c   |  17 +++
 .../riscv/rvp64_scan/builtin-rvp64-uclip16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-uclip32.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-ucmple16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ucmple8.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ucmplt16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ucmplt8.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukadd16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukadd32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukadd64.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-ukadd8.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukcras16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukcras32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukcrsa16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukcrsa32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ukmar64.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-ukmsr64.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-uksub16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-uksub32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-uksub64.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-uksub8.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-umar64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-umax16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-umax32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-umax8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-umin16.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-umin32.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-umin8.c    |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-umsr64.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-uradd16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-uradd32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-uradd64.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-uradd8.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-uraddw.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-urcras16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-urcras32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-urcrsa16.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-urcrsa32.c |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ursub16.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ursub32.c  |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ursub64.c  |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-ursub8.c   |  19 +++
 .../riscv/rvp64_scan/builtin-rvp64-ursubw.c   |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-wext.c     |  13 ++
 .../riscv/rvp64_scan/builtin-rvp64-zbpbo.c    |  80 ++++++++++++
 .../rvp64_scan/builtin-rvp64-zunpkd810.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-zunpkd820.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-zunpkd830.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-zunpkd831.c      |  19 +++
 .../rvp64_scan/builtin-rvp64-zunpkd832.c      |  19 +++
 .../gcc.target/riscv/rvp64_scan/rvp64.exp     |  42 +++++++
 368 files changed, 7627 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ave.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-bitrev.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-count.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cras16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-crsa16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-insb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-kmar64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mfb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsad.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsada.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbb16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbt16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktb16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktt16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-raddw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcras16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcrsa16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsubw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sclip8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smal.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalda.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smaldrs.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalds.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxda.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxds.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smar64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smax16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smdrs.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smds.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smin16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmul.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmulu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwb.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwbu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwtu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslda.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslxda.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smsr64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smtt.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smxds.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16u.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8u.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16u.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sraiu.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srau.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16u.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8u.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16u.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stas16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stsa16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd810.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd820.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd830.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd831.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd832.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-swap8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uclip8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umar64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umax16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umin16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umsr64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uraddw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcras16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcrsa16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursubw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-wext.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zbpbo.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd810.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd820.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd830.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd831.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd832.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp32_scan/rvp32.exp
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 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umsr64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uraddw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursubw.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-wext.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zbpbo.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd810.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd820.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd830.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd831.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd832.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvp64_scan/rvp64.exp

diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add16.c
new file mode 100644
index 000000000000..8f716ef323f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add16.c
@@ -0,0 +1,27 @@
+/* add16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dda (uint32_t ra, uint32_t rb)
+{
+  return __rv_add16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ddau_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_uadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t ddas_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_sadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add64.c
new file mode 100644
index 000000000000..9fe7e174ea0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add64.c
@@ -0,0 +1,21 @@
+/* add64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t ddas (int64_t ra, int64_t rb)
+{
+  return __rv_sadd64 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint64_t ddau (uint64_t ra, uint64_t rb)
+{
+  return __rv_uadd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add8.c
new file mode 100644
index 000000000000..0c885b007edf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-add8.c
@@ -0,0 +1,27 @@
+/* add8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dda (uint32_t ra, uint32_t rb)
+{
+  return __rv_add8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t ddau_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_uadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t ddas_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_sadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ave.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ave.c
new file mode 100644
index 000000000000..7a44534b602b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ave.c
@@ -0,0 +1,16 @@
+/* ave also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ave instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t eva (int32_t ra, int32_t rb)
+{
+  return __rv_ave (ra, rb);
+}
+
+/* { dg-final { scan-assembler-times "ave" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-bitrev.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-bitrev.c
new file mode 100644
index 000000000000..a49b1815af7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-bitrev.c
@@ -0,0 +1,15 @@
+/* bitrev also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for bitrev instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t vertib (uint32_t ra, uint32_t rb)
+{
+  return __rv_bitrev (ra, rb);
+}
+/* { dg-final { scan-assembler-times "bitrev" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq16.c
new file mode 100644
index 000000000000..5a9ca134a3f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq16.c
@@ -0,0 +1,27 @@
+/* cmpeq16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t qepmc (uint32_t ra, uint32_t rb)
+{
+  return __rv_cmpeq16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t qepmcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scmpeq16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t qepmcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucmpeq16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq8.c
new file mode 100644
index 000000000000..fb94d91386f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cmpeq8.c
@@ -0,0 +1,27 @@
+/* cmpeq8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t qepmc (uint32_t ra, uint32_t rb)
+{
+  return __rv_cmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t qepmcs_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_scmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t qepmcu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ucmpeq8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-count.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-count.c
new file mode 100644
index 000000000000..bb31693df292
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-count.c
@@ -0,0 +1,64 @@
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a) {
+  return __rv_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo1(uintXLEN_t a) {
+  return __rv_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a) {
+  return __rv_clrs32 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a) {
+  return __rv_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo4(uintXLEN_t a) {
+  return __rv_clz16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo5(uintXLEN_t a) {
+  return __rv_clz32 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo6(int8xN_t a) {
+  return __rv_v_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(int16xN_t a) {
+  return __rv_v_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo9(uint8xN_t a) {
+  return __rv_v_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo10(uint16xN_t a) {
+  return __rv_v_clz16 (a);
+}
+
+/* { dg-final { scan-assembler-times "clrs8" 2 } } */
+/* { dg-final { scan-assembler-times "clrs16" 2 } } */
+/* { dg-final { scan-assembler-times "clrs32" 1 } } */
+/* { dg-final { scan-assembler-times "clz8" 2 } } */
+/* { dg-final { scan-assembler-times "clz16" 2 } } */
+/* { dg-final { scan-assembler-times "clz32" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cras16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cras16.c
new file mode 100644
index 000000000000..96fa46f46fa0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-cras16.c
@@ -0,0 +1,27 @@
+/* cras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t sarc (uint32_t ra, uint32_t rb)
+{
+  return __rv_cras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t sarcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t sarcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cras16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-crsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-crsa16.c
new file mode 100644
index 000000000000..6c61da3423bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-crsa16.c
@@ -0,0 +1,27 @@
+/* crsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t asrc (uint32_t ra, uint32_t rb)
+{
+  return __rv_crsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t asrcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t asrcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "crsa16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-insb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-insb.c
new file mode 100644
index 000000000000..a320dd8ba142
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-insb.c
@@ -0,0 +1,15 @@
+/* insb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for insb instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bsni (uint32_t ra, uint32_t rb)
+{
+  return __rv_insb (ra, rb, 1);
+}
+/* { dg-final { scan-assembler-times "insb" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-kmar64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-kmar64.c
new file mode 100644
index 000000000000..5c13f44fa089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-kmar64.c
@@ -0,0 +1,17 @@
+/* kmar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmar64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t ramk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmar64 (rd, ra, rb);
+}
+
+/* { dg-final { scan-assembler-times "kmar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mfb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mfb.c
new file mode 100644
index 000000000000..d789d76e422d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-mfb.c
@@ -0,0 +1,41 @@
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+intXLEN_t foo(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+intXLEN_t foo1(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_umaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo3(int32xN_t t, int8xN_t a, int8xN_t b) {
+  return __rv_v_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo4(int32xN_t t, int8xN_t a, uint8xN_t b) {
+  return __rv_v_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo5(uint32xN_t t, uint8xN_t a, uint8xN_t b) {
+  return __rv_v_umaqa (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaqa.su" 2 } } */
+/* { dg-final { scan-assembler-times "smaqa" 4 } } */
+/* { dg-final { scan-assembler-times "umaqa" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsad.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsad.c
new file mode 100644
index 000000000000..3bd85099a7ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsad.c
@@ -0,0 +1,15 @@
+/* pbsad also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pbsad instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dasbp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pbsad (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pbsad" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsada.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsada.c
new file mode 100644
index 000000000000..bee02a4a7453
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pbsada.c
@@ -0,0 +1,15 @@
+/* pbsada also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pbsada instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t adasbp (uint32_t ra, uint32_t rb, uint32_t rc)
+{
+  return __rv_pbsada (ra, rb, rc);
+}
+/* { dg-final { scan-assembler-times "pbsada" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbb16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbb16.c
new file mode 100644
index 000000000000..e9bfc6eab57e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbb16.c
@@ -0,0 +1,21 @@
+/* pkbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbb16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bbkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pkbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t bbkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pkbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbt16.c
new file mode 100644
index 000000000000..3c894641a4a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pkbt16.c
@@ -0,0 +1,21 @@
+/* pkbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tbkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pkbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t tbkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pkbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktb16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktb16.c
new file mode 100644
index 000000000000..67f9e8d1c724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktb16.c
@@ -0,0 +1,21 @@
+/* pktb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktb16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t btkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pktb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t btkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pktb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktt16.c
new file mode 100644
index 000000000000..bcfacf164ac4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-pktt16.c
@@ -0,0 +1,21 @@
+/* pktt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ttkp (uint32_t ra, uint32_t rb)
+{
+  return __rv_pktt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ttkp_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_pktt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd16.c
new file mode 100644
index 000000000000..f1291380f4ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd16.c
@@ -0,0 +1,21 @@
+/* radd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddar (uint32_t ra, uint32_t rb)
+{
+  return __rv_radd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t ddar_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_radd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd64.c
new file mode 100644
index 000000000000..7cc82573eb71
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd64.c
@@ -0,0 +1,15 @@
+/* radd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t ddar (int64_t ra, int64_t rb)
+{
+  return __rv_radd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd8.c
new file mode 100644
index 000000000000..b0702a8b9d03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-radd8.c
@@ -0,0 +1,21 @@
+/* radd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddar (uint32_t ra, uint32_t rb)
+{
+  return __rv_radd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t ddar_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_radd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-raddw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-raddw.c
new file mode 100644
index 000000000000..339f9f1d1bae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-raddw.c
@@ -0,0 +1,15 @@
+/* raddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for raddw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t wddar (int32_t ra, int32_t rb)
+{
+  return __rv_raddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "raddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcras16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcras16.c
new file mode 100644
index 000000000000..12890d10d2c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcras16.c
@@ -0,0 +1,21 @@
+/* rcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcras16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t sarcr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t sarcr_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_rcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcrsa16.c
new file mode 100644
index 000000000000..6f0e8b601609
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rcrsa16.c
@@ -0,0 +1,21 @@
+/* rcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcrsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t asrcr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t asrcr_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_rcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub16.c
new file mode 100644
index 000000000000..5dfeb1c26fb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub16.c
@@ -0,0 +1,21 @@
+/* rsub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rsub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t busr_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_rsub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub64.c
new file mode 100644
index 000000000000..91a0b62f7a13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub64.c
@@ -0,0 +1,15 @@
+/* rsub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t busr (int64_t ra, int64_t rb)
+{
+  return __rv_rsub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub8.c
new file mode 100644
index 000000000000..6bdb2f9845dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsub8.c
@@ -0,0 +1,21 @@
+/* rsub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busr (uint32_t ra, uint32_t rb)
+{
+  return __rv_rsub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t busr_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_rsub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsubw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsubw.c
new file mode 100644
index 000000000000..aef6d0c2b7f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-rsubw.c
@@ -0,0 +1,15 @@
+/* rsubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsubw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t wbusr (int32_t ra, int32_t rb)
+{
+  return __rv_rsubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sclip8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sclip8.c
new file mode 100644
index 000000000000..62a1399257a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sclip8.c
@@ -0,0 +1,21 @@
+/* sclip8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t pilcs (int32_t ra)
+{
+  return __rv_sclip8 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+int8x4_t pilcs_v (int8x4_t ra)
+{
+  return __rv_v_sclip8 (ra, 3);
+}
+/* { dg-final { scan-assembler-times "sclip8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple16.c
new file mode 100644
index 000000000000..e9938af48c08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple16.c
@@ -0,0 +1,21 @@
+/* scmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t elpmcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple8.c
new file mode 100644
index 000000000000..9348df366007
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmple8.c
@@ -0,0 +1,21 @@
+/* scmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t elpmcs_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_scmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt16.c
new file mode 100644
index 000000000000..7a307cbe4735
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt16.c
@@ -0,0 +1,21 @@
+/* scmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t tlpmcs_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_scmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt8.c
new file mode 100644
index 000000000000..4b3ba41f530f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-scmplt8.c
@@ -0,0 +1,21 @@
+/* scmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcs (uint32_t ra, uint32_t rb)
+{
+  return __rv_scmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t tlpmcs_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_scmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll16.c
new file mode 100644
index 000000000000..1e2533d55daf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll16.c
@@ -0,0 +1,21 @@
+/* sll16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lls (uint32_t ra, uint32_t rb)
+{
+  return __rv_sll16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t lls_v (uint16x2_t ra, uint32_t rb)
+{
+  return __rv_v_sll16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll8.c
new file mode 100644
index 000000000000..091fe3432157
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sll8.c
@@ -0,0 +1,21 @@
+/* sll8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lls (uint32_t ra, uint32_t rb)
+{
+  return __rv_sll8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t lls_v (uint8x4_t ra, uint32_t rb)
+{
+  return __rv_v_sll8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smal.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smal.c
new file mode 100644
index 000000000000..7320da3157a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smal.c
@@ -0,0 +1,21 @@
+/* smal also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smal instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t lams (int64_t ra, uint32_t rb)
+{
+  return __rv_smal (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t lams_v (int64_t ra, int16x2_t rb)
+{
+  return __rv_v_smal (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smal" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalda.c
new file mode 100644
index 000000000000..c88764a3d893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalda.c
@@ -0,0 +1,22 @@
+/* smalda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smaldrs.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smaldrs.c
new file mode 100644
index 000000000000..43b1c7b8013a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smaldrs.c
@@ -0,0 +1,22 @@
+/* smaldrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smaldrs instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t srdlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smaldrs (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t srdlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smaldrs (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaldrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalds.c
new file mode 100644
index 000000000000..c64a910a8b11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalds.c
@@ -0,0 +1,22 @@
+/* smalds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t sdlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxda.c
new file mode 100644
index 000000000000..089f94dd5178
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxda.c
@@ -0,0 +1,22 @@
+/* smalxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adxlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalxda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalxda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxds.c
new file mode 100644
index 000000000000..d8b99073c3cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smalxds.c
@@ -0,0 +1,22 @@
+/* smalxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t sdxlams (int64_t t, uint32_t a, uint32_t b)
+{
+  return __rv_smalxds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxlams_v (int64_t t, int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smalxds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smar64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smar64.c
new file mode 100644
index 000000000000..ddb0731e045e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smar64.c
@@ -0,0 +1,15 @@
+/* smar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smar64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t rams (int64_t t, int a, int b)
+{
+  return __rv_smar64 (t, a, b);
+}
+/* { dg-final { scan-assembler-times "smar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smax16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smax16.c
new file mode 100644
index 000000000000..cbaf0ce8a6ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smax16.c
@@ -0,0 +1,21 @@
+/* smax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t xams (uint32_t ra, uint32_t rb)
+{
+  return __rv_smax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t xams_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbb.c
new file mode 100644
index 000000000000..03ef38603d06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbb.c
@@ -0,0 +1,20 @@
+/* This is a test program for smbb instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t bbms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int bbms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbb16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbt.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbt.c
new file mode 100644
index 000000000000..bd958da9f13a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smbt.c
@@ -0,0 +1,20 @@
+/* This is a test program for smbt instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t tbms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t tbms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smdrs.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smdrs.c
new file mode 100644
index 000000000000..eb2b02d331aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smdrs.c
@@ -0,0 +1,21 @@
+/* smdrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smdrs instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t srdms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smdrs (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t srdms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smdrs (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smdrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smds.c
new file mode 100644
index 000000000000..61b58e938f24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smds.c
@@ -0,0 +1,21 @@
+/* smds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t sdms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t sdms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smin16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smin16.c
new file mode 100644
index 000000000000..eaecf26d4f1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smin16.c
@@ -0,0 +1,21 @@
+/* smin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t nims (uint32_t ra, uint32_t rb)
+{
+  return __rv_smin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t nims_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmul.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmul.c
new file mode 100644
index 000000000000..8e8b62b2600e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmul.c
@@ -0,0 +1,14 @@
+/* This is a test program for smmul instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t lumms (int32_t ra, int32_t rb)
+{
+  return __rv_smmul (ra, rb);
+}
+/* { dg-final { scan-assembler-times "mulh" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmulu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmulu.c
new file mode 100644
index 000000000000..09771c6f61ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmulu.c
@@ -0,0 +1,14 @@
+/* This is a test program for smmul.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t u_lumms (int32_t ra, int32_t rb)
+{
+  return __rv_smmul_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmul.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwb.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwb.c
new file mode 100644
index 000000000000..28cde8686c53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwb.c
@@ -0,0 +1,21 @@
+/* smmwb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwb instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t bwmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t bwmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwbu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwbu.c
new file mode 100644
index 000000000000..1d36dbbf03b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwbu.c
@@ -0,0 +1,20 @@
+/* This is a test program for smmwb.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t u_bwmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwb_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t u_bwmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwb_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwt.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwt.c
new file mode 100644
index 000000000000..47d5d19ffb7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwt.c
@@ -0,0 +1,21 @@
+/* smmwt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwt instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t twmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t twmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwtu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwtu.c
new file mode 100644
index 000000000000..9ac2464cefc9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smmwtu.c
@@ -0,0 +1,20 @@
+/* This is a test program for smmwt.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t u_twmms (int32_t ra, uint32_t rb)
+{
+  return __rv_smmwt_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t u_twmms_v (int32_t ra, int16x2_t rb)
+{
+  return __rv_v_smmwt_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslda.c
new file mode 100644
index 000000000000..0d49c7cb08ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslda.c
@@ -0,0 +1,21 @@
+/* smslda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adlsms (int64_t rt, uint32_t ra, uint32_t rb)
+{
+  return __rv_smslda (rt, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adlsms_v (int64_t rt, int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smslda (rt, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smslda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslxda.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslxda.c
new file mode 100644
index 000000000000..a5d3a457e69e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smslxda.c
@@ -0,0 +1,21 @@
+/* smslxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslxda instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t adxlsms (int64_t rt, uint32_t ra, uint32_t rb)
+{
+  return __rv_smslxda (rt, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlsms_v (int64_t rt, int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smslxda (rt, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smslxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smsr64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smsr64.c
new file mode 100644
index 000000000000..778f89d11880
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smsr64.c
@@ -0,0 +1,15 @@
+/* smsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smsr64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t rsms (int64_t t, int a, int b)
+{
+  return __rv_smsr64 (t, a, b);
+}
+/* { dg-final { scan-assembler-times "smsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smtt.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smtt.c
new file mode 100644
index 000000000000..a5ccf2727466
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smtt.c
@@ -0,0 +1,20 @@
+/* This is a test program for smtt instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t ttms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t ttms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smtt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul16.c
new file mode 100644
index 000000000000..f3166094c4ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul16.c
@@ -0,0 +1,21 @@
+/* smul16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smul16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smul16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t lums_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smul16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smul16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul8.c
new file mode 100644
index 000000000000..1e167edc844b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smul8.c
@@ -0,0 +1,21 @@
+/* smul8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smul8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smul8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t lums_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_smul8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smul8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx16.c
new file mode 100644
index 000000000000..f27a4df56bf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx16.c
@@ -0,0 +1,21 @@
+/* smulx16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smulx16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smulx16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t xlums_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smulx16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smulx16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx8.c
new file mode 100644
index 000000000000..5fceea0541e7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smulx8.c
@@ -0,0 +1,21 @@
+/* smulx8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smulx8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlums (uint32_t ra, uint32_t rb)
+{
+  return __rv_smulx8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t xlums_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_smulx8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smulx8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smxds.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smxds.c
new file mode 100644
index 000000000000..ac787d929e11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-smxds.c
@@ -0,0 +1,21 @@
+/* smxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smxds instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int32_t sdxms (uint32_t ra, uint32_t rb)
+{
+  return __rv_smxds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t sdxms_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_smxds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16.c
new file mode 100644
index 000000000000..5b25b3ab3be6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16.c
@@ -0,0 +1,21 @@
+/* sra16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t ars_v (int16x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16u.c
new file mode 100644
index 000000000000..e3d871839860
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for sra16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u61ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t u61ars_v (int16x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8.c
new file mode 100644
index 000000000000..acf3bc380767
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8.c
@@ -0,0 +1,21 @@
+/* sra8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t ars_v (int8x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8u.c
new file mode 100644
index 000000000000..f32b8d6a7f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sra8u.c
@@ -0,0 +1,20 @@
+/* This is a test program for sra8.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u8ars (uint32_t ra, uint32_t rb)
+{
+  return __rv_sra8_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t u8ars_v (int8x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra8_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra8.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16.c
new file mode 100644
index 000000000000..b4bbb2e4fb4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16.c
@@ -0,0 +1,20 @@
+/* This is a test program for srai16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t iars (uint32_t ra)
+{
+  return __rv_sra16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x2_t iars_v (int16x2_t ra)
+{
+  return __rv_v_sra16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16u.c
new file mode 100644
index 000000000000..8ff72c1e7bea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srai16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for srai16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u61iars (uint32_t ra)
+{
+  return __rv_sra16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x2_t u61iars_v (int16x2_t ra)
+{
+  return __rv_v_sra16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sraiu.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sraiu.c
new file mode 100644
index 000000000000..712ce0448f4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sraiu.c
@@ -0,0 +1,14 @@
+/* This is a test program for srai.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int uiars (int ra)
+{
+  return __rv_sra_u (ra, 8);
+}
+/* { dg-final { scan-assembler-times "srai.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srau.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srau.c
new file mode 100644
index 000000000000..22c931105386
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srau.c
@@ -0,0 +1,14 @@
+/* This is a test program for sra.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int uars (int ra, uint32_t rb)
+{
+  return __rv_sra_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16.c
new file mode 100644
index 000000000000..9ed1ee3eeafa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16.c
@@ -0,0 +1,21 @@
+/* srl16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t lrs_v (uint16x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16u.c
new file mode 100644
index 000000000000..5275d229ae47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for srl16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u_61lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t u_61lrs_v (uint16x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8.c
new file mode 100644
index 000000000000..556f98d396a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8.c
@@ -0,0 +1,21 @@
+/* srl8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t lrs_v (uint8x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8u.c
new file mode 100644
index 000000000000..344db2c1a9d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srl8u.c
@@ -0,0 +1,20 @@
+/* This is a test program for srl8.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u_8lrs (uint32_t ra, uint32_t rb)
+{
+  return __rv_srl8_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t u_8lrs_v (uint8x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl8_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl8.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16.c
new file mode 100644
index 000000000000..23c0dfcae6cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16.c
@@ -0,0 +1,20 @@
+/* This is a test program for srli16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ilrs (uint32_t ra)
+{
+  return __rv_srl16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ilrs_v (uint16x2_t ra)
+{
+  return __rv_v_srl16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16u.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16u.c
new file mode 100644
index 000000000000..9b95bfd8d962
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-srli16u.c
@@ -0,0 +1,20 @@
+/* This is a test program for sril16.u instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t u_61ilrs (uint32_t ra)
+{
+  return __rv_srl16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t u_61ilrs_v (uint16x2_t ra)
+{
+  return __rv_v_srl16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stas16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stas16.c
new file mode 100644
index 000000000000..93a5b68b5087
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stas16.c
@@ -0,0 +1,70 @@
+/* stas16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stas16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo9(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo11(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstas16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stas16" 12 } } */
+/* { dg-final { scan-assembler-times "rstas16" 4 } } */
+/* { dg-final { scan-assembler-times "urstas16" 2 } } */
+/* { dg-final { scan-assembler-times "kstas16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstas16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stsa16.c
new file mode 100644
index 000000000000..8fc3a9073977
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-stsa16.c
@@ -0,0 +1,70 @@
+/* stsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo9(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo11(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstsa16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stsa16" 12 } } */
+/* { dg-final { scan-assembler-times "rstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "urstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "kstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub16.c
new file mode 100644
index 000000000000..740650a1a585
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub16.c
@@ -0,0 +1,27 @@
+/* sub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bus (uint32_t ra, uint32_t rb)
+{
+  return __rv_sub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t busu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_usub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x2_t buss_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_ssub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub64.c
new file mode 100644
index 000000000000..a99174b0f630
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub64.c
@@ -0,0 +1,21 @@
+/* sub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+int64_t buss (int64_t ra, int64_t rb)
+{
+  return __rv_ssub64 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint64_t busu (uint64_t ra, uint64_t rb)
+{
+  return __rv_usub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub8.c
new file mode 100644
index 000000000000..5e40e86d0227
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sub8.c
@@ -0,0 +1,27 @@
+/* sub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t bus (uint32_t ra, uint32_t rb)
+{
+  return __rv_sub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t busu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_usub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x4_t buss_v (int8x4_t ra, int8x4_t rb)
+{
+  return __rv_v_ssub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd810.c
new file mode 100644
index 000000000000..d1475b13fab9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd810.c
@@ -0,0 +1,21 @@
+/* sunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd810 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd820.c
new file mode 100644
index 000000000000..481d5507fd6a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd820.c
@@ -0,0 +1,21 @@
+/* sunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd820 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd830.c
new file mode 100644
index 000000000000..90f1b80ad899
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd830.c
@@ -0,0 +1,21 @@
+/* sunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd830 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd831.c
new file mode 100644
index 000000000000..cae3ece3e948
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd831.c
@@ -0,0 +1,21 @@
+/* sunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd831 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd832.c
new file mode 100644
index 000000000000..6a138fd6a1a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-sunpkd832.c
@@ -0,0 +1,21 @@
+/* sunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd832 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnus (uint32_t a)
+{
+  return __rv_sunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+int16x2_t dkpnus_v (int8x4_t a)
+{
+  return __rv_v_sunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-swap8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-swap8.c
new file mode 100644
index 000000000000..53760554de42
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-swap8.c
@@ -0,0 +1,15 @@
+/* swap8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for wsbh instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t paws (uint32_t a)
+{
+  return __rv_swap8 (a);
+}
+/* { dg-final { scan-assembler-times "swap8" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uclip8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uclip8.c
new file mode 100644
index 000000000000..2afc1624fd0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uclip8.c
@@ -0,0 +1,21 @@
+/* uclip8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t pilcu (uint32_t ra)
+{
+  return __rv_uclip8 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t pilcu_v (int8x4_t ra)
+{
+  return __rv_v_uclip8 (ra, 3);
+}
+/* { dg-final { scan-assembler-times "uclip8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple16.c
new file mode 100644
index 000000000000..087ed5a78920
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple16.c
@@ -0,0 +1,21 @@
+/* ucmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t elpmcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple8.c
new file mode 100644
index 000000000000..2e36728f2e5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmple8.c
@@ -0,0 +1,21 @@
+/* ucmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t elpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t elpmcu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ucmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt16.c
new file mode 100644
index 000000000000..baaa1fc3ed52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt16.c
@@ -0,0 +1,21 @@
+/* ucmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t tlpmcu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ucmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt8.c
new file mode 100644
index 000000000000..bef1f1a80afd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ucmplt8.c
@@ -0,0 +1,21 @@
+/* ucmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t tlpmcu (uint32_t ra, uint32_t rb)
+{
+  return __rv_ucmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t tlpmcu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ucmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umar64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umar64.c
new file mode 100644
index 000000000000..6ce1a370b685
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umar64.c
@@ -0,0 +1,15 @@
+/* umar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umar64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t ramu (uint64_t t,unsigned int a,unsigned int b)
+{
+  return __rv_umar64 (t, a, b);
+}
+/* { dg-final { scan-assembler-times "umar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umax16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umax16.c
new file mode 100644
index 000000000000..f71fc727d3a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umax16.c
@@ -0,0 +1,21 @@
+/* umax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t xamu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t xamu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umin16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umin16.c
new file mode 100644
index 000000000000..54cb57aa218d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umin16.c
@@ -0,0 +1,21 @@
+/* umin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t nimu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t nimu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umsr64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umsr64.c
new file mode 100644
index 000000000000..41967d13a0ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umsr64.c
@@ -0,0 +1,15 @@
+/* umsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umsr64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t rsmu (uint64_t t, unsigned int a, unsigned int b)
+{
+  return __rv_umsr64 (t, a, b);
+}
+/* { dg-final { scan-assembler-times "umsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul16.c
new file mode 100644
index 000000000000..f41e7c2347c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul16.c
@@ -0,0 +1,21 @@
+/* umul16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umul16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umul16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t lumu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umul16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umul16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul8.c
new file mode 100644
index 000000000000..bf8ac795ceae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umul8.c
@@ -0,0 +1,21 @@
+/* umul8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umul8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t lumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umul8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t lumu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_umul8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umul8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx16.c
new file mode 100644
index 000000000000..0398ed3c5b88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx16.c
@@ -0,0 +1,21 @@
+/* umulx16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umulx16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umulx16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t xlumu_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_umulx16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umulx16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx8.c
new file mode 100644
index 000000000000..447bb13ea57a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-umulx8.c
@@ -0,0 +1,21 @@
+/* umulx8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umulx8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t xlumu (uint32_t ra, uint32_t rb)
+{
+  return __rv_umulx8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t xlumu_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_umulx8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umulx8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd16.c
new file mode 100644
index 000000000000..5e015527033a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd16.c
@@ -0,0 +1,21 @@
+/* uradd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uradd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t ddaru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_uradd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd64.c
new file mode 100644
index 000000000000..6abb4a57a6dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd64.c
@@ -0,0 +1,15 @@
+/* uradd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd8.c
new file mode 100644
index 000000000000..19536d11941e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uradd8.c
@@ -0,0 +1,21 @@
+/* uradd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t ddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uradd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t ddaru_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_uradd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uraddw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uraddw.c
new file mode 100644
index 000000000000..40680db9e0a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-uraddw.c
@@ -0,0 +1,15 @@
+/* uraddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uraddw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t wddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uraddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uraddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcras16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcras16.c
new file mode 100644
index 000000000000..7995e3e4cb56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcras16.c
@@ -0,0 +1,21 @@
+/* urcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcras16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t sarcru (uint32_t ra, uint32_t rb)
+{
+  return __rv_urcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t sarcru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_urcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcrsa16.c
new file mode 100644
index 000000000000..9fae75c5e031
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-urcrsa16.c
@@ -0,0 +1,21 @@
+/* urcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcrsa16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t asrcru (uint32_t ra, uint32_t rb)
+{
+  return __rv_urcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t asrcru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_urcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub16.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub16.c
new file mode 100644
index 000000000000..1edc0fdf23ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub16.c
@@ -0,0 +1,21 @@
+/* ursub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub16 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busru (uint32_t ra, uint32_t rb)
+{
+  return __rv_ursub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t busru_v (uint16x2_t ra, uint16x2_t rb)
+{
+  return __rv_v_ursub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub64.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub64.c
new file mode 100644
index 000000000000..44691be66492
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub64.c
@@ -0,0 +1,15 @@
+/* ursub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub64 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub8.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub8.c
new file mode 100644
index 000000000000..da5a26336c7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursub8.c
@@ -0,0 +1,21 @@
+/* ursub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub8 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t busru (uint32_t ra, uint32_t rb)
+{
+  return __rv_ursub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x4_t busru_v (uint8x4_t ra, uint8x4_t rb)
+{
+  return __rv_v_ursub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursubw.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursubw.c
new file mode 100644
index 000000000000..a306cadf95db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-ursubw.c
@@ -0,0 +1,15 @@
+/* ursubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursubw instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t wbusru (unsigned int ra,unsigned int rb)
+{
+  return __rv_ursubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-wext.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-wext.c
new file mode 100644
index 000000000000..dc5cc8e83665
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-wext.c
@@ -0,0 +1,15 @@
+/* wext also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for wext instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t txew (int64_t ra, uint32_t rb)
+{
+  return __rv_wext (ra, rb);
+}
+/* { dg-final { scan-assembler-times "wext" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zbpbo.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zbpbo.c
new file mode 100644
index 000000000000..66bfba7f4df9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zbpbo.c
@@ -0,0 +1,115 @@
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zbpbo_zpn_zpsf -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t foo (uint32_t a)
+{
+  return __rv_clz (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2 (uintXLEN_t a, uintXLEN_t b, uintXLEN_t c)
+{
+  return __rv_cmix (a, b, c);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo3(uint32_t a, uint32_t b, uint32_t c)
+{
+  return __rv_fsr (a, b, c);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo4(uint32_t a, uint32_t b)
+{
+  return __rv_fsr (a, 1, b);
+}
+
+static __attribute__ ((noinline))
+int32_t foo5(int32_t a, int32_t b)
+{
+  return __rv_max (a, b);
+}
+
+static __attribute__ ((noinline))
+int32_t foo6(int32_t a, int32_t b)
+{
+  return __rv_min (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo7(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_pack (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_packu (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo9(uintXLEN_t a)
+{
+  return __rv_rev (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a)
+{
+  return __rv_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo11(uint8xN_t a)
+{
+  return __rv_v_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo12(uintXLEN_t a)
+{
+  return __rv_swap8 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo13(uint8xN_t a)
+{
+  return __rv_v_swap8 (a);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo14 (uint32_t ra, uint32_t rb)
+{
+  return __rv_pkbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo15 (uint32_t ra, uint32_t rb)
+{
+  return __rv_pktt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo18 (uint32_t a)
+{
+  return __rv_clz32 (a);
+}
+/* { dg-final { scan-assembler-times "rev8.h" 4 } } */
+/* { dg-final { scan-assembler-times "rev" 5 } } */
+/* { dg-final { scan-assembler-times "pack" 4 } } */
+/* { dg-final { scan-assembler-times "packu" 2 } } */
+/* { dg-final { scan-assembler-times "min" 1 } } */
+/* { dg-final { scan-assembler-times "max" 1 } } */
+/* { dg-final { scan-assembler-times "fsr" 2 } } */
+/* { dg-final { scan-assembler-times "fsri" 1 } } */
+/* { dg-final { scan-assembler-times "cmix" 1 } } */
+/* { dg-final { scan-assembler-times "clz" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
+/* { dg-final { scan-assembler-times "maxw" 0 } } */
+/* { dg-final { scan-assembler-times "minw" 0 } } */
+/* { dg-final { scan-assembler-times "clz32" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd810.c
new file mode 100644
index 000000000000..f3b98d96214f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd810.c
@@ -0,0 +1,21 @@
+/* zunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd810 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd820.c
new file mode 100644
index 000000000000..6faade029280
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd820.c
@@ -0,0 +1,21 @@
+/* zunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd820 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd830.c
new file mode 100644
index 000000000000..cd4f65fa6d66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd830.c
@@ -0,0 +1,21 @@
+/* zunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd830 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd831.c
new file mode 100644
index 000000000000..a95be4bd451c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd831.c
@@ -0,0 +1,21 @@
+/* zunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd831 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd832.c
new file mode 100644
index 000000000000..147a40d32420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/builtin-rvp-zunpkd832.c
@@ -0,0 +1,21 @@
+/* zunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd832 instruction.  */
+/* { dg-do compile { target riscv32*-*-* } } */
+/* { dg-options "-march=rv32gc_zpn -mabi=ilp32d -O0" } */
+
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uint32_t dkpnuz (uint32_t a)
+{
+  return __rv_zunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x2_t dkpnuz_v (uint8x4_t a)
+{
+  return __rv_v_zunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp32_scan/rvp32.exp b/gcc/testsuite/gcc.target/riscv/rvp32_scan/rvp32.exp
new file mode 100644
index 000000000000..13aa2dd52ca8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp32_scan/rvp32.exp
@@ -0,0 +1,41 @@
+# Copyright (C) 2017-2020 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv32*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add16.c
new file mode 100644
index 000000000000..a9830bb27e4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add16.c
@@ -0,0 +1,25 @@
+/* add16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dda (uint64_t ra, uint64_t rb)
+{
+  return __rv_add16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ddau_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_uadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ddas_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_sadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add32.c
new file mode 100644
index 000000000000..834d4635c415
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add32.c
@@ -0,0 +1,25 @@
+/* add32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dda (uint64_t ra, uint64_t rb)
+{
+  return __rv_add32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ddau_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_uadd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ddas_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_sadd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add8.c
new file mode 100644
index 000000000000..628b2fd97fc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-add8.c
@@ -0,0 +1,25 @@
+/* add8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dda (uint64_t ra, uint64_t rb)
+{
+  return __rv_add8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t ddau_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_uadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t ddas_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_sadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "add8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-bitrev.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-bitrev.c
new file mode 100644
index 000000000000..76d535df3113
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-bitrev.c
@@ -0,0 +1,21 @@
+/* bitrev also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for bitrev instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t vertib (uint64_t ra, uint32_t rb)
+{
+  return __rv_bitrev (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint64_t ivertib (uint64_t ra)
+{
+  return __rv_bitrev (ra, 3);
+}
+
+/* { dg-final { scan-assembler-times "bitrev" 3 } } */
+/* { dg-final { scan-assembler-times "bitrevi" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq16.c
new file mode 100644
index 000000000000..67b1b14620de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq16.c
@@ -0,0 +1,23 @@
+/* cmpeq16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t qepmc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cmpeq16 (ra, rb);
+}
+static __attribute__ ((noinline))
+uint16x4_t qepmcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scmpeq16 (ra, rb);
+}
+static __attribute__ ((noinline))
+uint16x4_t qepmcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucmpeq16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq8.c
new file mode 100644
index 000000000000..77385b95cd40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cmpeq8.c
@@ -0,0 +1,25 @@
+/* cmpeq8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cmpeq8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t qepmc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t qepmcs_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_scmpeq8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t qepmcu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ucmpeq8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cmpeq8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-count.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-count.c
new file mode 100644
index 000000000000..3027afa752f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-count.c
@@ -0,0 +1,72 @@
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a) {
+  return __rv_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo1(uintXLEN_t a) {
+  return __rv_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a) {
+  return __rv_clrs32 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a) {
+  return __rv_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo4(uintXLEN_t a) {
+  return __rv_clz16 (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo5(uintXLEN_t a) {
+  return __rv_clz32 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo6(int8xN_t a) {
+  return __rv_v_clrs8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(int16xN_t a) {
+  return __rv_v_clrs16 (a);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t foo8(int32x2_t a) {
+  return __rv_v_clrs32 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo9(uint8xN_t a) {
+  return __rv_v_clz8 (a);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo10(uint16xN_t a) {
+  return __rv_v_clz16 (a);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t foo11(uint32x2_t a) {
+  return __rv_v_clz32 (a);
+}
+
+/* { dg-final { scan-assembler-times "clrs8" 2 } } */
+/* { dg-final { scan-assembler-times "clrs16" 2 } } */
+/* { dg-final { scan-assembler-times "clrs32" 2 } } */
+/* { dg-final { scan-assembler-times "clz8" 2 } } */
+/* { dg-final { scan-assembler-times "clz16" 2 } } */
+/* { dg-final { scan-assembler-times "clz32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras16.c
new file mode 100644
index 000000000000..af89a5edf420
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras16.c
@@ -0,0 +1,25 @@
+/* cras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t sarcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sarcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cras16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras32.c
new file mode 100644
index 000000000000..01cfbb00beab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-cras32.c
@@ -0,0 +1,25 @@
+/* cras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarc (uint64_t ra, uint64_t rb)
+{
+  return __rv_cras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t sarcu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ucras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sarcs_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_scras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "cras32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa16.c
new file mode 100644
index 000000000000..8b2e963b459b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa16.c
@@ -0,0 +1,25 @@
+/* crsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrc (uint64_t ra, uint64_t rb)
+{
+  return __rv_crsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t asrcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t asrcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "crsa16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa32.c
new file mode 100644
index 000000000000..e021878c9c11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-crsa32.c
@@ -0,0 +1,25 @@
+/* crsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrc (uint64_t ra, uint64_t rb)
+{
+  return __rv_crsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t asrcu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ucrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t asrcs_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_scrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "crsa32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-insb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-insb.c
new file mode 100644
index 000000000000..e6c8622bf3e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-insb.c
@@ -0,0 +1,13 @@
+/* insb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for insb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bsni (uint64_t ra, uint32_t rb)
+{
+  return __rv_insb (ra, rb, 1);
+}
+/* { dg-final { scan-assembler-times "insb" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs16.c
new file mode 100644
index 000000000000..01c1c830ab43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs16.c
@@ -0,0 +1,19 @@
+/* kabs16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kabs16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sbak (uint64_t ra)
+{
+  return __rv_kabs16 (ra);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sbak_v (int16x4_t ra)
+{
+  return __rv_v_kabs16 (ra);
+}
+/* { dg-final { scan-assembler-times "kabs16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs32.c
new file mode 100644
index 000000000000..04320936fda0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs32.c
@@ -0,0 +1,19 @@
+/* kabs32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kabs32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sbak (uint64_t ra)
+{
+  return __rv_kabs32 (ra);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sbak_v (int32x2_t ra)
+{
+  return __rv_v_kabs32 (ra);
+}
+/* { dg-final { scan-assembler-times "kabs32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs8.c
new file mode 100644
index 000000000000..20c48d185f98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kabs8.c
@@ -0,0 +1,19 @@
+/* kabs8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kabs8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sbak (uint64_t ra)
+{
+  return __rv_kabs8 (ra);
+}
+
+static __attribute__ ((noinline))
+int8x8_t sbak_v (int8x8_t ra)
+{
+  return __rv_v_kabs8 (ra);
+}
+/* { dg-final { scan-assembler-times "kabs8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd16.c
new file mode 100644
index 000000000000..ad6a2bcdbf69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd16.c
@@ -0,0 +1,19 @@
+/* kadd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddak (uint64_t ra, uint64_t rb)
+{
+  return __rv_kadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ddak_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd32.c
new file mode 100644
index 000000000000..bb7179c25150
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd32.c
@@ -0,0 +1,19 @@
+/* kadd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kadd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddak (uint64_t ra, uint64_t rb)
+{
+  return __rv_kadd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ddak_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kadd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd64.c
new file mode 100644
index 000000000000..1a623aa7bfb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd64.c
@@ -0,0 +1,13 @@
+/* kadd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kadd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ddak (int64_t ra, int64_t rb)
+{
+  return __rv_kadd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd8.c
new file mode 100644
index 000000000000..e19d031e0dbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kadd8.c
@@ -0,0 +1,19 @@
+/* kadd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddak (uint64_t ra, uint64_t rb)
+{
+  return __rv_kadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t ddak_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_kadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kadd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddh.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddh.c
new file mode 100644
index 000000000000..93596c0fa92d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddh.c
@@ -0,0 +1,13 @@
+/* kaddh also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kaddh instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t hddak (int32_t ra, int32_t rb)
+{
+  return __rv_kaddh (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kaddh" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddw.c
new file mode 100644
index 000000000000..af478c31fd52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kaddw.c
@@ -0,0 +1,13 @@
+/* kaddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kaddw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t wddak (int32_t ra, int32_t rb)
+{
+  return __rv_kaddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kaddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras16.c
new file mode 100644
index 000000000000..1be710547f06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras16.c
@@ -0,0 +1,19 @@
+/* kcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarc (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sarck_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras32.c
new file mode 100644
index 000000000000..d486d3e00d85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcras32.c
@@ -0,0 +1,19 @@
+/* kcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarck (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sarck_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa16.c
new file mode 100644
index 000000000000..1d71c785ee05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa16.c
@@ -0,0 +1,19 @@
+/* kcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrck (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t asrck_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa32.c
new file mode 100644
index 000000000000..df14b0f23c07
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kcrsa32.c
@@ -0,0 +1,19 @@
+/* kcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrck (uint64_t ra, uint64_t rb)
+{
+  return __rv_kcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t asrck_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb.c
new file mode 100644
index 000000000000..d75c7bf6c681
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb.c
@@ -0,0 +1,19 @@
+/* kdmbb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t bbmdk (uint32_t ra, uint32_t rb)
+{
+  return __rv_kdmbb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t bbmdk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_kdmbb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb16.c
new file mode 100644
index 000000000000..6297b0546c61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbb16.c
@@ -0,0 +1,19 @@
+/* kdmbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbmdk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kdmbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbmdk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kdmbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt.c
new file mode 100644
index 000000000000..ec4a20178469
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt.c
@@ -0,0 +1,19 @@
+/* kdmbt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t tbmdk (uint32_t ra, uint32_t rb)
+{
+  return __rv_kdmbt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t tbmdk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_kdmbt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt16.c
new file mode 100644
index 000000000000..7381827fb8cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmbt16.c
@@ -0,0 +1,19 @@
+/* kdmbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmbt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tbmdk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kdmbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbmdk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kdmbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt.c
new file mode 100644
index 000000000000..5ab7de8d178a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt.c
@@ -0,0 +1,19 @@
+/* kdmtt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmtt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t ttmdk (uint32_t ra, uint32_t rb)
+{
+  return __rv_kdmtt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32_t ttmdk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_kdmtt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmtt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt16.c
new file mode 100644
index 000000000000..76b1e9658685
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kdmtt16.c
@@ -0,0 +1,19 @@
+/* kdmtt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kdmtt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttmdk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kdmtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttmdk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kdmtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kdmtt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm16.c
new file mode 100644
index 000000000000..7201f0ec1445
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm16.c
@@ -0,0 +1,19 @@
+/* khm16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khm16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t mhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khm16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t mhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khm16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khm16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm8.c
new file mode 100644
index 000000000000..b08dccc3109d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khm8.c
@@ -0,0 +1,19 @@
+/* khm8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khm8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t mhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khm8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t mhk_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_khm8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khm8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb.c
new file mode 100644
index 000000000000..1843eac684d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb.c
@@ -0,0 +1,19 @@
+/* khmbb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbmhk (uint32_t ra, uint32_t rb)
+{
+  return __rv_khmbb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t bbmhk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_khmbb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb16.c
new file mode 100644
index 000000000000..44dd26c0672c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbb16.c
@@ -0,0 +1,19 @@
+/* khmbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt.c
new file mode 100644
index 000000000000..a261d96a422d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt.c
@@ -0,0 +1,19 @@
+/* khmbt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbmhk (uint32_t ra, uint32_t rb)
+{
+  return __rv_khmbt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t tbmhk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_khmbt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt16.c
new file mode 100644
index 000000000000..392a441b5160
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmbt16.c
@@ -0,0 +1,19 @@
+/* khmbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmbt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tbmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt.c
new file mode 100644
index 000000000000..89ca750ecd33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt.c
@@ -0,0 +1,19 @@
+/* khmtt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmtt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttmhk (uint32_t ra, uint32_t rb)
+{
+  return __rv_khmtt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ttmhk_v (int16x2_t ra, int16x2_t rb)
+{
+  return __rv_v_khmtt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmtt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt16.c
new file mode 100644
index 000000000000..9bd88f3c62ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmtt16.c
@@ -0,0 +1,19 @@
+/* khmtt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmtt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmtt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx16.c
new file mode 100644
index 000000000000..b008a164fd58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx16.c
@@ -0,0 +1,19 @@
+/* khmx16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmx16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmx16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t xmhk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_khmx16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmx16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx8.c
new file mode 100644
index 000000000000..e62427faa841
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-khmx8.c
@@ -0,0 +1,19 @@
+/* khmx8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for khmx8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xmhk (uint64_t ra, uint64_t rb)
+{
+  return __rv_khmx8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t xmhk_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_khmx8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "khmx8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb.c
new file mode 100644
index 000000000000..f3f93fbf6e81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb.c
@@ -0,0 +1,19 @@
+/* kmabb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabb (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmabb (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb32.c
new file mode 100644
index 000000000000..024a9918980b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabb32.c
@@ -0,0 +1,19 @@
+/* kmabb32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabb32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabb32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t bbamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmabb32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabb32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt.c
new file mode 100644
index 000000000000..f8615b6f690b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt.c
@@ -0,0 +1,19 @@
+/* kmabt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabt (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmabt (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt32.c
new file mode 100644
index 000000000000..cc8ec0ad3c02
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmabt32.c
@@ -0,0 +1,19 @@
+/* kmabt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmabt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmabt32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t tbamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmabt32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmabt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada.c
new file mode 100644
index 000000000000..4f799af2712f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada.c
@@ -0,0 +1,19 @@
+/* kmada also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmada instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmada (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmada (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmada" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada32.c
new file mode 100644
index 000000000000..4eb0666ced5b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmada32.c
@@ -0,0 +1,19 @@
+/* kmada32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmada32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmada32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmada32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs.c
new file mode 100644
index 000000000000..952c20f9d744
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs.c
@@ -0,0 +1,19 @@
+/* kmadrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmadrs instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdamk (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmadrs (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t srdamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmadrs (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmadrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs32.c
new file mode 100644
index 000000000000..6a3ec8984d58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmadrs32.c
@@ -0,0 +1,19 @@
+/* kmadrs32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmadrs32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmadrs32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t srdamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmadrs32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmadrs32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads.c
new file mode 100644
index 000000000000..06268364f2a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads.c
@@ -0,0 +1,19 @@
+/* kmads also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmads instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdamk (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmads (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmads (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmads" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads32.c
new file mode 100644
index 000000000000..f9b7dc9f05a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmads32.c
@@ -0,0 +1,19 @@
+/* kmads32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmads32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmads32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmads32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmads32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmar64.c
new file mode 100644
index 000000000000..18029f74e618
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmar64.c
@@ -0,0 +1,19 @@
+/* kmar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ramk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmar64 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ramk2 (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmar64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt.c
new file mode 100644
index 000000000000..4d8fc8560133
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt.c
@@ -0,0 +1,19 @@
+/* kmatt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmatt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmatt (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmatt (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmatt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt32.c
new file mode 100644
index 000000000000..a6b94b60488b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmatt32.c
@@ -0,0 +1,19 @@
+/* kmatt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmatt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmatt32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ttamk_v (uint64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmatt32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmatt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda.c
new file mode 100644
index 000000000000..0e2dd29cb447
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda.c
@@ -0,0 +1,19 @@
+/* kmaxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxamk (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxda (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adxamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmaxda (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda32.c
new file mode 100644
index 000000000000..b10711907fc4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxda32.c
@@ -0,0 +1,19 @@
+/* kmaxda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxda32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxamk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmaxda32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds.c
new file mode 100644
index 000000000000..8437dba74bdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds.c
@@ -0,0 +1,19 @@
+/* kmaxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxds (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdxamk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmaxds (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds32.c
new file mode 100644
index 000000000000..a9cabf284706
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmaxds32.c
@@ -0,0 +1,19 @@
+/* kmaxds32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmaxds32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxamk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmaxds32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxamk_v (int32_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmaxds32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmaxds32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda.c
new file mode 100644
index 000000000000..6f940ace35ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda.c
@@ -0,0 +1,19 @@
+/* kmda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t admk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmda (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t admk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmda (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda32.c
new file mode 100644
index 000000000000..d98da686b74e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmda32.c
@@ -0,0 +1,19 @@
+/* kmda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t admk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmda32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t admk_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmda32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmac.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmac.c
new file mode 100644
index 000000000000..1b6e273e598e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmac.c
@@ -0,0 +1,19 @@
+/* kmmac also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmac instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t cammk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmac (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t cammk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmac (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmac" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmacu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmacu.c
new file mode 100644
index 000000000000..e30ab4ff2831
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmacu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmacu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ucammk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmac_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ucammk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmac_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmac.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb.c
new file mode 100644
index 000000000000..93638e4f557b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb.c
@@ -0,0 +1,19 @@
+/* kmmawb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2.c
new file mode 100644
index 000000000000..3a58b2493c7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2.c
@@ -0,0 +1,19 @@
+/* kmmawb2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawb2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb2 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb2 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2u.c
new file mode 100644
index 000000000000..15cc4865b40f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawb2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawb2.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2bwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb2_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2bwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb2_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawbu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawbu.c
new file mode 100644
index 000000000000..6831352972ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawbu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawb.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ubwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawb_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ubwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawb_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt.c
new file mode 100644
index 000000000000..7bd36727d645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt.c
@@ -0,0 +1,19 @@
+/* kmmawt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2.c
new file mode 100644
index 000000000000..1defba2b55d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2.c
@@ -0,0 +1,19 @@
+/* kmmawt2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmawt2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt2 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt2 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2u.c
new file mode 100644
index 000000000000..3cfab265307f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawt2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawt2.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2twammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt2_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2twammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt2_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawtu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawtu.c
new file mode 100644
index 000000000000..66b6e99d354b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmawtu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmawt.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t utwammk (int64_t rd, int64_t ra, uint64_t rb)
+{
+  return __rv_kmmawt_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t utwammk_v (int32x2_t rd, int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmawt_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmawt.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsb.c
new file mode 100644
index 000000000000..7e979d796002
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsb.c
@@ -0,0 +1,19 @@
+/* kmmsb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmsb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bsmmk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmsb (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bsmmk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmsb (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmsb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsbu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsbu.c
new file mode 100644
index 000000000000..14ad33e444ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmsbu.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmsbu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ubsmmk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmmsb_u (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bsmmk2 (int32x2_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmmsb_u (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmsb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2.c
new file mode 100644
index 000000000000..fc5c4fc323b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2.c
@@ -0,0 +1,19 @@
+/* kmmwb2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmwb2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwmmk (int64_t ra, int64_t rb)
+{
+  return __rv_kmmwb2 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwb2 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwb2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2u.c
new file mode 100644
index 000000000000..bf689e1bcbf8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwb2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmwb2u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2bwmmk (int64_t ra, int64_t rb)
+{
+  return __rv_kmmwb2_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2bwmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwb2_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwb2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2.c
new file mode 100644
index 000000000000..3ed4ce4c72e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2.c
@@ -0,0 +1,19 @@
+/* kmmwt2 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmmwt2 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twmmk (int64_t ra, uint64_t rb)
+{
+  return __rv_kmmwt2 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwt2 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwt2" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2u.c
new file mode 100644
index 000000000000..f5dafd50a4a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmmwt2u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kmmwt2u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u2twmmk (int64_t ra, uint64_t rb)
+{
+  return __rv_kmmwt2_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u2twmmk_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_kmmwt2_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmmwt2.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda.c
new file mode 100644
index 000000000000..0dd7481cc704
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda.c
@@ -0,0 +1,19 @@
+/* kmsda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsda (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adsmk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmsda (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda32.c
new file mode 100644
index 000000000000..bd96a6f53024
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsda32.c
@@ -0,0 +1,19 @@
+/* kmsda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsda32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adsmk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmsda32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsr64.c
new file mode 100644
index 000000000000..c83dbc666678
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsr64.c
@@ -0,0 +1,19 @@
+/* kmsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t rsmk (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_kmsr64 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t rsmk2 (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsr64" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda.c
new file mode 100644
index 000000000000..47a296608c1e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda.c
@@ -0,0 +1,19 @@
+/* kmsxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsxda (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adxsmk_v (int32x2_t rd, int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmsxda (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda32.c
new file mode 100644
index 000000000000..b4882d8d728d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmsxda32.c
@@ -0,0 +1,19 @@
+/* kmsxda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmsxda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxsmk (int64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_kmsxda32 (rd, ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxsmk_v (int64_t rd, int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmsxda32 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmsxda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda.c
new file mode 100644
index 000000000000..08a21cac0fb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda.c
@@ -0,0 +1,19 @@
+/* kmxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxmk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmxda (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t adxmk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_kmxda (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda32.c
new file mode 100644
index 000000000000..bab80fbd1ed8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kmxda32.c
@@ -0,0 +1,19 @@
+/* kmxda32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kmxda32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxmk (uint64_t ra, uint64_t rb)
+{
+  return __rv_kmxda32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t adxmk_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_kmxda32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kmxda32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll.c
new file mode 100644
index 000000000000..3f89cbcc3496
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll.c
@@ -0,0 +1,12 @@
+/* This is a test program for ksll instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t llsk (int32_t ra, uint32_t rb)
+{
+  return __rv_ksllw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksllw" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll16.c
new file mode 100644
index 000000000000..e4ca36910f80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll16.c
@@ -0,0 +1,19 @@
+/* ksll16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksll16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t llsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_ksll16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t llsk_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_ksll16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksll16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll32.c
new file mode 100644
index 000000000000..e957ffc64679
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksll32.c
@@ -0,0 +1,19 @@
+/* ksll32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksll32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t llsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_ksll32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t llsk_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_ksll32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksll32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslli.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslli.c
new file mode 100644
index 000000000000..bfc82eecdad7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslli.c
@@ -0,0 +1,12 @@
+/* This is a test program for kslli instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int32_t illsk (int32_t ra)
+{
+  return __rv_ksllw (ra, 8);
+}
+/* { dg-final { scan-assembler-times "kslliw" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16.c
new file mode 100644
index 000000000000..909d083c4da2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16.c
@@ -0,0 +1,19 @@
+/* kslra16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslra16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t arlsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_kslra16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t arlsk_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_kslra16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16u.c
new file mode 100644
index 000000000000..032274fb8864
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kslra16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u61arlsk (uint64_t ra, int32_t rb)
+{
+  return __rv_kslra16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t u61arlsk_v (int16x4_t ra, int32_t rb)
+{
+  return __rv_v_kslra16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32.c
new file mode 100644
index 000000000000..48002dd69367
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32.c
@@ -0,0 +1,19 @@
+/* kslra32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslra32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t arlsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_kslra32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t arlsk_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_kslra32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32u.c
new file mode 100644
index 000000000000..df034d0b9e99
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslra32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for kslra32.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23arlsk (uint64_t ra, uint32_t rb)
+{
+  return __rv_kslra32_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u23arlsk_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_kslra32_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslra32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslraw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslraw.c
new file mode 100644
index 000000000000..5df586c2b122
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslraw.c
@@ -0,0 +1,13 @@
+/* kslraw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslraw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t warlsk (int32_t ra, int32_t rb)
+{
+  return __rv_kslraw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslraw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslrawu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslrawu.c
new file mode 100644
index 000000000000..5df586c2b122
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kslrawu.c
@@ -0,0 +1,13 @@
+/* kslraw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kslraw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t warlsk (int32_t ra, int32_t rb)
+{
+  return __rv_kslraw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kslraw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub16.c
new file mode 100644
index 000000000000..14714b70a071
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub16.c
@@ -0,0 +1,19 @@
+/* ksub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busk (uint64_t ra, uint64_t rb)
+{
+  return __rv_ksub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t busk_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_ksub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub32.c
new file mode 100644
index 000000000000..e1af892ac8fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub32.c
@@ -0,0 +1,19 @@
+/* ksub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busk (uint64_t ra, uint64_t rb)
+{
+  return __rv_ksub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t busk_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_ksub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub64.c
new file mode 100644
index 000000000000..a0896cdf556f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub64.c
@@ -0,0 +1,13 @@
+/* ksub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t busk (int64_t ra, int64_t rb)
+{
+  return __rv_ksub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub8.c
new file mode 100644
index 000000000000..673230074fdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksub8.c
@@ -0,0 +1,19 @@
+/* ksub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busk (uint64_t ra, uint64_t rb)
+{
+  return __rv_ksub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t busk_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_ksub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubh.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubh.c
new file mode 100644
index 000000000000..4b0a0d9e63b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubh.c
@@ -0,0 +1,13 @@
+/* ksubh also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksubh instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int hbusk (int ra, int rb)
+{
+  return __rv_ksubh (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksubh" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubw.c
new file mode 100644
index 000000000000..af07ce051560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ksubw.c
@@ -0,0 +1,13 @@
+/* ksubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ksubw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int wbusk (int ra, int rb)
+{
+  return __rv_ksubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ksubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmul.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmul.c
new file mode 100644
index 000000000000..085c4b9ad850
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmul.c
@@ -0,0 +1,13 @@
+/* kwmmul also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for kwmmul instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t lummwk (int64_t ra, int64_t rb)
+{
+  return __rv_kwmmul (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kwmmul" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmulu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmulu.c
new file mode 100644
index 000000000000..27635b6d3ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-kwmmulu.c
@@ -0,0 +1,12 @@
+/* This is a test program for kwmmulu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ulummwk (int64_t ra, int64_t rb)
+{
+  return __rv_kwmmul_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "kwmmul.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-mfb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-mfb.c
new file mode 100644
index 000000000000..570f6c36e76e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-mfb.c
@@ -0,0 +1,39 @@
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+intXLEN_t foo(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+intXLEN_t foo1(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(intXLEN_t t, uintXLEN_t a, uintXLEN_t b) {
+  return __rv_umaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo3(int32xN_t t, int8xN_t a, int8xN_t b) {
+  return __rv_v_smaqa (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo4(int32xN_t t, int8xN_t a, uint8xN_t b) {
+  return __rv_v_smaqa_su (t, a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo5(uint32xN_t t, uint8xN_t a, uint8xN_t b) {
+  return __rv_v_umaqa (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaqa.su" 2 } } */
+/* { dg-final { scan-assembler-times "smaqa" 4 } } */
+/* { dg-final { scan-assembler-times "umaqa" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbb16.c
new file mode 100644
index 000000000000..56ad57db596d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbb16.c
@@ -0,0 +1,19 @@
+/* pkbb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bbkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pkbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t bbkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pkbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbt16.c
new file mode 100644
index 000000000000..3cbedf648400
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pkbt16.c
@@ -0,0 +1,19 @@
+/* pkbt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pkbt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tbkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pkbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t tbkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pkbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pkbt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktb16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktb16.c
new file mode 100644
index 000000000000..5cc4c83a64f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktb16.c
@@ -0,0 +1,19 @@
+/* pktb16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktb16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t btkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pktb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t btkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pktb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktb16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktt16.c
new file mode 100644
index 000000000000..637d2793b7ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-pktt16.c
@@ -0,0 +1,19 @@
+/* pktt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for pktt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttkp (uint64_t ra, uint64_t rb)
+{
+  return __rv_pktt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ttkp_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_pktt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "pktt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd16.c
new file mode 100644
index 000000000000..2e3131d2387b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd16.c
@@ -0,0 +1,19 @@
+/* radd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddar (uint64_t ra, uint64_t rb)
+{
+  return __rv_radd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ddar_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_radd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd32.c
new file mode 100644
index 000000000000..6443f7546c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd32.c
@@ -0,0 +1,19 @@
+/* radd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddar (uint64_t ra, uint64_t rb)
+{
+  return __rv_radd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ddar_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_radd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd64.c
new file mode 100644
index 000000000000..7adc8bb1b202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd64.c
@@ -0,0 +1,13 @@
+/* radd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ddar (int64_t ra, int64_t rb)
+{
+  return __rv_radd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd8.c
new file mode 100644
index 000000000000..c717ed8be8b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-radd8.c
@@ -0,0 +1,19 @@
+/* radd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddar (uint64_t ra, uint64_t rb)
+{
+  return __rv_radd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t ddar_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_radd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-raddw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-raddw.c
new file mode 100644
index 000000000000..f9ffea056c81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-raddw.c
@@ -0,0 +1,13 @@
+/* raddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for raddw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t wddar (int32_t ra, int32_t rb)
+{
+  return __rv_raddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "raddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras16.c
new file mode 100644
index 000000000000..a43231a4d9b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras16.c
@@ -0,0 +1,19 @@
+/* rcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t sarcr_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_rcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras32.c
new file mode 100644
index 000000000000..44ce8ae58871
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcras32.c
@@ -0,0 +1,19 @@
+/* rcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sarcr_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_rcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa16.c
new file mode 100644
index 000000000000..f16d22d67891
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa16.c
@@ -0,0 +1,19 @@
+/* rcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcrsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t asrcr_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_rcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa32.c
new file mode 100644
index 000000000000..f41b1ed0eccf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rcrsa32.c
@@ -0,0 +1,19 @@
+/* rcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t asrcr_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_rcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub16.c
new file mode 100644
index 000000000000..697bfb427f72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub16.c
@@ -0,0 +1,19 @@
+/* rsub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rsub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t busr_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_rsub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub32.c
new file mode 100644
index 000000000000..8a93bf505ee9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub32.c
@@ -0,0 +1,19 @@
+/* rsub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rsub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t busr_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_rsub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub64.c
new file mode 100644
index 000000000000..bb65b1a943c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub64.c
@@ -0,0 +1,13 @@
+/* rsub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t busr (int64_t ra, int64_t rb)
+{
+  return __rv_rsub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub8.c
new file mode 100644
index 000000000000..1912f277ce90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsub8.c
@@ -0,0 +1,19 @@
+/* rsub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busr (uint64_t ra, uint64_t rb)
+{
+  return __rv_rsub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t busr_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_rsub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsubw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsubw.c
new file mode 100644
index 000000000000..d765587c44ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-rsubw.c
@@ -0,0 +1,13 @@
+/* rsubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for rsubw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t wbusr (int32_t ra, int32_t rb)
+{
+  return __rv_rsubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "rsubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip16.c
new file mode 100644
index 000000000000..7829336cfe92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip16.c
@@ -0,0 +1,19 @@
+/* sclip16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sclip16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t pilcs (int64_t ra)
+{
+  return __rv_sclip16 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+int16x4_t pilcs_v (int16x4_t ra)
+{
+  return __rv_v_sclip16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "sclip16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip32.c
new file mode 100644
index 000000000000..cc933ce3439a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sclip32.c
@@ -0,0 +1,13 @@
+/* sclip32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t pilcs (int64_t ra)
+{
+  return __rv_sclip32 (ra, 5);
+}
+/* { dg-final { scan-assembler-times "sclip32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple16.c
new file mode 100644
index 000000000000..dd47b483537d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple16.c
@@ -0,0 +1,19 @@
+/* scmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t elpmcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple8.c
new file mode 100644
index 000000000000..e44b17d15771
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmple8.c
@@ -0,0 +1,19 @@
+/* scmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmple8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t elpmcs_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_scmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt16.c
new file mode 100644
index 000000000000..571e4a2218c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt16.c
@@ -0,0 +1,19 @@
+/* scmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t tlpmcs_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_scmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt8.c
new file mode 100644
index 000000000000..0f5e19fcc3b8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-scmplt8.c
@@ -0,0 +1,19 @@
+/* scmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for scmplt8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcs (uint64_t ra, uint64_t rb)
+{
+  return __rv_scmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t tlpmcs_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_scmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "scmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll16.c
new file mode 100644
index 000000000000..585abfa46a25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll16.c
@@ -0,0 +1,19 @@
+/* sll16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lls (uint64_t ra, uint32_t rb)
+{
+  return __rv_sll16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t lls_v (uint16x4_t ra, uint32_t rb)
+{
+  return __rv_v_sll16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll32.c
new file mode 100644
index 000000000000..3717363b65db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sll32.c
@@ -0,0 +1,19 @@
+/* sll32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sll32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lls (uint64_t ra, uint32_t rb)
+{
+  return __rv_sll32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t lls_v (uint32x2_t ra, uint32_t rb)
+{
+  return __rv_v_sll32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sll32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-slli32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-slli32.c
new file mode 100644
index 000000000000..a3782665191f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-slli32.c
@@ -0,0 +1,18 @@
+/* This is a test program for slli32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ills (uint64_t ra)
+{
+  return __rv_sll32 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ills_v (uint32x2_t ra)
+{
+  return __rv_v_sll32 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "slli32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smal.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smal.c
new file mode 100644
index 000000000000..a7dbe833c48b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smal.c
@@ -0,0 +1,19 @@
+/* smal also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smal instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t lams (int64_t ra, int64_t rb)
+{
+  return __rv_smal (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t lams_v (int64_t ra, int16x4_t rb)
+{
+  return __rv_v_smal (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smal" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbb.c
new file mode 100644
index 000000000000..0096799d3fd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbb.c
@@ -0,0 +1,20 @@
+/* smalbb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bblams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalbb (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t bblams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalbb (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalbb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbt.c
new file mode 100644
index 000000000000..3eb27a76102d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalbt.c
@@ -0,0 +1,20 @@
+/* smalbt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tblams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalbt (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t tblams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalbt (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalbt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalda.c
new file mode 100644
index 000000000000..261c33d6924e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalda.c
@@ -0,0 +1,20 @@
+/* smalda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaldrs.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaldrs.c
new file mode 100644
index 000000000000..1efd5d33b0eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaldrs.c
@@ -0,0 +1,20 @@
+/* smaldrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smaldrs instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smaldrs (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t srdlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smaldrs (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaldrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalds.c
new file mode 100644
index 000000000000..35393e049e57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalds.c
@@ -0,0 +1,20 @@
+/* smalds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaltt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaltt.c
new file mode 100644
index 000000000000..8250a84ce878
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smaltt.c
@@ -0,0 +1,20 @@
+/* smaltt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smaltt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smaltt (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t ttlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smaltt (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smaltt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxda.c
new file mode 100644
index 000000000000..0991fc915f91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxda.c
@@ -0,0 +1,20 @@
+/* smalxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalxda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalxda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxds.c
new file mode 100644
index 000000000000..8f9e7e2b32e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smalxds.c
@@ -0,0 +1,20 @@
+/* smalxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smalxds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxlams (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smalxds (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxlams_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smalxds (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smalxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smar64.c
new file mode 100644
index 000000000000..dee5c01adf8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smar64.c
@@ -0,0 +1,13 @@
+/* smar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t rams (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_smar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax16.c
new file mode 100644
index 000000000000..1cf0575444de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax16.c
@@ -0,0 +1,19 @@
+/* smax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xams (uint64_t ra, uint64_t rb)
+{
+  return __rv_smax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t xams_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax32.c
new file mode 100644
index 000000000000..fed71e33e59b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax32.c
@@ -0,0 +1,19 @@
+/* smax32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xams (uint64_t ra, uint64_t rb)
+{
+  return __rv_smax32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t xams_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smax32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax8.c
new file mode 100644
index 000000000000..4173151c666f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smax8.c
@@ -0,0 +1,19 @@
+/* smax8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smax8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xams (uint64_t ra, uint64_t rb)
+{
+  return __rv_smax8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t xams_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_smax8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smax8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb.c
new file mode 100644
index 000000000000..72e603d70af9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb.c
@@ -0,0 +1,18 @@
+/* This is a test program for smbb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbb16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bbms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smbb16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbb16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb32.c
new file mode 100644
index 000000000000..c3749f03454d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbb32.c
@@ -0,0 +1,19 @@
+/* smbb32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smbb32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbb32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t bbms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smbb32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbb32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt.c
new file mode 100644
index 000000000000..899eb98b80ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt.c
@@ -0,0 +1,18 @@
+/* This is a test program for smbt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t tbms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smbt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt32.c
new file mode 100644
index 000000000000..821d97c494bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smbt32.c
@@ -0,0 +1,19 @@
+/* smbt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smbt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t tbms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smbt32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t tbms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smbt32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smbt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs.c
new file mode 100644
index 000000000000..1908e9645cb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs.c
@@ -0,0 +1,19 @@
+/* smdrs also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smdrs instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smdrs (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t srdms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smdrs (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smdrs" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs32.c
new file mode 100644
index 000000000000..e4fd8fd6fb57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smdrs32.c
@@ -0,0 +1,19 @@
+/* smdrs32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smdrs32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t srdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smdrs32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t srdms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smdrs32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smdrs32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds.c
new file mode 100644
index 000000000000..4ced3400bbaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds.c
@@ -0,0 +1,19 @@
+/* smds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds32.c
new file mode 100644
index 000000000000..c14e265ba80b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smds32.c
@@ -0,0 +1,19 @@
+/* smds32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smds32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smds32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smds32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smds32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin16.c
new file mode 100644
index 000000000000..7466c61a8d50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin16.c
@@ -0,0 +1,19 @@
+/* smin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nims (uint64_t ra, uint64_t rb)
+{
+  return __rv_smin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t nims_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin32.c
new file mode 100644
index 000000000000..52560fd6565b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin32.c
@@ -0,0 +1,19 @@
+/* smin32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nims (uint64_t ra, uint64_t rb)
+{
+  return __rv_smin32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t nims_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smin32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin8.c
new file mode 100644
index 000000000000..55c5c4712dfd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smin8.c
@@ -0,0 +1,19 @@
+/* smin8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smin8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nims (uint64_t ra, uint64_t rb)
+{
+  return __rv_smin8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t nims_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_smin8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smin8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmul.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmul.c
new file mode 100644
index 000000000000..b65a3d3e9c65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmul.c
@@ -0,0 +1,13 @@
+/* smmul also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmul instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t lumms (int64_t ra, int64_t rb)
+{
+  return __rv_smmul (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmul" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmulu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmulu.c
new file mode 100644
index 000000000000..539883b33b68
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmulu.c
@@ -0,0 +1,12 @@
+/* This is a test program for smmul.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t u_lumms (int64_t ra, int64_t rb)
+{
+  return __rv_smmul_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmul.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwb.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwb.c
new file mode 100644
index 000000000000..6385c1976339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwb.c
@@ -0,0 +1,19 @@
+/* smmwb also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwb instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t bwmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwb (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t bwmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwb (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwbu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwbu.c
new file mode 100644
index 000000000000..a5f69059d6f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwbu.c
@@ -0,0 +1,18 @@
+/* This is a test program for smmwbu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ubwmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwb_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ubwmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwb_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwb.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwt.c
new file mode 100644
index 000000000000..dc470241e550
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwt.c
@@ -0,0 +1,19 @@
+/* smmwt also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smmwt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t twmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwt (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t twmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwt (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwtu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwtu.c
new file mode 100644
index 000000000000..da0aedd609c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smmwtu.c
@@ -0,0 +1,18 @@
+/* This is a test program for smmwtu instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t utwmms (int64_t ra, int64_t rb)
+{
+  return __rv_smmwt_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t utwmms_v (int32x2_t ra, int16x4_t rb)
+{
+  return __rv_v_smmwt_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smmwt.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslda.c
new file mode 100644
index 000000000000..484116863ed2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslda.c
@@ -0,0 +1,20 @@
+/* smslda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adlsms (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smslda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adlsms_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smslda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smslda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslxda.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslxda.c
new file mode 100644
index 000000000000..32b946e13eca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smslxda.c
@@ -0,0 +1,20 @@
+/* smslxda also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smslxda instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t adxlsms (int64_t t, uint64_t a, uint64_t b)
+{
+  return __rv_smslxda (t, a, b);
+}
+
+static __attribute__ ((noinline))
+int64_t adxlsms_v (int64_t t, int16x4_t a, int16x4_t b)
+{
+  return __rv_v_smslxda (t, a, b);
+}
+
+/* { dg-final { scan-assembler-times "smslxda" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smsr64.c
new file mode 100644
index 000000000000..9b60a892a4d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smsr64.c
@@ -0,0 +1,13 @@
+/* smsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t rsms (int64_t rd, int64_t ra, int64_t rb)
+{
+  return __rv_smsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "smsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt.c
new file mode 100644
index 000000000000..5bfafdf336dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt.c
@@ -0,0 +1,18 @@
+/* This is a test program for smtt instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smtt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smtt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smtt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt32.c
new file mode 100644
index 000000000000..9bf98d31f6d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smtt32.c
@@ -0,0 +1,19 @@
+/* smtt32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smtt32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ttms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smtt32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t ttms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smtt32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smtt32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smulx.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smulx.c
new file mode 100644
index 000000000000..03a42888cd97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smulx.c
@@ -0,0 +1,57 @@
+/* smtt32 also appears on filename, so scan-assembler-times plus 1 */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zprv_zpsf -mabi=lp64d -O0" } */#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ttms (uint32_t a, uint32_t b)
+{
+  return __rv_smul8 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ttms_v (int8x4_t a, int8x4_t b)
+{
+  return __rv_v_smul8 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint64_t ttmsx (uint32_t a, uint32_t b)
+{
+  return __rv_smulx8 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ttmsx_v (int8x4_t a, int8x4_t b)
+{
+  return __rv_v_smulx8 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint64_t ttms2 (uint32_t a, uint32_t b)
+{
+  return __rv_smul16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttms_v2 (int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smul16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint64_t xttms2 (uint32_t a, uint32_t b)
+{
+  return __rv_smulx16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ttmsx_v2 (int16x2_t a, int16x2_t b)
+{
+  return __rv_v_smulx16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "smul8" 2 } } */
+/* { dg-final { scan-assembler-times "smulx8" 2 } } */
+/* { dg-final { scan-assembler-times "smul16" 2 } } */
+/* { dg-final { scan-assembler-times "smulx16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds.c
new file mode 100644
index 000000000000..d9c9a6eaf690
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds.c
@@ -0,0 +1,19 @@
+/* smxds also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smxds instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smxds (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t sdxms_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_smxds (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smxds" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds32.c
new file mode 100644
index 000000000000..caccefe116d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-smxds32.c
@@ -0,0 +1,19 @@
+/* smxds32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for smxds32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t sdxms (uint64_t ra, uint64_t rb)
+{
+  return __rv_smxds32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int64_t sdxms_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_smxds32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "smxds32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16.c
new file mode 100644
index 000000000000..7e98cd27525f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16.c
@@ -0,0 +1,19 @@
+/* sra16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t ars_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16u.c
new file mode 100644
index 000000000000..be4490a4cdcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for sra16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u61ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t u61ars_v (int16x4_t ra, uint32_t rb)
+{
+  return __rv_v_sra16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32.c
new file mode 100644
index 000000000000..56112451613a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32.c
@@ -0,0 +1,19 @@
+/* sra32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sra32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t ars_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32u.c
new file mode 100644
index 000000000000..a40dbe37c955
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sra32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for sra32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23ars (uint64_t ra, uint32_t rb)
+{
+  return __rv_sra32_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u23ars_v (int32x2_t ra, uint32_t rb)
+{
+  return __rv_v_sra32_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16.c
new file mode 100644
index 000000000000..5c92f64832e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t iars (uint64_t ra)
+{
+  return __rv_sra16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x4_t iars_v (int16x4_t ra)
+{
+  return __rv_v_sra16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16u.c
new file mode 100644
index 000000000000..fe2a374d91f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u61iars (uint64_t ra)
+{
+  return __rv_sra16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int16x4_t u61iars_v (int16x4_t ra)
+{
+  return __rv_v_sra16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32.c
new file mode 100644
index 000000000000..e5654c9fd8bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t iars (uint64_t ra)
+{
+  return __rv_sra32 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int32x2_t iars_v (int32x2_t ra)
+{
+  return __rv_v_sra32 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32u.c
new file mode 100644
index 000000000000..26ec45373b6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srai32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srai32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23iars (uint64_t ra)
+{
+  return __rv_sra32_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+int32x2_t u23iars_v (int32x2_t ra)
+{
+  return __rv_v_sra32_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srai32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sraiu.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sraiu.c
new file mode 100644
index 000000000000..c037f7bddb7d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sraiu.c
@@ -0,0 +1,12 @@
+/* This is a test program for srai.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t uiars (int64_t ra)
+{
+  return __rv_sra_u (ra, 8);
+}
+/* { dg-final { scan-assembler-times "srai.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srau.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srau.c
new file mode 100644
index 000000000000..f5df3067bc66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srau.c
@@ -0,0 +1,12 @@
+/* This is a test program for sra.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t uars (int64_t ra, uint32_t rb)
+{
+  return __rv_sra_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sra.u" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16.c
new file mode 100644
index 000000000000..8cbce03f4762
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16.c
@@ -0,0 +1,19 @@
+/* srl16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t lrs_v (uint16x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16u.c
new file mode 100644
index 000000000000..84f83af3241a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srl16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u_61lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl16_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t u_61lrs_v (uint16x4_t ra, uint32_t rb)
+{
+  return __rv_v_srl16_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32.c
new file mode 100644
index 000000000000..fc3301e5ff72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32.c
@@ -0,0 +1,19 @@
+/* srl32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for srl32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t lrs_v (uint32x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32u.c
new file mode 100644
index 000000000000..b2cdcdcb956d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srl32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srl32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23lrs (uint64_t ra, uint32_t rb)
+{
+  return __rv_srl32_u (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t u23lrs_v (uint32x2_t ra, uint32_t rb)
+{
+  return __rv_v_srl32_u (ra, rb);
+}
+/* { dg-final { scan-assembler-times "srl32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16.c
new file mode 100644
index 000000000000..8adef29a0c2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16.c
@@ -0,0 +1,18 @@
+/* This is a test program for srli16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ilrs (uint64_t ra)
+{
+  return __rv_srl16 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ilrs_v (uint16x4_t ra)
+{
+  return __rv_v_srl16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16u.c
new file mode 100644
index 000000000000..41753750bc33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli16u.c
@@ -0,0 +1,18 @@
+/* This is a test program for sril16.u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u_61ilrs (uint64_t ra)
+{
+  return __rv_srl16_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t u_61ilrs_v (uint16x4_t ra)
+{
+  return __rv_v_srl16_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli16.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32.c
new file mode 100644
index 000000000000..6c495f1b55a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32.c
@@ -0,0 +1,18 @@
+/* This is a test program for srli32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ilrs (uint64_t ra)
+{
+  return __rv_srl32 (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ilrs_v (uint32x2_t ra)
+{
+  return __rv_v_srl32 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32u.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32u.c
new file mode 100644
index 000000000000..f35af1d7e975
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-srli32u.c
@@ -0,0 +1,18 @@
+/* This is a test program for srli32u instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t u23ilrs (uint64_t ra)
+{
+  return __rv_srl32_u (ra, 4);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t u23ilrs_v (uint32x2_t ra)
+{
+  return __rv_v_srl32_u (ra, 4);
+}
+/* { dg-final { scan-assembler-times "srli32.u" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas16.c
new file mode 100644
index 000000000000..a8ce6e864707
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas16.c
@@ -0,0 +1,68 @@
+/* stas16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stas16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo21(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo31(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo8(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstas16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo9(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstas16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stas16" 12 } } */
+/* { dg-final { scan-assembler-times "rstas16" 4 } } */
+/* { dg-final { scan-assembler-times "urstas16" 2 } } */
+/* { dg-final { scan-assembler-times "kstas16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstas16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas32.c
new file mode 100644
index 000000000000..f105833d7206
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stas32.c
@@ -0,0 +1,70 @@
+/* stas32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stas32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+typedef uint32x2_t uint32xN_t;
+typedef int32x2_t int32xN_t;
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo4(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ustas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo5(int32xN_t a, int32xN_t b) {
+  return __rv_v_sstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo6(int32xN_t a, int32xN_t b) {
+  return __rv_v_rstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo7(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_urstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo9(int32xN_t a, int32xN_t b) {
+  return __rv_v_kstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstas32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo11(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ukstas32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stas32" 12 } } */
+/* { dg-final { scan-assembler-times "rstas32" 4 } } */
+/* { dg-final { scan-assembler-times "urstas32" 2 } } */
+/* { dg-final { scan-assembler-times "kstas32" 4 } } */
+/* { dg-final { scan-assembler-times "ukstas32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa16.c
new file mode 100644
index 000000000000..f9d470df58f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa16.c
@@ -0,0 +1,68 @@
+/* stsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo4(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ustsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo5(int16xN_t a, int16xN_t b) {
+  return __rv_v_sstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo6(int16xN_t a, int16xN_t b) {
+  return __rv_v_rstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo7(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_urstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+int16xN_t foo9(int16xN_t a, int16xN_t b) {
+  return __rv_v_kstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstsa16 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint16xN_t foo11(uint16xN_t a, uint16xN_t b) {
+  return __rv_v_ukstsa16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stsa16" 12 } } */
+/* { dg-final { scan-assembler-times "rstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "urstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "kstsa16" 4 } } */
+/* { dg-final { scan-assembler-times "ukstsa16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa32.c
new file mode 100644
index 000000000000..98a32e6d64bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-stsa32.c
@@ -0,0 +1,70 @@
+/* stsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for stsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+typedef uint32x2_t uint32xN_t;
+typedef int32x2_t int32xN_t;
+
+static __attribute__ ((noinline))
+uintXLEN_t foo(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_stsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_rstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo3(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_urstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo4(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ustsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo5(int32xN_t a, int32xN_t b) {
+  return __rv_v_sstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo6(int32xN_t a, int32xN_t b) {
+  return __rv_v_rstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo7(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_urstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_kstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+int32xN_t foo9(int32xN_t a, int32xN_t b) {
+  return __rv_v_kstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a, uintXLEN_t b) {
+  return __rv_ukstsa32 (a, b);
+}
+
+static __attribute__ ((noinline))
+uint32xN_t foo11(uint32xN_t a, uint32xN_t b) {
+  return __rv_v_ukstsa32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "stsa32" 12 } } */
+/* { dg-final { scan-assembler-times "rstsa32" 4 } } */
+/* { dg-final { scan-assembler-times "urstsa32" 2 } } */
+/* { dg-final { scan-assembler-times "kstsa32" 4 } } */
+/* { dg-final { scan-assembler-times "ukstsa32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub16.c
new file mode 100644
index 000000000000..f52ad51e9bf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub16.c
@@ -0,0 +1,25 @@
+/* sub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bus (uint64_t ra, uint64_t rb)
+{
+  return __rv_sub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t busu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_usub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int16x4_t buss_v (int16x4_t ra, int16x4_t rb)
+{
+  return __rv_v_ssub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub16" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub32.c
new file mode 100644
index 000000000000..1bef6603149e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub32.c
@@ -0,0 +1,25 @@
+/* sub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bus (uint64_t ra, uint64_t rb)
+{
+  return __rv_sub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t busu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_usub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int32x2_t buss_v (int32x2_t ra, int32x2_t rb)
+{
+  return __rv_v_ssub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub32" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub8.c
new file mode 100644
index 000000000000..b05bd891388f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sub8.c
@@ -0,0 +1,25 @@
+/* sub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t bus (uint64_t ra, uint64_t rb)
+{
+  return __rv_sub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t busu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_usub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+int8x8_t buss_v (int8x8_t ra, int8x8_t rb)
+{
+  return __rv_v_ssub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "sub8" 4 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd810.c
new file mode 100644
index 000000000000..27e2703ba20a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd810.c
@@ -0,0 +1,19 @@
+/* sunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd810 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd820.c
new file mode 100644
index 000000000000..fb017348a77c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd820.c
@@ -0,0 +1,19 @@
+/* sunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd820 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd830.c
new file mode 100644
index 000000000000..2814b8d30b0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd830.c
@@ -0,0 +1,19 @@
+/* sunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd830 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd831.c
new file mode 100644
index 000000000000..905c2a951389
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd831.c
@@ -0,0 +1,19 @@
+/* sunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd831 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd832.c
new file mode 100644
index 000000000000..bf4bcddb5ae3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-sunpkd832.c
@@ -0,0 +1,19 @@
+/* sunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sunpkd832 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnus (uint64_t a)
+{
+  return __rv_sunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+int16x4_t dkpnus_v (int8x8_t a)
+{
+  return __rv_v_sunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "sunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-swap16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-swap16.c
new file mode 100644
index 000000000000..4004b815a2c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-swap16.c
@@ -0,0 +1,17 @@
+/* This is a test program for swap16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t paws (uint64_t a)
+{
+  return __rv_swap16 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t paws_v (uint16x4_t a)
+{
+  return __rv_v_swap16 (a);
+}
+/* { dg-final { scan-assembler-times "pkbt16" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip16.c
new file mode 100644
index 000000000000..05d0a0c50b31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip16.c
@@ -0,0 +1,19 @@
+/* uclip16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uclip16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t pilcu (uint64_t ra)
+{
+  return __rv_uclip16 (ra, 2);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t pilcu_v (int16x4_t ra)
+{
+  return __rv_v_uclip16 (ra, 4);
+}
+/* { dg-final { scan-assembler-times "uclip16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip32.c
new file mode 100644
index 000000000000..ef4e5693d6a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uclip32.c
@@ -0,0 +1,13 @@
+/* uclip32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t pilcu (int64_t ra)
+{
+  return __rv_uclip32 (ra, 5);
+}
+/* { dg-final { scan-assembler-times "uclip32" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple16.c
new file mode 100644
index 000000000000..673aa4150532
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple16.c
@@ -0,0 +1,19 @@
+/* ucmple16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmple16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t elpmcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucmple16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple8.c
new file mode 100644
index 000000000000..f4d4a98ad579
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmple8.c
@@ -0,0 +1,19 @@
+/* ucmple8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmple8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t elpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmple8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t elpmcu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ucmple8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmple8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt16.c
new file mode 100644
index 000000000000..ca4c8db5b7f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt16.c
@@ -0,0 +1,19 @@
+/* ucmplt16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmplt16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t tlpmcu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ucmplt16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt8.c
new file mode 100644
index 000000000000..b3d35c26b4ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ucmplt8.c
@@ -0,0 +1,19 @@
+/* ucmplt8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ucmplt8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t tlpmcu (uint64_t ra, uint64_t rb)
+{
+  return __rv_ucmplt8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t tlpmcu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ucmplt8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ucmplt8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd16.c
new file mode 100644
index 000000000000..17480ec10e3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd16.c
@@ -0,0 +1,19 @@
+/* ukadd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ddaku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ukadd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd32.c
new file mode 100644
index 000000000000..92d442be68c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd32.c
@@ -0,0 +1,19 @@
+/* ukadd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukadd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ddaku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ukadd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd64.c
new file mode 100644
index 000000000000..52353505cb98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd64.c
@@ -0,0 +1,13 @@
+/* ukadd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukadd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd8.c
new file mode 100644
index 000000000000..0942254f4eca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukadd8.c
@@ -0,0 +1,19 @@
+/* ukadd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for add8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukadd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t ddaku_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ukadd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukadd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras16.c
new file mode 100644
index 000000000000..0ae424e61d92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras16.c
@@ -0,0 +1,19 @@
+/* ukcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for cras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t sarcku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ukcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras32.c
new file mode 100644
index 000000000000..0ace36560768
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcras32.c
@@ -0,0 +1,19 @@
+/* ukcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t sarcku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ukcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa16.c
new file mode 100644
index 000000000000..fdee2d00d893
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa16.c
@@ -0,0 +1,19 @@
+/* ukcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for crsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t asrcku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ukcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa32.c
new file mode 100644
index 000000000000..5cb7b2e73f7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukcrsa32.c
@@ -0,0 +1,19 @@
+/* ukcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcku (uint64_t ra, uint64_t rb)
+{
+  return __rv_ukcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t asrcku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ukcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmar64.c
new file mode 100644
index 000000000000..603ae68c78ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmar64.c
@@ -0,0 +1,13 @@
+/* ukmar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukmar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ramku (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_ukmar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukmar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmsr64.c
new file mode 100644
index 000000000000..ff56edec0e5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ukmsr64.c
@@ -0,0 +1,13 @@
+/* ukmsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ukmsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t rsmku (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_ukmsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "ukmsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub16.c
new file mode 100644
index 000000000000..05b9605f6b97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub16.c
@@ -0,0 +1,19 @@
+/* uksub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t busku_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_uksub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub32.c
new file mode 100644
index 000000000000..27a112f655c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub32.c
@@ -0,0 +1,19 @@
+/* uksub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uksub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t busku_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_uksub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub64.c
new file mode 100644
index 000000000000..59f9736f7b53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub64.c
@@ -0,0 +1,13 @@
+/* uksub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uksub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub8.c
new file mode 100644
index 000000000000..1b7f4d6d6d72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uksub8.c
@@ -0,0 +1,19 @@
+/* uksub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for sub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busku (uint64_t ra, uint64_t rb)
+{
+  return __rv_uksub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t busku_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_uksub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uksub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umar64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umar64.c
new file mode 100644
index 000000000000..d057cec333c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umar64.c
@@ -0,0 +1,13 @@
+/* umar64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umar64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ramu (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_umar64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "umar64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax16.c
new file mode 100644
index 000000000000..a6ee2feffa9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax16.c
@@ -0,0 +1,19 @@
+/* umax16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xamu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umax16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t xamu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_umax16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax32.c
new file mode 100644
index 000000000000..f8aa8688e5ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax32.c
@@ -0,0 +1,19 @@
+/* umax32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xamu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umax32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t xamu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_umax32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax8.c
new file mode 100644
index 000000000000..f0ab97956a46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umax8.c
@@ -0,0 +1,19 @@
+/* umax8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umax8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t xamu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umax8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t xamu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_umax8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umax8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin16.c
new file mode 100644
index 000000000000..90429268ea98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin16.c
@@ -0,0 +1,19 @@
+/* umin16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nimu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umin16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t nimu_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_umin16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin32.c
new file mode 100644
index 000000000000..908f0b2541f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin32.c
@@ -0,0 +1,19 @@
+/* umin32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nimu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umin32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t nimu_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_umin32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin8.c
new file mode 100644
index 000000000000..93c22d612a2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umin8.c
@@ -0,0 +1,19 @@
+/* umin8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umin8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t nimu (uint64_t ra, uint64_t rb)
+{
+  return __rv_umin8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t nimu_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_umin8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "umin8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umsr64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umsr64.c
new file mode 100644
index 000000000000..262f636b7360
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-umsr64.c
@@ -0,0 +1,13 @@
+/* umsr64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for umsr64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t rsmu (uint64_t rd, uint64_t ra, uint64_t rb)
+{
+  return __rv_umsr64 (rd, ra, rb);
+}
+/* { dg-final { scan-assembler-times "umsr64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd16.c
new file mode 100644
index 000000000000..e363f07d8f24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd16.c
@@ -0,0 +1,19 @@
+/* uradd16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t ddaru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_uradd16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd32.c
new file mode 100644
index 000000000000..e6fe41fbc9da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd32.c
@@ -0,0 +1,19 @@
+/* uradd32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t ddaru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_uradd32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd64.c
new file mode 100644
index 000000000000..7adc8bb1b202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd64.c
@@ -0,0 +1,13 @@
+/* radd64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for radd64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t ddar (int64_t ra, int64_t rb)
+{
+  return __rv_radd64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "radd64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd8.c
new file mode 100644
index 000000000000..846fae2c049a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uradd8.c
@@ -0,0 +1,19 @@
+/* uradd8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uradd8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t ddaru (uint64_t ra, uint64_t rb)
+{
+  return __rv_uradd8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t ddaru_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_uradd8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uradd8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uraddw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uraddw.c
new file mode 100644
index 000000000000..90359456fa2c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-uraddw.c
@@ -0,0 +1,13 @@
+/* uraddw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for uraddw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t wddaru (uint32_t ra, uint32_t rb)
+{
+  return __rv_uraddw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "uraddw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras16.c
new file mode 100644
index 000000000000..8f699528deeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras16.c
@@ -0,0 +1,19 @@
+/* urcras16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcras16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcras16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t sarcru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_urcras16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcras16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras32.c
new file mode 100644
index 000000000000..7b7ac9b7281f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcras32.c
@@ -0,0 +1,19 @@
+/* urcras32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcras32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t sarcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcras32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t sarcru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_urcras32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcras32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa16.c
new file mode 100644
index 000000000000..fc82fa3ed6dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa16.c
@@ -0,0 +1,19 @@
+/* urcrsa16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcrsa16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcrsa16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t asrcru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_urcrsa16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcrsa16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa32.c
new file mode 100644
index 000000000000..078c2f93c82d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-urcrsa32.c
@@ -0,0 +1,19 @@
+/* urcrsa32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for urcrsa32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t asrcru (uint64_t ra, uint64_t rb)
+{
+  return __rv_urcrsa32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t asrcru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_urcrsa32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "urcrsa32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub16.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub16.c
new file mode 100644
index 000000000000..07ad516a08c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub16.c
@@ -0,0 +1,19 @@
+/* ursub16 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub16 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub16 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t busru_v (uint16x4_t ra, uint16x4_t rb)
+{
+  return __rv_v_ursub16 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub16" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub32.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub32.c
new file mode 100644
index 000000000000..e76640c3aa00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub32.c
@@ -0,0 +1,19 @@
+/* ursub32 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub32 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub32 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint32x2_t busru_v (uint32x2_t ra, uint32x2_t rb)
+{
+  return __rv_v_ursub32 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub32" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub64.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub64.c
new file mode 100644
index 000000000000..63596eab8021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub64.c
@@ -0,0 +1,13 @@
+/* ursub64 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub64 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub64 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub64" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub8.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub8.c
new file mode 100644
index 000000000000..79bdd1ce4e50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursub8.c
@@ -0,0 +1,19 @@
+/* ursub8 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursub8 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t busru (uint64_t ra, uint64_t rb)
+{
+  return __rv_ursub8 (ra, rb);
+}
+
+static __attribute__ ((noinline))
+uint8x8_t busru_v (uint8x8_t ra, uint8x8_t rb)
+{
+  return __rv_v_ursub8 (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursub8" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursubw.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursubw.c
new file mode 100644
index 000000000000..8e45b8c2b9fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-ursubw.c
@@ -0,0 +1,13 @@
+/* ursubw also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for ursubw instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint32_t wbusru (uint32_t ra, uint32_t rb)
+{
+  return __rv_ursubw (ra, rb);
+}
+/* { dg-final { scan-assembler-times "ursubw" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-wext.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-wext.c
new file mode 100644
index 000000000000..8ecff709e4d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-wext.c
@@ -0,0 +1,13 @@
+/* wext also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for wext instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+int64_t txew (uint64_t ra, uint32_t rb)
+{
+  return __rv_wext (ra, rb);
+}
+/* { dg-final { scan-assembler-times "wext" 2 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zbpbo.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zbpbo.c
new file mode 100644
index 000000000000..3190ed8004d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zbpbo.c
@@ -0,0 +1,80 @@
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zbpbo_zpn_zpsf -mabi=lp64d -O0" } */#include <rvp_intrinsic.h>
+
+static __attribute__ ((noinline))
+uintXLEN_t foo2 (uintXLEN_t a, uintXLEN_t b, uintXLEN_t c)
+{
+  return __rv_cmix (a, b, c);
+}
+
+static __attribute__ ((noinline))
+uint32_t foo3(uint32_t a, uint32_t b, uint32_t c)
+{
+  return __rv_fsrw (a, b, c);
+}
+
+static __attribute__ ((noinline))
+int32_t foo5(int32_t a, int32_t b)
+{
+  return __rv_max (a, b);
+}
+
+static __attribute__ ((noinline))
+int32_t foo6(int32_t a, int32_t b)
+{
+  return __rv_min (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo7(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_pack (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo8(uintXLEN_t a, uintXLEN_t b)
+{
+  return __rv_packu (a, b);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo9(uintXLEN_t a)
+{
+  return __rv_rev (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo10(uintXLEN_t a)
+{
+  return __rv_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo11(uint8xN_t a)
+{
+  return __rv_v_rev8h (a);
+}
+
+static __attribute__ ((noinline))
+uintXLEN_t foo12(uintXLEN_t a)
+{
+  return __rv_swap8 (a);
+}
+
+static __attribute__ ((noinline))
+uint8xN_t foo13(uint8xN_t a)
+{
+  return __rv_v_swap8 (a);
+}
+
+/* { dg-final { scan-assembler-times "rev8.h" 4 } } */
+/* { dg-final { scan-assembler-times "rev" 5 } } */
+/* { dg-final { scan-assembler-times "pack" 2 } } */
+/* { dg-final { scan-assembler-times "packu" 1 } } */
+/* { dg-final { scan-assembler-times "fsrw" 1 } } */
+/* { dg-final { scan-assembler-times "min" 1 } } */
+/* { dg-final { scan-assembler-times "max" 1 } } */
+/* { dg-final { scan-assembler-times "cmix" 1 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
+/* { dg-final { scan-assembler-times "maxw" 0 } } */
+/* { dg-final { scan-assembler-times "minw" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd810.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd810.c
new file mode 100644
index 000000000000..90db21e60810
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd810.c
@@ -0,0 +1,19 @@
+/* zunpkd810 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd810 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd810 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd810 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd810" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd820.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd820.c
new file mode 100644
index 000000000000..ad09ee48935e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd820.c
@@ -0,0 +1,19 @@
+/* zunpkd820 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd820 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd820 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd820 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd820" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd830.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd830.c
new file mode 100644
index 000000000000..47a2adee0df8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd830.c
@@ -0,0 +1,19 @@
+/* zunpkd830 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd830 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd830 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd830 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd830" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd831.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd831.c
new file mode 100644
index 000000000000..b287a6760600
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd831.c
@@ -0,0 +1,19 @@
+/* zunpkd831 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd831 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd831 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd831 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd831" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd832.c b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd832.c
new file mode 100644
index 000000000000..ffd109ee40f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/builtin-rvp64-zunpkd832.c
@@ -0,0 +1,19 @@
+/* zunpkd832 also appears on filename, so scan-assembler-times plus 1 */
+/* This is a test program for zunpkd832 instruction.  */
+/* { dg-do compile { target riscv64*-*-* } } */
+/* { dg-options "-march=rv64gc_zpn_zpsf -mabi=lp64d -O0" } */
+#include <rvp_intrinsic.h>
+#include <stdlib.h>
+static __attribute__ ((noinline))
+uint64_t dkpnuz (uint64_t a)
+{
+  return __rv_zunpkd832 (a);
+}
+
+static __attribute__ ((noinline))
+uint16x4_t dkpnuz_v (uint8x8_t a)
+{
+  return __rv_v_zunpkd832 (a);
+}
+/* { dg-final { scan-assembler-times "zunpkd832" 3 } } */
+/* { dg-final { scan-assembler-times "builtin_riscv" 0 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvp64_scan/rvp64.exp b/gcc/testsuite/gcc.target/riscv/rvp64_scan/rvp64.exp
new file mode 100644
index 000000000000..6e7aecba3c91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvp64_scan/rvp64.exp
@@ -0,0 +1,42 @@
+
+# Copyright (C) 2017-2020 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+    set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \
+	"" $DEFAULT_CFLAGS
+
+# All done.
+dg-finish
\ No newline at end of file