From 82035e75dad0db0391ea8e935c90d774c4ec7407 Mon Sep 17 00:00:00 2001
From: Lin Sinan <sinan@isrc.iscas.ac.cn>
Date: Tue, 11 May 2021 02:07:44 +0300
Subject: [PATCH] [Hook] Add even-odd pair of register support in
 TARGET_HARD_REGNO_MODE_OK hook

---
 gcc/config/riscv/riscv.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 5b0b1419afe5..62c5272b4d26 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4516,6 +4516,14 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 	!= call_used_or_fixed_reg_p (regno + i))
       return false;
 
+  /* use even/odd pair of registers in rv32 zpsf subset */
+  if (TARGET_ZPSF && !TARGET_64BIT)
+    {
+      if ((GET_MODE_CLASS (mode) == MODE_INT || 
+          GET_MODE_CLASS (mode) == MODE_VECTOR_INT) &&
+          GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DImode))
+        return !(regno & 1);
+    }
   return true;
 }