diff --git a/Zc-specification/Zc.adoc b/Zc-specification/Zc.adoc
index 4bd996b..391f120 100644
--- a/Zc-specification/Zc.adoc
+++ b/Zc-specification/Zc.adoc
@@ -11,6 +11,7 @@
 [width="100%",options=header]
 |====================================================================================
 |Version  | change
+|v1.0.4-3    | Added misa.C clarification
 |v1.0.4-2    | Added rule that C implies Zca, Zcf, Zcd - discussed in https://github.com/riscv/riscv-isa-manual/issues/1132
 |v1.0.4-1    | Added rule that Zcf implies F and Zcd implies D - discussed in https://github.com/riscv/riscv-code-size-reduction/issues/221
 
@@ -120,6 +121,22 @@ Therefore common ISA strings can be updated as follows to include the relevant Z
 * RV32IMC becomes RV32IM_Zce
 * RV32IMCF becomes RV32IMF_Zce
 
+[#misaC]
+=== MISA.C
+
+If all the instructions from the C extension are present, and the MISA CSR, has been implemented, then MISA.C is set. This happens if the following extensions are selected:
+
+* Zca and not F
+* Zca, Zcf and F is specified (RV32 only)
+* Zca, Zcf and Zcd if D is specified (RV32 only)
+** this configuration excludes Zcmp, Zcmt
+* Zca, Zcd if D is specified (RV64 only)
+** this configuration excludes Zcmp, Zcmt
+
+Therefore MISA.C can be set without directly specifying the C extension.
+
+Specifying Zce sets MISA.C if D is not implemented. If D _is_ implemented then Zce does _not_ set MISA.C as it cannot include Zcd because some of the encodings have been repurposed by Zcmp and Zcmt.
+
 [#Zca]
 === Zca